MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

250 Chapter 14.
24 23 22 21 20 19 18 17 16
0 BEV TS SR NMI
CH CE DE
Figure 14-12 Diagnostic Status Field
Table 14-11 Status Register Diagnostic Status Bits
Bit Description
BEV
Controls the location of TLB refill and general exception
vectors.
0 → normal
1→ bootstrap
This bit is set when a TLB write presents an entry that matches
any other virtual page entry in the TLB. Should this occur,
any TLB entries that allow multiple matches, even in the
Wired area, are invalidated before this new entry can be
TS
written into the TLB. This prevents multiple matches during
address translation.
0 → normal
1→ TLB shutdown has occurred.
SR 1→ Indicates a Soft Reset or NMI exception.
NMI
1→ Indicates a nonmaskable interrupt has occurred. Used to
distinguish between a Soft Reset and a nonmaskable interrupt
in a Soft Reset exception.
Hit (tag match and valid state) or miss indication for last
CACHE Hit Invalidate, Hit Write Back Invalidate for a
CH secondary cache.
0 → miss
1 → hit
CE Reserved in the R10000, and should be set to 0.
DE
0
2 1 1 1 1 1 1 1
Specifies that cache parity or ECC errors cannot cause
exceptions.
0 → parity/ECC remain enabled
1 → disables parity/ECC
Reserved. Must be written as zeroes, and returns zeroes
when read.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual