MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

248 Chapter 14.
Status Register Fields
Table 14-10 describes the Status register fields.
Table 14-10 Status Register Fields
Field Description
XX
CU
RP
Enables execution of MIPS IV instructions in User mode.
1 → MIPS IV instructions usable
0 → MIPS IV instructions unusable
Controls the usability of each of the four coprocessor unit
numbers. CP0 is always usable when in Kernel mode,
regardless of the setting of the CU 0 bit.
1 → usable
0 → unusable
In the R4400 processor, this bit enables reduced-power
operation by reducing the internal clock frequency. In the
R10000 processor, this bit should be set to zero.
Enables additional floating-point registers
FR 0 → 16 registers
1 → 32 registers
RE Reverse-Endian bit, valid in User mode.
DS Diagnostic Status field (see Figure 14-12).
IM
KX
SX
UX
Interrupt Mask: controls the enabling of each of the external,
internal, and software interrupts. An interrupt is taken if
interrupts are enabled, and the corresponding bits are set in
both the Interrupt Mask field of the Status register and the
Interrupt Pending field of the Cause register.
0 → disabled
1→ enabled
Enables 64-bit addressing in Kernel mode. The extendedaddressing
TLB refill exception is used for TLB misses on
kernel addresses.
0 → 32−bit
1 → 64−bit
Enables 64-bit addressing and operations in Supervisor
mode. The extended-addressing TLB refill exception is used
for TLB misses on supervisor addresses.
0 → 32−bit
1 → 64−bit
Enables 64-bit addressing and operations in User mode. The
extended-addressing TLB refill exception is used for TLB
misses on user addresses.
0 → 32−bit
1 → 64−bit
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual