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MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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Coprocessor 0 247<br />

CU2 CU2<br />

CU1 CU1<br />

CU0 CU0<br />

BEV BEV<br />

• The Reduced Power (RP) bit is reserved and should be zero. The<br />

<strong>R10000</strong> processor does not define a reduced power mode.<br />

• The Reverse-Endian (RE) bit, bit 25, reverses the endianness of the<br />

machine. The processor can be configured as either little-endian or<br />

big-endian at system reset; reverse-endian selection is available in<br />

Kernel and Supervisor modes, and in the User mode when the RE bit<br />

is 0. Setting the RE bit to 1 inverts the User mode endianness.<br />

• The 9-bit Diagnostic Status (DS) field is used for self-testing, and<br />

checks the cache and virtual memory system. This field is described<br />

in Table 14-11 and Figure 14-12.<br />

• The 8-bit Interrupt Mask (IM) field controls the enabling of eight<br />

interrupt conditions. Interrupts must be enabled before they can be<br />

asserted, and the corresponding bits are set in both the Interrupt Mask<br />

field of the Status register and the Interrupt Pending field of the Cause<br />

register.<br />

• The processor mode is undefined if the KSU field is set to 3 (112 ). The<br />

<strong>R10000</strong> processor implements this as User mode.<br />

Status Register<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

XX XX RP RP FR FR RE RE 0<br />

0 TS TS SR SRNMI 0 CH CHCE CEDE DE<br />

IM IM (8 (8 bits) bits) KX KX SX SX UX UX KSU KSU<br />

Coprocessor<br />

Usable<br />

Diagnostic Status Fields<br />

Figure 14-11 Status Register<br />

<strong>MIPS</strong> <strong>R10000</strong> <strong>Microprocessor</strong> <strong>User's</strong> <strong>Manual</strong> Version 2.0 of January 29, 1997<br />

ERL ERL<br />

RXL EXL<br />

IE IE

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