MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 245
14.9 EntryHi Register (10)
The EntryHi register holds the high-order bits of a TLB entry for TLB read and
write operations.
The EntryHi register is accessed by the TLB Probe, TLB Write Random, TLB Write
Indexed, and TLB Read Indexed instructions.
Figure 14-10 shows the format of this register and Table 14-8 describes the
register’s fields..
63
R
2
Figure 14-10 EntryHi Register
Table 14-8 EntryHi Register Fields
Field Description
VPN2
ASID
Virtual page number divided by two (maps to two pages); upper
bits of the virtual address
Address space ID field. An 8-bit field that lets multiple processes
share the TLB; each process has a distinct mapping of otherwise
identical virtual page numbers.
Region. (00 → user, 01 → supervisor, 11 → kernel) used to match
R
vAddr63...62 Fill Reserved. 0 on read; ignored on write.
0
62 61 44 43
EntryHi Register
VPN2
31
13 12 8 7
Reserved. Must be written as zeroes, and returns zeroes when
read.
In 64-bit addressing mode, the VPN2 field contains bits 43:13 of the 44-bit virtual
address.
In 32-bit addressing mode only the lower 32 bits of the EntryHi register are used,
so the format remains the same as in the R4400 processor’s 32-bit addressing
mode. The FILL field is ignored on write and read as zeroes, as it was in the R4400
implementation.
When either a TLB refill, TLB invalid, or TLB modified exception occurs, the
EntryHi register is loaded with the virtual page number (VPN2) and the ASID of
the virtual address that did not have a matching TLB entry.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
FILL
18
0
ASID
5 8
0