MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

240 Chapter 14.
The PFN fields of the EntryLo0 and EntryLo1 registers span bits 33:6 of the 40-bit
physical address.
Two additional bits for the mapped space’s uncached attribute can be loaded into
bits 63:62 of the EntryLo register, which are then written into the TLB with a TLB
Write. During the address cycle of processor double/single/partial-word read
and write requests, and during the address cycle of processor uncached accelerated
block write requests, the processor drives the uncached attribute on SysAD[59:58].
The same EntryLo registers are used for the 64-bit and 32-bit addressing modes. In
both modes the registers are 64 bits wide, however when the MIPS III ISA is not
enabled (32-bit User and Supervisor modes) only the lower 32 bits of the EntryLo
registers are accessible.
MIPS III is disabled when the processor is in 32-bit Supervisor or User mode.
Loading of the integer registers is limited to bits 31:0, sign-extended through bits
63:32. EntryLo[33:31] or PFN[39:38] can only be set to all zeroes or all ones. In 32and
64-bit modes, the UC and PFN bits of both EntryLo registers are written into
the TLB. The PFN bits can be masked by setting bits in the FrameMask register
(described in this chapter) but the UC bits cannot be masked or initialized in 32-bit
User or Supervisor modes. In 32-bit Kernel mode, MIPS III is enabled and 64-bit
operations are always available to program the UC bits.
There is only one G bit per TLB entry, and it is written with EntryLo0[0] and
EntryLo1[0] on a TLB write.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual