MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Coprocessor 0 239
14.3 EntryLo0 (2), and EntryLo1 (3) Registers
63
UC
62 61
0
The EntryLo register consists of two registers with identical formats:
• EntryLo0 is used for even virtual pages.
• EntryLo1 is used for odd virtual pages.
The EntryLo0 and EntryLo1 registers are read/write registers. They hold the
physical page frame number (PFN) of the TLB entry for even and odd pages,
respectively, when performing TLB read and write operations. Figure 14-3 shows
the format of these registers.
Figure 14-3 Fields of the EntryLo0 and EntryLo1 Registers
Table 14-4 Description of EntryLo Registers’ Fields
Field Description
UC Uncached attribute
PFN Page frame number; the upper bits of the physical address.
C Specifies the TLB page coherency attribute.
D
V
G
0
EntryLo0 and EntryLo1 Registers
34 33 6 5 3 2 1 0
PFN C D V G
28
3 1 1 1
Valid. If this bit is set, it indicates that the TLB entry is valid;
otherwise, a TLBL or TLBS invalid exception occurs.
Valid. If this bit is set, it indicates that the TLB entry is valid;
otherwise, a TLBL or TLBS invalid exception occurs.
Global. If this bit is set in both Lo0 and Lo1, then the processor
ignores the ASID during TLB lookup.
Reserved. Must be written as zeroes, and returns zeroes when
read.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997