MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Electrical Specifications 215
12.2 AC Electrical Specification
Maximum Operating Conditions
Test Specification
Secondary Cache and System Interface Timing
This section describes the following AC electrical characteristics of the R10000
processor:
• maximum operating conditions
• test specification
• secondary cache and system interface timing
• enable/output delay, setup, hold time
• asynchronous inputs
The R10000 chip clamps signals that overshoot the DC limits established for input
logic levels. These limits are published as part of the fabrication process
characterization.
The R10000 chip provides silicon diode clamps on all signal pins.
HSTL test conditions are based on the JEDEC Standard conditions.
Timing measurements are referenced from the mid-swing point of the input
signal to the crossing point of the SysClk and SysClk* input clocks. All input
signals maintain a 1 V/ns edge rate in the 20% to 80% range of the input signal
swing.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997