MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library
MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library
MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library
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xxiv Table of Contents<br />
14<br />
Coprocessor 0<br />
Index Register (0)............................................................................................................................237<br />
Random Register (1).......................................................................................................................238<br />
EntryLo0 (2), and EntryLo1 (3) Registers....................................................................................239<br />
Context (4) .......................................................................................................................................241<br />
PageMask Register (5)....................................................................................................................242<br />
Wired Register (6)...........................................................................................................................243<br />
BadVAddr Register (8) ..................................................................................................................244<br />
Count and Compare Registers (9 and 11) ...................................................................................244<br />
EntryHi Register (10) .....................................................................................................................245<br />
Status Register (12).........................................................................................................................246<br />
Status Register Fields...........................................................................................................248<br />
Diagnostic Status Field ........................................................................................................249<br />
Coprocessor Accessibility ...................................................................................................251<br />
Cause Register (13).........................................................................................................................252<br />
Exception Program Counter (14)..................................................................................................254<br />
Processor Revision Identifier (PRId) Register (15) ....................................................................255<br />
Config Register (16)........................................................................................................................256<br />
Load Linked Address (LLAddr) Register (17) ...........................................................................257<br />
WatchLo (18) and WatchHi (19) Registers..................................................................................258<br />
XContext Register (20) ...................................................................................................................259<br />
FrameMask Register (21)...............................................................................................................260<br />
Diagnostic Register (22).................................................................................................................261<br />
Performance Counter Registers (25)............................................................................................264<br />
ECC Register (26)............................................................................................................................273<br />
CacheErr Register (27) ...................................................................................................................274<br />
CacheErr Register Format for Primary Instruction Cache Errors .................................274<br />
CacheErr Register Format for Primary Data Cache Errors ............................................275<br />
CacheErr Register Format for Secondary Cache Errors..................................................276<br />
CacheErr Register Format for System Interface Errors...................................................277<br />
TagLo (28) and TagHi (29) Registers ...........................................................................................278<br />
CacheOp is Index Load/Store Tag ....................................................................................278<br />
Primary Instruction Cache Operation.....................................................................279<br />
Primary Data Cache Operation................................................................................279<br />
Secondary Cache Operation .....................................................................................281<br />
CacheOp is Index Load/Store Data ..................................................................................282<br />
Primary Instruction Cache Operation.....................................................................282<br />
Primary Data Cache Operation................................................................................283<br />
Secondary Cache Operation .....................................................................................283<br />
ErrorEPC Register (30)...................................................................................................................284<br />
CP0 Instructions..............................................................................................................................285<br />
Hazards..................................................................................................................................285<br />
Version 2.0 of January 29, 1997 <strong>MIPS</strong> <strong>R10000</strong> <strong>Microprocessor</strong> <strong>User's</strong> <strong>Manual</strong>