MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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208 Chapter 11. ‡ Will be eliminated after rev. 1.2. Table 11-2 (cont.) Boundary Scan Register Pinlist, rev 1.2 Signal Signal Signal Signal Signal Signal 253. SCData[112] 254. SCBDWr* 255. SCBDOE* 256. SCBDCS* 257. SCBDWay 258. SCBAddr[8] 259. SCBAddr[7] 260. SCBAddr[6] 261. SCBAddr[5] 262. SCBAddr[4] 263. SCBAddr[3] 264. SCBAddr[2] 265. SCBAddr[1] 266. SCBAddr[0] 267. SCData[111] 268. SCData[110] 269. SCData[109] 270. SCData[108] 271. SCTag[8] 272. SCTag[7] 273. SCTag[6] 274. SCTag[5] 275. SCTag[4] 276. SCTag[3] 277. SCTag[2] 278. SCTag[1] 279. SCTag[0] 280. SCTagLSBAddr 281. TriState ‡ 282. SCTWay 283. SCTagChk[6] 284. SCTagChk[5] 285. SCTagChk[4] 286. SCTagChk[3] 287. SCTagChk[2] 288. SCTagChk[1] 289. SCTagChk[0] 290. SysCmd[0] 291. SysCmd[1] 292. SysCmd[2] 293. SysCmd[3] 294. SysCmd[4] 295. SysCmd[5] 296. SysCmd[6] 297. SysCmd[7] 298. SysCmd[8] 299. SysCmd[9] 300. SysCmd[10] 301. SysCmd[11] 302. SysCmdPar 303. SysVal* 304. SysReq* 305. SysRel* 306. SysGnt* 307. SysReset* 308. SysRespVal* 309. SysRespPar 310. SysResp[4] 311. SysResp[3] 312. SysResp[2] 313. SysResp[1] 314. SysResp[0] 315. SysGblPerf* 316. SysRdRdy* 317. SysWrRdy* 318. SysStateVal* 319. SysStatePar 320. SysState[2] 321. SysState[1] 322. SysState[0] 323. SysCorErr* 324. SysUncErr* 325. SysNMI* 326. SCDataChk[7] 327. SCDataChk[5] 328. SCData[127] 329. SCData[126] 330. SCData[125] 331. SCData[124] 332. SCData[123] 333. SCData[122] 334. SCData[121] 335. SCData[120] 336. SCData[119] 337. SCData[118] 338. SCData[117] 339. SCData[116] 340. SCData[115] 341. SCData[114] 342. SCData[113] 343. SCData[112] 344. SCBDWr* 345. SCBDOE* 346. SCBDCS* 347. SCBDWay 348. SCBAddr[8] 349. SCBAddr[7] 350. SCBAddr[6] 351. SCBAddr[5] 352. SCBAddr[4] 353. SCBAddr[3] 354. SCBAddr[2] 355. SCBAddr[1] 356. SCBAddr[0] 357. SCData[111] 358. SCData[110] 359. SCData[109] 360. SCData[108] 361. SCData[107] 362. SCData[106] 363. SCData[105] 364. SCData[104] 365. SysAD[63] 366. SysAD[62] 367. SysAD[61] 368. SysAD[60] 369. SysAD[59] 370. SysAD[58] 371. SysAD[57] 372. SysAD[56] 373. SysAD[55] 374. SysAD[54] 375. SysAD[53] 376. SysAD[52] 377. SysAD[51] 378. SysAD[50] 379. SysAD[49] 380. SysAD[48] 381. SysADChk[7] 382. SysADChk[6] 383. SysADChk[5] 384. SysADChk[4] 385. SysADChk[3] 386. SysADChk[2] 387. SysADChk[1] 388. SysADChk[0] 389. SysAD[31] 390. SysAD[30] 391. SysAD[29] 392. SysAD[28] 393. SysAD[27] 394. SysAD[26] 395. SysAD[25] 396. SysAD[24] 397. SysAD[23] 398. SysAD[22] 399. SysAD[21] 400. SysAD[20] 401. SysAD[19] 402. SysAD[18] 403. SysAD[17] 404. SysAD[16] 405. SCData[103] 406. SCData[102] 407. SCData[101] 408. SCData[100] 409. SCData[99] 410. SCData[98] 411. SCData[97] 412. SCData[96] 413. SCDataChk[3] 414. SCBAddr[9] 415. SCBAddr[10] 416. SCBAddr[11] 417. SCBAddr[12] 418. SCBAddr[13] 419. SCBAddr[14] 420. SCBAddr[15] 421. SCBAddr[16] 422. SCBAddr[17] 423. SCBAddr[18] Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
12. Electrical Specifications This chapter contains the following electrical and signal information about the R10000 processor: • DC electrical specification • AC electrical specification • signal integrity issues MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997209
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
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7. Clock Signals The R10000 process
Page 187 and 188: Clock Signals 157 7.2 Secondary Cac
Page 189 and 190: 8. Initialization This section desc
Page 191 and 192: Initialization 161 Errata Vcc VccQ[
Page 193 and 194: Initialization 163 8.4 Soft Reset S
Page 195 and 196: Initialization 165 Table 8-1 (cont.
Page 197 and 198: 9. Error Protection and Handling Th
Page 199 and 200: Error Protection and Handling 169 9
Page 207 and 208: Error Protection and Handling 177 D
Page 209 and 210: Error Protection and Handling 179 T
Page 211 and 212: Error Protection and Handling 181 E
Page 213 and 214: Error Protection and Handling 183 W
Page 215 and 216: Error Protection and Handling 185 P
Page 217 and 218: 10. CACHE Instructions This chapter
Page 219 and 220: CACHE Instructions 189 TLB Refill a
Page 221 and 222: CACHE Instructions 191 Op Field Enc
Page 223 and 224: CACHE Instructions 193 10.4 Index W
Page 225 and 226: CACHE Instructions 195 10.7 Index L
Page 227 and 228: CACHE Instructions 197 10.11 Hit In
Page 229 and 230: CACHE Instructions 199 10.15 Hit Wr
Page 231 and 232: CACHE Instructions 201 10.17 Index
Page 233 and 234: 11. JTAG Interface Operation Errata
Page 235 and 236: JTAG Interface Operation 205 11.2 I
Page 237: JTAG Interface Operation 207 ‡ Wi
Page 241 and 242: Electrical Specifications 211 DCOk
Page 243 and 244: Electrical Specifications 213 Unuse
Page 245 and 246: Electrical Specifications 215 12.2
Page 247 and 248: Electrical Specifications 217 12.3
Page 249 and 250: 13. Packaging The R10000 microproce
Page 251 and 252: Packaging 221 Electrical Characteri
Page 253 and 254: Packaging 223 Figure 13-1 R10000 59
Page 255 and 256: Packaging 225 Table 13-3 (cont.) Si
Page 261 and 262: Packaging 231 Figure 13-3 599LGA PW
Page 263 and 264: Packaging 233 Figure 13-5 599LGA Bo
Page 265 and 266: 14. Coprocessor 0 This chapter desc
Page 267 and 268: Coprocessor 0 237 14.1 Index Regist
Page 269 and 270: Coprocessor 0 239 14.3 EntryLo0 (2)
Page 271 and 272: Coprocessor 0 241 14.4 Context (4)
Page 273 and 274: Coprocessor 0 243 14.6 Wired Regist
Page 275 and 276: Coprocessor 0 245 14.9 EntryHi Regi
Page 277 and 278: Coprocessor 0 247 CU2 CU2 CU1 CU1 C
Page 279 and 280: Coprocessor 0 249 Diagnostic Status
Page 281 and 282: Coprocessor 0 251 Coprocessor Acces
Page 283 and 284: Coprocessor 0 253 Table 14-13 Cause
Page 285 and 286: Coprocessor 0 255 14.13 Processor R
Page 287 and 288: Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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