MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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202 Chapter 10. 10.20 Index Store Data (I) 10.21 Index Store Data (D) 10.22 Index Store Data (S) Index Store Data (I) stores a single instruction into the primary instruction cache. The address where this instruction will be written comes from VA[13:2] of the CACHE instruction. The way where the data will be written comes from VA[0] of the CACHE instruction. The instruction itself comes from CP0 TagHi[3:0] and TagLo[31:0]. The parity bit is also stored. This comes from CP0 ECC[0]. The data to be stored bypasses the predecode and is written directly into the instruction cache. The tag field is unmodified. Index Store Data (D) stores a word of data and its byte parity into the data cache from the CP0 TagLo and ECC registers. The address where this word will be written is defined by VA[13:2] of the CACHE instruction. The way is defined by VA[0]. The data word comes from CP0 TagLo. The parity bits come from CP0 ECC[3:0]. The data cache tag array including the LRU bit is left unchanged. Index Store Data (S) stores a quadword of data and 10 check bits into the secondary cache data array. It stores a doubleword of data from CP0 TagHi and TagLo and pads the remaining doubleword with zeroes. This allows the ECC and parity, which are based on the quadword, to be valid for the doubleword of data stored. The address of the quadword stored is defined by the PA of the CACHE instruction, and the way is defined by PA[0]. The data stored in the non-padded doubleword comes from CP0 TagHi and TagLo. The check bits are stored from ECC[9:0]. The tag array including the MRU bit is left unchanged. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
11. JTAG Interface Operation Errata The JTAG interface is implemented according to the standard IEEE 1149.1 test access port protocol specifications. The JTAG interface accesses the JTAG controller and instruction register as well as a boundary scan register. The JTAG operation does not require DCOk to be asserted or SysClk to be running; however, if DCOk is asserted the SysClk must run at the specified minimum frequency or the core logic may be damaged. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997203
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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System Interface Operations 115 Pro
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System Interface Operations 127 Ext
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System Interface Operations 131 Cyc
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System Interface Operations 143 Coh
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System Interface Operations 147 The
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System Interface Operations 149 In
Page 181 and 182: System Interface Operations 151 Cyc
Page 183 and 184: System Interface Operations 153 6.2
Page 185 and 186: 7. Clock Signals The R10000 process
Page 187 and 188: Clock Signals 157 7.2 Secondary Cac
Page 189 and 190: 8. Initialization This section desc
Page 191 and 192: Initialization 161 Errata Vcc VccQ[
Page 193 and 194: Initialization 163 8.4 Soft Reset S
Page 195 and 196: Initialization 165 Table 8-1 (cont.
Page 197 and 198: 9. Error Protection and Handling Th
Page 199 and 200: Error Protection and Handling 169 9
Page 207 and 208: Error Protection and Handling 177 D
Page 209 and 210: Error Protection and Handling 179 T
Page 211 and 212: Error Protection and Handling 181 E
Page 213 and 214: Error Protection and Handling 183 W
Page 215 and 216: Error Protection and Handling 185 P
Page 217 and 218: 10. CACHE Instructions This chapter
Page 219 and 220: CACHE Instructions 189 TLB Refill a
Page 221 and 222: CACHE Instructions 191 Op Field Enc
Page 223 and 224: CACHE Instructions 193 10.4 Index W
Page 225 and 226: CACHE Instructions 195 10.7 Index L
Page 227 and 228: CACHE Instructions 197 10.11 Hit In
Page 229 and 230: CACHE Instructions 199 10.15 Hit Wr
Page 231: CACHE Instructions 201 10.17 Index
Page 235 and 236: JTAG Interface Operation 205 11.2 I
Page 237 and 238: JTAG Interface Operation 207 ‡ Wi
Page 239 and 240: 12. Electrical Specifications This
Page 241 and 242: Electrical Specifications 211 DCOk
Page 243 and 244: Electrical Specifications 213 Unuse
Page 245 and 246: Electrical Specifications 215 12.2
Page 247 and 248: Electrical Specifications 217 12.3
Page 249 and 250: 13. Packaging The R10000 microproce
Page 251 and 252: Packaging 221 Electrical Characteri
Page 253 and 254: Packaging 223 Figure 13-1 R10000 59
Page 255 and 256: Packaging 225 Table 13-3 (cont.) Si
Page 261 and 262: Packaging 231 Figure 13-3 599LGA PW
Page 263 and 264: Packaging 233 Figure 13-5 599LGA Bo
Page 265 and 266: 14. Coprocessor 0 This chapter desc
Page 267 and 268: Coprocessor 0 237 14.1 Index Regist
Page 269 and 270: Coprocessor 0 239 14.3 EntryLo0 (2)
Page 271 and 272: Coprocessor 0 241 14.4 Context (4)
Page 273 and 274: Coprocessor 0 243 14.6 Wired Regist
Page 275 and 276: Coprocessor 0 245 14.9 EntryHi Regi
Page 277 and 278: Coprocessor 0 247 CU2 CU2 CU1 CU1 C
Page 279 and 280: Coprocessor 0 249 Diagnostic Status
Page 281 and 282: Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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