MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

182 Chapter 9.
Errata
SysAD(63:0) Bus
Processor in Master State
Processor in Slave State
Correctable Error Detected
Uncorrectable Error Detected
The 64-bit wide system address/data bus, SysAD(63:0), is protected by an 8-bitwide
ECC.
Whenever the processor is in master state and it asserts SysVal* to indicate it is
driving valid information on the SysAD(63:0) bus, it also drives the proper ECC
on the SysADChk(7:0) bus.
Whenever the processor is in slave state, error checking is enabled with the
assertion of SysCmd(0), and an external agent asserts SysVal* to indicate it is
driving valid information on the SysAD(63:0) bus, the processor checks the
SysADChk(7:0) bus for the proper ECC.
If a correctable error is detected during an external address cycle, or during an
external data cycle for a processor read or upgrade request originated by the
R10000 processor, correction is automatically performed in-line without affecting
latency. The processor asserts SysCorErr* for one SysClk cycle to inform the
external agent that a correctable error has been detected and corrected.
If an uncorrectable error is detected during an external address cycle, the processor
ignores the SysCmd(11:0) and SysAD(63:0) buses for one SysClk cycle, and the
System interface unit posts a Cache Error exception and sets the SA bit in the local
CacheErr register. Additionally, the processor informs the external agent by
asserting SysUncErr* for one SysClk cycle.
Caution: By ignoring the SysCmd(11:0) and SysAD(63:0) buses, this
processor may become unsynchronized with other processors or the
external agent on the cluster bus.
If an uncorrectable error is detected or the data quality indication on SysCmd(5) is
asserted during an external data cycle for a processor read or upgrade request
originated by the processor, the R10000 asserts the corresponding incoming buffer
uncorrectable error flag.
When the processor forwards block data from an incoming buffer entry after
receiving an external ACK completion response, the associated incoming buffer
uncorrectable error flags are checked, and if any are asserted, the System interface
unit posts a single Cache Error exception and initializes the EE, D, and SIdx fields
in the local CacheErr register.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual