MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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166 Chapter 8. Errata Table 8-1 (cont.) Mode Bits SysAD Bit Name and Function Value Mode Setting 28:25 SCClkTap Specifies the alignment ‡ of SCClk[5:0] and SCClk*[5:0] relative to the internal secondary cache clock. 29 Reserved 0 30 31 ODrainSys Specifies whether or not to configure select * System interface bidirectional and output signals as open drain. CTM Specifies whether or not to enable cache test mode. 63:32 Reserved 0 ‡ Does not include the output buffer delay. * SysReq*, SysRel*, SysCmd[11:0], SysCmdPar, SysAD[63:0], SysADChk[7:0], SysVal*, SysState[2:0], SysStatePar, SysStateVal*, SysCorErr*, SysUncErr* The description of bits 28:25 of Table 8-1 has been revised. Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 0 1 SCClk same phase as internal clock SCClk 1/12 PClk period earlier than internal clock SCClk 2/12 PClk period earlier than internal clock SCClk 3/12 PClk period earlier than internal clock SCClk 4/12 PClk period earlier than internal clock SCClk 5/12 PClk period earlier than internal clock undefined undefined SCClk 6/12 PClk period earlier than internal clock SCClk 7/12 PClk period earlier than internal clock SCClk 8/12 PClk period earlier than internal clock SCClk 9/12 PClk period earlier than internal clock SCClk 10/12 PClk period earlier than internal clock SCClk 11/12 PClk period earlier than internal clock undefined undefined Push-pull Open drain Disable Enable
9. Error Protection and Handling This chapter presents the error protection and handling features provided by the R10000 processor. Two types of errors can occur in an R10000 system: • correctable • uncorrectable The following two sections describe them. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997167
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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5. Secondary Cache Interface The pr
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Secondary Cache Interface 61 5.2 Se
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Secondary Cache Interface 63 Indexi
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Secondary Cache Interface 65 Errata
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Secondary Cache Interface 67 SCTag(
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Secondary Cache Interface 69 4-Word
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Secondary Cache Interface 71 16 or
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Secondary Cache Interface 73 5.7 Wr
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Secondary Cache Interface 75 8-Word
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Secondary Cache Interface 77 Tag Wr
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6. System Interface Operations The
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System Interface Operations 81 6.4
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System Interface Operations 85 Mult
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System Interface Operations 87 Exte
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System Interface Operations 91 Outg
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System Interface Operations 97 Duri
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System Interface Operations 99 Erra
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System Interface Operations 101 Cyc
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System Interface Operations 103 Sys
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System Interface Operations 111 Mul
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System Interface Operations 113 Err
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Page 147 and 148: System Interface Operations 117 Err
Page 157 and 158: System Interface Operations 127 Ext
Page 161 and 162: System Interface Operations 131 Cyc
Page 171 and 172: System Interface Operations 141 6.1
Page 173 and 174: System Interface Operations 143 Coh
Page 175 and 176: System Interface Operations 145 Err
Page 177 and 178: System Interface Operations 147 The
Page 179 and 180: System Interface Operations 149 In
Page 181 and 182: System Interface Operations 151 Cyc
Page 183 and 184: System Interface Operations 153 6.2
Page 185 and 186: 7. Clock Signals The R10000 process
Page 187 and 188: Clock Signals 157 7.2 Secondary Cac
Page 189 and 190: 8. Initialization This section desc
Page 191 and 192: Initialization 161 Errata Vcc VccQ[
Page 193 and 194: Initialization 163 8.4 Soft Reset S
Page 195: Initialization 165 Table 8-1 (cont.
Page 199 and 200: Error Protection and Handling 169 9
Page 207 and 208: Error Protection and Handling 177 D
Page 209 and 210: Error Protection and Handling 179 T
Page 211 and 212: Error Protection and Handling 181 E
Page 213 and 214: Error Protection and Handling 183 W
Page 215 and 216: Error Protection and Handling 185 P
Page 217 and 218: 10. CACHE Instructions This chapter
Page 219 and 220: CACHE Instructions 189 TLB Refill a
Page 221 and 222: CACHE Instructions 191 Op Field Enc
Page 223 and 224: CACHE Instructions 193 10.4 Index W
Page 225 and 226: CACHE Instructions 195 10.7 Index L
Page 227 and 228: CACHE Instructions 197 10.11 Hit In
Page 229 and 230: CACHE Instructions 199 10.15 Hit Wr
Page 231 and 232: CACHE Instructions 201 10.17 Index
Page 233 and 234: 11. JTAG Interface Operation Errata
Page 235 and 236: JTAG Interface Operation 205 11.2 I
Page 237 and 238: JTAG Interface Operation 207 ‡ Wi
Page 239 and 240: 12. Electrical Specifications This
Page 241 and 242: Electrical Specifications 211 DCOk
Page 243 and 244: Electrical Specifications 213 Unuse
Page 245 and 246: Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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