MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Table of Contents xix
9
Error Protection and Handling
Correctable Errors ..........................................................................................................................168
Uncorrectable Errors......................................................................................................................169
Propagation of Uncorrectable Errors...........................................................................................170
Cache Error Exception...................................................................................................................171
CP0 CacheErr Register EW Bit .....................................................................................................172
CP0 Status Register DE Bit............................................................................................................172
CACHE Instruction........................................................................................................................172
Error Protection Schemes Used by R10000.................................................................................173
Parity......................................................................................................................................173
Sparse Encoding ...................................................................................................................173
ECC.........................................................................................................................................173
Primary Instruction Cache Error Protection and Handling.....................................................174
Error Protection ....................................................................................................................174
Error Handling .....................................................................................................................174
Primary Data Cache Error Protection and Handling................................................................175
Error Protection ....................................................................................................................175
Error Handling .....................................................................................................................175
Secondary Cache Error Protection and Handling .....................................................................176
Error Protection ....................................................................................................................176
Error Handling .....................................................................................................................176
Data Array...................................................................................................................176
Tag Array ....................................................................................................................179
System Interface Error Protection and Handling ......................................................................180
Error Protection ....................................................................................................................180
Error Handling .....................................................................................................................181
SysCmd(11:0) Bus.......................................................................................................181
SysAD(63:0) Bus .........................................................................................................182
SysState(2:0) Bus.........................................................................................................184
SysResp(4:0) Bus.........................................................................................................184
Protocol Observation ...........................................................................................................185
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997