MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

154 Chapter 6.
6.24 Support for Hardware Emulation
Cycle
SysClk
Master
SysReq*
SysGnt*
SysRel*
SysCmd(11:0)
SysCmdPar
SysAD(63:0)
SysADChk(7:0)
SysVal*
SysRdRdy*
SysWrRdy*
SysState(2:0)
SysStatePar
SysStateVal*
SysResp(4:0)
SysRespPar
SysRespVal*
SysCyc*
Virtual SysClk
When using the R10000 processor in hardware emulation, it is desirable to operate
the System interface at a relative low frequency (typically 1 MHz or below). Since
the R10000 processor contains dynamic circuitry, an external agent cannot simply
provide low frequency SysClk, so a SysCyc* input to the processor allows an
external agent to define a virtual system clock, and yet supply a SysClk within the
acceptable operating range. The assertion of SysCyc* in a particular SysClk cycle
creates a virtual system clock pulse four SysClk cycles later. SysCyc* may be
asserted aperiodically.
In a normal system environment, the SysCyc* input should be permanently
asserted.
Figure 6-29 depicts the use of SysCyc* to create a virtual SysClk of one-third the
normal SysClk frequency.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 - - - EA EA EA
DSPWr ReqLst DSPRd RspLst
Adr Dat Adr Dat
Figure 6-29 Hardware Emulation Protocol
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual