MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 153
6.22 Support for a Directory-Based Coherency Protocol
6.23 Support for Uncached Attribute
Some system designs implement a directory-based coherency protocol.
For such systems, the processor provides the processor eliminate request cycle. If
the PrcElmReq mode bit is asserted, the processor issues a processor eliminate
request whenever it intends to eliminate a Shared, CleanExclusive, or DirtyExclusive
block from the secondary cache. During the address cycle of the processor
eliminate request, the physical address and the secondary cache block former
state are provided. The external agent may then use this information to maintain
an external directory structure.
The processor supports a 2-bit user-defined Uncached Attribute, which is driven on
SysAD[59:58] during the address cycle of the following:
• processor double/single/partial-word read requests
• double/single/partial-word write requests
• block write requests resulting from completely gathered uncached
accelerated blocks
For unmapped accesses, the uncached attribute is sourced from VA[58:57].
For mapped accesses, the uncached attribute is sourced from the TLB Uncached
Attribute field. The TLB Uncached Attribute field may be initialized in 64-bit mode
using bits 63:62 of the CP0 EntryLo0 and EntryLo1 registers.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997