MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 149
In the same manner, a processor coherency data response issued by a processor in
the master state is observed as an external block data response by any processors
in the slave state.
External coherency requests that target a processor are handled in FIFO order and
result in processor coherency state responses. If an external coherency request
that targets a processor hits a DirtyExclusive secondary cache block, the processor
also provides a processor coherency data response.
Figure 6-27 presents an example of a processor read request with four R10000
processors residing on the cluster bus. The CohPrcReqTar mode bit is asserted
for a snoopy-based coherency protocol. R10000 0 issues a processor coherent read
exclusive request. This is observed as an external intervention exclusive request
by R10000 1 , R10000 2 , and R10000 3 . R10000 1 and R10000 3 respond with Invalid
processor coherency state responses. R10000 2 responds with a DirtyExclusive
processor coherency state response. Based on these processor coherency state
responses, the cluster coordinator allows R10000 2 to become master of the System
interface so that it may provide a processor coherency data response, which will
be observed as an external block data response by R10000 0 . Finally, the cluster
coordinator issues an external ACK completion response to forward the external
block data response and to free the request number.
Figure 6-28 presents an example of a processor upgrade request with four R10000
processors residing on the cluster bus. The CohPrcReqTar mode bit is asserted
for a snoopy-based coherency protocol. R10000 0 issues a processor upgrade
request, observed as an external invalidate request by R10000 1 , R10000 2 , and
R10000 3 . R10000 2 and R10000 3 provide Shared processor coherency state
responses. R10000 1 provides an Invalid processor coherency state response. Based
on these processor coherency state responses, the cluster coordinator issues an
external ACK completion response for the processor upgrade request to indicate
that the request was successful and to free the request number.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997