MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

More documents

Recommendations

Info

148 Chapter 6. SysGblPerf* Signal 6.19 Cluster Bus Operation The SysGblPerf* signal is provided for systems implementing a relaxed consistency memory model. The external agent asserts this signal when all processor requests are globally performed, thereby allowing the processor to graduate SYNC instructions. The external agent negates this signal when some processor requests are not yet globally performed, thereby preventing the processor from graduating SYNC instructions. To prevent a SYNC instruction from graduating, the external agent must negate the SysGblPerf* signal no later than the same SysClk cycle in which it issued the external completion response for a processor read or upgrade request which is not yet globally performed. Also, the external agent must negate the SysGblPerf* signal no later than two SysClk cycles after the address cycle of a processor double/single/partial-word write request which has not yet been globally performed. The SysGblPerf* signal may be permanently asserted in systems implementing a sequential consistency memory model. A R10000 multiprocessor cluster may be created by directly attaching the System interfaces of 2 to 4 R10000 processors, and providing an external cluster coordinator to handle arbitration and coherency management. The cluster coordinator arbitrates the multiprocessors using the SysReq*, SysGnt*, and SysRel* signals. A processor request issued by an R10000 processor in master state is observed as an external request by any R10000 processors in the slave state on the cluster bus. This is described Table 6-31. Table 6-31 Relationship Between Processor and External Requests for the Cluster Bus Processor Request External Request Coherent block read shared Intervention shared Coherent block read exclusive Intervention exclusive Noncoherent block read Allocate request number Double/single/partial-word read Allocate request number Block write NOP Double/single/partial-word write NOP Upgrade Invalidate Eliminate NOP Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
System Interface Operations 149 In the same manner, a processor coherency data response issued by a processor in the master state is observed as an external block data response by any processors in the slave state. External coherency requests that target a processor are handled in FIFO order and result in processor coherency state responses. If an external coherency request that targets a processor hits a DirtyExclusive secondary cache block, the processor also provides a processor coherency data response. Figure 6-27 presents an example of a processor read request with four R10000 processors residing on the cluster bus. The CohPrcReqTar mode bit is asserted for a snoopy-based coherency protocol. R10000 0 issues a processor coherent read exclusive request. This is observed as an external intervention exclusive request by R10000 1 , R10000 2 , and R10000 3 . R10000 1 and R10000 3 respond with Invalid processor coherency state responses. R10000 2 responds with a DirtyExclusive processor coherency state response. Based on these processor coherency state responses, the cluster coordinator allows R10000 2 to become master of the System interface so that it may provide a processor coherency data response, which will be observed as an external block data response by R10000 0 . Finally, the cluster coordinator issues an external ACK completion response to forward the external block data response and to free the request number. Figure 6-28 presents an example of a processor upgrade request with four R10000 processors residing on the cluster bus. The CohPrcReqTar mode bit is asserted for a snoopy-based coherency protocol. R10000 0 issues a processor upgrade request, observed as an external invalidate request by R10000 1 , R10000 2 , and R10000 3 . R10000 2 and R10000 3 provide Shared processor coherency state responses. R10000 1 provides an Invalid processor coherency state response. Based on these processor coherency state responses, the cluster coordinator issues an external ACK completion response for the processor upgrade request to indicate that the request was successful and to free the request number. MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
Page 1 and 2:
MIPS R10000 Microprocessor User’s
Page 3 and 4:
Acknowledgments This book represent
Page 5 and 6:
About This Manual Glossary Stylisti
Page 7 and 8:
Table of Contents vii Contents Ackn
Page 9 and 10:
Table of Contents ix Superscalar In
Page 11 and 12:
Table of Contents xi 3 Interface Si
Page 13 and 14:
Table of Contents xiii 5 Secondary
Page 15 and 16:
Table of Contents xv SysAD[63:0] Ad
Page 17 and 18:
Table of Contents xvii 7 Clock Sign
Page 19 and 20:
Table of Contents xix 9 Error Prote
Page 21 and 22:
Table of Contents xxi 11 JTAG Inter
Page 23 and 24:
Table of Contents xxiii 13 Packagin
Page 25 and 26:
Table of Contents xxv Branch on Cop
Page 27 and 28:
Table of Contents xxvii 16 Memory M
Page 29 and 30:
Table of Contents xxix 18 A Cache T
Page 31 and 32:
1. Introduction to the R10000 Proce
Page 33 and 34:
Introduction to the R10000 Processo
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Page 63 and 64:
2. System Configurations The R10000
Page 65 and 66:
System Configurations 35 2.2 Multip
Page 67 and 68:
3. Interface Signal Descriptions Th
Page 69 and 70:
Interface Signal Descriptions 39 3.
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
4. Cache Organization and Coherency
Page 77 and 78:
Cache Organization and Coherency 47
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
5. Secondary Cache Interface The pr
Page 91 and 92:
Secondary Cache Interface 61 5.2 Se
Page 93 and 94:
Secondary Cache Interface 63 Indexi
Page 95 and 96:
Secondary Cache Interface 65 Errata
Page 97 and 98:
Secondary Cache Interface 67 SCTag(
Page 99 and 100:
Secondary Cache Interface 69 4-Word
Page 101 and 102:
Secondary Cache Interface 71 16 or
Page 103 and 104:
Secondary Cache Interface 73 5.7 Wr
Page 105 and 106:
Secondary Cache Interface 75 8-Word
Page 107 and 108:
Secondary Cache Interface 77 Tag Wr
Page 109 and 110:
6. System Interface Operations The
Page 111 and 112:
System Interface Operations 81 6.4
Page 113 and 114:
Page 115 and 116:
System Interface Operations 85 Mult
Page 117 and 118:
System Interface Operations 87 Exte
Page 119 and 120:
Page 121 and 122:
System Interface Operations 91 Outg
Page 123 and 124:
Page 125 and 126:
Page 127 and 128: System Interface Operations 97 Duri
Page 129 and 130: System Interface Operations 99 Erra
Page 131 and 132: System Interface Operations 101 Cyc
Page 133 and 134: System Interface Operations 103 Sys
Page 137 and 138: System Interface Operations 107 6.1
Page 141 and 142: System Interface Operations 111 Mul
Page 143 and 144: System Interface Operations 113 Err
Page 145 and 146: System Interface Operations 115 Pro
Page 157 and 158: System Interface Operations 127 Ext
Page 173 and 174: System Interface Operations 143 Coh
Page 177: System Interface Operations 147 The
Page 185 and 186: 7. Clock Signals The R10000 process
Page 187 and 188: Clock Signals 157 7.2 Secondary Cac
Page 189 and 190: 8. Initialization This section desc
Page 191 and 192: Initialization 161 Errata Vcc VccQ[
Page 193 and 194: Initialization 163 8.4 Soft Reset S
Page 195 and 196: Initialization 165 Table 8-1 (cont.
Page 197 and 198: 9. Error Protection and Handling Th
Page 199 and 200: Error Protection and Handling 169 9
Page 207 and 208: Error Protection and Handling 177 D
Page 209 and 210: Error Protection and Handling 179 T
Page 211 and 212: Error Protection and Handling 181 E
Page 213 and 214: Error Protection and Handling 183 W
Page 215 and 216: Error Protection and Handling 185 P
Page 217 and 218: 10. CACHE Instructions This chapter
Page 219 and 220: CACHE Instructions 189 TLB Refill a
Page 221 and 222: CACHE Instructions 191 Op Field Enc
Page 223 and 224: CACHE Instructions 193 10.4 Index W
Page 225 and 226: CACHE Instructions 195 10.7 Index L
Page 227 and 228: CACHE Instructions 197 10.11 Hit In
Page 229 and 230:
CACHE Instructions 199 10.15 Hit Wr
Page 231 and 232:
CACHE Instructions 201 10.17 Index
Page 233 and 234:
11. JTAG Interface Operation Errata
Page 235 and 236:
JTAG Interface Operation 205 11.2 I
Page 237 and 238:
JTAG Interface Operation 207 ‡ Wi
Page 239 and 240:
12. Electrical Specifications This
Page 241 and 242:
Electrical Specifications 211 DCOk
Page 243 and 244:
Electrical Specifications 213 Unuse
Page 245 and 246:
Electrical Specifications 215 12.2
Page 247 and 248:
Electrical Specifications 217 12.3
Page 249 and 250:
13. Packaging The R10000 microproce
Page 251 and 252:
Packaging 221 Electrical Characteri
Page 253 and 254:
Packaging 223 Figure 13-1 R10000 59
Page 255 and 256:
Packaging 225 Table 13-3 (cont.) Si
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Packaging 231 Figure 13-3 599LGA PW
Page 263 and 264:
Packaging 233 Figure 13-5 599LGA Bo
Page 265 and 266:
14. Coprocessor 0 This chapter desc
Page 267 and 268:
Coprocessor 0 237 14.1 Index Regist
Page 269 and 270:
Coprocessor 0 239 14.3 EntryLo0 (2)
Page 271 and 272:
Coprocessor 0 241 14.4 Context (4)
Page 273 and 274:
Coprocessor 0 243 14.6 Wired Regist
Page 275 and 276:
Coprocessor 0 245 14.9 EntryHi Regi
Page 277 and 278:
Coprocessor 0 247 CU2 CU2 CU1 CU1 C
Page 279 and 280:
Coprocessor 0 249 Diagnostic Status
Page 281 and 282:
Coprocessor 0 251 Coprocessor Acces
Page 283 and 284:
Coprocessor 0 253 Table 14-13 Cause
Page 285 and 286:
Coprocessor 0 255 14.13 Processor R
Page 287 and 288:
Coprocessor 0 257 14.15 Load Linked
Page 289 and 290:
Coprocessor 0 259 14.17 XContext Re
Page 291 and 292:
Coprocessor 0 261 14.19 Diagnostic
Page 293 and 294:
Coprocessor 0 263 Errata There are
Page 295 and 296:
Coprocessor 0 265 Errata Errata The
Page 297 and 298:
Coprocessor 0 267 Event 1 for Count
Page 299 and 300:
Coprocessor 0 269 Event 6 for Count
Page 301 and 302:
Coprocessor 0 271 Event 14 for Coun
Page 303 and 304:
Coprocessor 0 273 14.21 ECC Registe
Page 305 and 306:
Coprocessor 0 275 CacheErr Register
Page 307 and 308:
Coprocessor 0 277 CacheErr Register
Page 309 and 310:
Coprocessor 0 279 Errata Primary In
Page 311 and 312:
Coprocessor 0 281 Errata Errata Sec
Page 313 and 314:
Coprocessor 0 283 Primary Data Cach
Page 315 and 316:
Coprocessor 0 285 14.25 CP0 Instruc
Page 317 and 318:
Coprocessor 0 287 14.27 CACHE Instr
Page 319 and 320:
Coprocessor 0 289 Cache CACHE (cont
Page 321 and 322:
Coprocessor 0 291 14.29 DMTC0 Instr
Page 323 and 324:
Coprocessor 0 293 14.31 MFC0 Instru
Page 325 and 326:
Coprocessor 0 295 MTPS 31 Format: M
Page 327 and 328:
Coprocessor 0 297 14.34 TLBP Instru
Page 329 and 330:
Coprocessor 0 299 14.36 TLBWI Instr
Page 331 and 332:
15. Floating-Point Unit This sectio
Page 333 and 334:
Floating-Point Unit 303 15.2 Floati
Page 335 and 336:
Floating-Point Unit 305 Load and St
Page 337 and 338:
Floating-Point Unit 307 63 63 Doubl
Page 339 and 340:
Floating-Point Unit 309 Floating-Po
Page 341 and 342:
Floating-Point Unit 311 Loading the
Page 343 and 344:
Floating-Point Unit 313 Moves and C
Page 345 and 346:
16. Memory Management This section
Page 347 and 348:
Memory Management 317 Addressing Mo
Page 349 and 350:
Memory Management 319 32-bit User M
Page 351 and 352:
Memory Management 321 32-bit Superv
Page 353 and 354:
Memory Management 323 32-bit Kernel
Page 355 and 356:
Memory Management 325 0X BFFFFFFF 0
Page 357 and 358:
Memory Management 327 64-bit Virtua
Page 359 and 360:
Memory Management 329 Using the TLB
Page 361 and 362:
17. CPU Exceptions This chapter des
Page 363 and 364:
CPU Exceptions 333 17.3 TLB Refill
Page 365 and 366:
CPU Exceptions 335 Priority of Exce
Page 367 and 368:
CPU Exceptions 337 Soft † Reset E
Page 369 and 370:
CPU Exceptions 339 NMI Exception Ca
Page 371 and 372:
CPU Exceptions 341 TLB Exceptions T
Page 373 and 374:
CPU Exceptions 343 TLB Invalid Exce
Page 375 and 376:
CPU Exceptions 345 Cache Error Exce
Page 377 and 378:
CPU Exceptions 347 Integer Overflow
Page 379 and 380:
CPU Exceptions 349 System Call Exce
Page 381 and 382:
CPU Exceptions 351 Reserved Instruc
Page 383 and 384:
CPU Exceptions 353 Floating-Point E
Page 385 and 386:
CPU Exceptions 355 Interrupt Except
Page 387 and 388:
CPU Exceptions 357 17.5 COP0 Instru
Page 389 and 390:
18. Cache Test Mode The R10000 proc
Page 391 and 392:
Cache Test Mode 361 18.3 Entering C
Page 393 and 394:
Cache Test Mode 363 18.5 SysAD(63:0
Page 395 and 396:
Cache Test Mode 365 Auto-Increment
Page 397 and 398:
Cache Test Mode 367 Auto-Increment
Page 399 and 400:
A. Glossary The following terms are
Page 401 and 402:
A.6 Dynamic Scheduling The R10000 p
Page 403 and 404:
A.11 Nonblocking Loads and Stores M
Page 405 and 406:
A.13 Logical and Physical Registers
Page 407 and 408:
Index I-1 Index Numerics 16-word, c
Page 409 and 410:
Index I-3 uncached accelerated, des
Page 411 and 412:
Index I-5 branch on CP0 instruction
Page 413 and 414:
Index I-7 F fetch pipeline 6, 17 fe
Page 415 and 416:
Index I-9 TLBWR 285, 300 unsupporte
Page 417 and 418:
Index I-11 NMI see also nonmaskable
Page 419 and 420:
Index I-13 CP0 (description of) 235
Page 421 and 422:
Index I-15 SysAD[20:16] interrupt r
Page 423 and 424:
Index I-17 SysWrRdy, signal 41, 118
show all

MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?