MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 147
The external coherency request latency is presented in Table 6-30.
Table 6-30 External Coherency Request Latency
Processor Coherency State
Response (tpcsr )
SCClkDiv Min †
Latency ‡ (PClk cycles)
‡ This latency assumes no other previously issued external coherency requests are
outstanding. 1 to 3 additional PClk cycles may be required for synchronization with
SysClk depending on the SysClkDiv mode bits.
* This value assumes a 32-word secondary cache block size.
† This value assumes the external coherency request hits a cached or outgoing buffer
entry.
‡‡ This value assumes the external coherency request does not hit a cached or outgoing
buffer entry, the secondary cache is not busy, and the external coherency request hits in
the MRU way of the secondary cache. If the external coherency request misses in the
most-recently used (MRU) way of the secondary cache, 1 to 3 additional PClk cycles are
required to query the LRU way of the secondary cache, depending on the SCClkDiv
mode bits.
** This value assumes the external coherency request does not hit a cached or outgoing
buffer entry, the secondary cache just commenced an index-conflicting CACHE Hit
WriteBack Invalidate (S), and the external coherency request misses in the secondary
cache MRU way.
†† This value assumes the external coherency request hits an outgoing buffer entry.
‡‡‡ This value assumes the external coherency request does not hit a cached or outgoing
buffer entry, the secondary cache is not busy, the external coherency request hits in the
MRU way of the secondary cache, no subset primary data cache blocks are inconsistent,
and the external coherency request is secondary cache block-aligned. If the external
coherency request misses in the MRU way of the secondary cache, 1 to 3 additional PClk
cycles are required to query the LRU way of the secondary cache, depending on the
SCClkDiv mode bits.
*** This value assumes the external coherency request does not hit a cached or outgoing
buffer entry, the secondary cache just commenced an index-conflicting CACHE Hit
WriteBack Invalidate (S), the external coherency request hits in the LRU way of the
secondary cache, all subset primary data cache blocks are inconsistent, and the external
coherency request is not secondary cache block-aligned.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
Processor Coherency Data
Response * (tpcdr )
Typ ‡‡‡ Max ***
Typ ‡‡ Max ** Min ††
1 5 10 39 8 28 70
1.5 5 13 48 8 33 88
2 5 14 59 8 38 105
2.5 5 16 71 8 43 128
3 5 17 79 8 43 141