MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

146 Chapter 6.
External Coherency Request Latency
Cycle
SysClk
Master
SysReq*
SysGnt*
SysRel*
SysCmd(11:0)
SysCmdPar
SysAD(63:0)
SysADChk(7:0)
SysVal*
SysRdRdy*
SysWrRdy*
SysState(2:0)
SysStatePar
SysStateVal*
SysResp(4:0)
SysRespPar
SysRespVal*
This section describes the R10000 external coherency request latency. Figure 6-26
depicts the following:
• an external coherency request which targets the processor
• the resulting processor coherency state response
• the potential processor coherency data response
Two external coherency request latency parameters are also defined:
• the processor coherency state response latency, tpcsr , specifies the time
from external coherency request to processor coherency state response
• the processor coherency data response latency, tpcdr , specifies the time
from the external coherency request to the processor coherency data
response if a master, or to the assertion of the processor coherency data
response indication on SysState[0] if a slave.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
EA EA EA EA EA EA EA EA EA EA - P0 P0 P0 P0 P0 P0 ExtCoh
Adr
0 DrtExc 0
1
0
t pcsr
t pcdr
Figure 6-26 External Coherency Request Latency Parameters
Empty RspDat RspDat RspLst
Dat0 Dat14 Dat15
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual