MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 145
Errata
Processor Requests that
are Pending Response
Coherent block read
Upgrade
Table 6-29 External Coherency Conflict Resolution
Conflicting External
Resolution
Coherency Request
Intervention shared The external agent responds to the external
coherency requestor that the block is Invalid. At
some later time, the external agent supplies an
external response to the processor coherent
block read request that is pending response. ‡
Intervention exclusive
Invalidate
The external agent responds to the external
coherency requestor that the block is Shared. At
Intervention shared some later time, the external agent supplies an
external response to the processor upgrade
request that is pending response. *
Intervention exclusive The external agent issues the conflicting external
coherency request to the processor. The
processor allows the conflicting external
coherency request to proceed and supplies a
Shared processor coherency state response. After
observing the processor coherency state
response, the external agent provides an external
ACK completion response for the conflicting
Invalidate
external coherency request. At some later time,
the external agent supplies an external response
for the processor upgrade request that is
pending response. This external response may
not be an external ACK completion response
unless it is associated with an external block data
response.
‡ Although it is not required, the external agent may choose to issue the conflicting external coherency request to R10000 and the
processor will return an invalid processor coherency state response.
* Although it is not required, the external agent may choose to issue the conflicting external coherency request to R10000 and the
processor will return a shared processor coherency state response.
Revised the two footnotes in Table 6-29 above.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997