MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

142 Chapter 6.
External Coherency Request Action
Secondary Cache
Block
Former State
Invalid
Shared
CleanExclusive
DirtyExclusive
Table 6-27 indicates the action taken for external coherency requests that target the
processor.
Table 6-27 Action Taken for External Coherency Requests that Target the R10000 Processor †
Type of
External Request
Intervention shared
Intervention exclusive
Invalidate
Intervention shared
Intervention exclusive
Invalidate
Intervention shared
Intervention exclusive
Invalidate ‡
Intervention shared *
Intervention exclusive
Invalidate ∗
Secondary
Cache Block
New State
Invalid
Invalid
Invalid
Shared
Invalid
Invalid
Shared
Invalid
Invalid
Shared
Invalid
Invalid
‡ This should not occur under normal circumstances.
* The processor coherency data response must be written back to memory.
Processor
Coherency State
Response
SysState[1:0]
Processor
Coherency
Data
Response
Required?
† These actions are taken in cases where there are no internal coherency conflicts. For
exceptions due to internal coherency conflicts, please refer to Table 6-28.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
0
0
0
1
1
1
2
2
2
3
3
3
No
No
No
No
No
No
No
No
No
Yes
Yes
No
Processor
Coherency Data
Response State
SysCmd[2:1]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Shared
DirtyExclusive
N/A