MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 141
6.18 System Interface Coherency
External Intervention Shared Request
External Intervention Exclusive Request
External Invalidate Request
The System interface supports external intervention shared, intervention
exclusive, and invalidate coherency requests. These requests are used by an
external agent or other R10000 processors on the cluster bus to maintain cache
coherency.
Each external coherency request that targets an R10000 results in a processor
coherency state response. Additionally, each external intervention request that
targets the R10000 and hits a DirtyExclusive secondary cache block results in a
processor coherency data response.
External coherency requests and the corresponding processor coherency state
responses are handled in FIFO order.
An external intervention shared request is used by an external agent to obtain a
Shared copy of a cache block. If the desired block resides in the processor cache, it
is marked Shared.
If the secondary cache block’s former state was DirtyExclusive, the processor
issues a processor coherency data response.
An external intervention exclusive request is used by an external agent to obtain
an Exclusive copy of a cache block. If the desired block resides in the processor
cache, it is marked Invalid.
If the secondary cache block’s former state was DirtyExclusive, the processor
issues a processor coherency data response.
An external invalidate request is used by an external agent to invalidate a cache
block. If the desired block resides in the processor cache, it is marked Invalid.
Under normal circumstances, the secondary cache block former state should not
be CleanExclusive or DirtyExclusive.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997