MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 137
Processor Response Protocol
Processor responses are supplied by the processor in response to external
coherency requests that target the processor. The R10000 processor issues a
processor coherency state response for each external coherency request that
targets the processor. The processor issues a processor coherency data response
for each external intervention request that targets the processor and hits a
DirtyExclusive secondary cache block.
Processor coherency state responses are issued by the processor in the same order
that the corresponding external coherency requests are received. Processor
coherency state and data responses may occur in adjacent SysClk cycles.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997