MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

136 Chapter 6.
External Interrupt Request Protocol
Cycle
SysClk
Master
SysReq*
SysGnt*
SysRel*
SysCmd(11:0)
SysCmdPar
SysAD(63:0)
SysADChk(7:0)
SysVal*
SysRdRdy*
SysWrRdy*
SysState(2:0)
SysStatePar
SysStateVal*
SysResp(4:0)
SysRespPar
SysRespVal*
An external agent issues an external interrupt request to interrupt the normal
instruction flow of the processor.
An external agent issues an external interrupt request with a single address cycle.
This address cycle consists of the following:
• negating SysCmd[11]
• driving the special command on SysCmd[7:5]
• driving the interrupt special cause indication on SysCmd[4:3]
• driving the ECC check indication on SysCmd[0]
• driving the target indication on SysAD[63:60]
• driving the Interrupt register write enables on SysAD[20:16]
• driving the Interrupt register values on SysAD[4:0]
• asserting SysVal*
An external agent may only issue an external interrupt request address cycle when
the System interface is in slave state.
Figure 6-23 depicts three external interrupt requests. Since the System interface is
initially in master state, the external agent must first negate SysGnt* and then wait
until the processor relinquishes mastership of the System interface by asserting
SysRel*.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
P0 P0 P0 P0 P0 - EA EA EA EA EA EA EA EA EA EA EA
Figure 6-23 External Interrupt Request Protocol
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
Int
Adr
Int
Adr
Int
Adr