MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 121
Processor Upgrade Request Protocol
A processor upgrade request results from a store or prefetch exclusive that hits a
Shared block in the secondary cache.
As shown in Figure 6-14, the processor issues a processor upgrade request with a
single address cycle. This address cycle consists of the following:
• negating SysCmd[11]
• driving a free request number on SysCmd[10:8]
• driving the upgrade command on SysCmd[7:5]
• driving the upgrade cause indication on SysCmd[4:3]
• driving the secondary cache block former state on SysCmd[2:1]
• asserting SysCmd[0]
• driving the target indication on SysAD[63:60]
• driving the secondary cache block way on SysAD[57]
• driving the physical address on SysAD[39:0]
• asserting SysVal*
The processor may only issue a processor upgrade request address cycle when the
following are true:
• the System interface is in master state
• SysRdRdy* was asserted two SysClk cycles previously
• the maximum number of outstanding processor requests specified by
the PrcReqMax mode bits is not exceeded
• there is a free request number
• the processor is not the target of a conflicting outstanding external
coherency request
A single processor may have as many as four processor upgrade requests
outstanding on the System interface at any given time.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997