MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library
MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library
MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library
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Table of Contents xv<br />
SysAD[63:0] Address Cycle Encoding....................................................................102<br />
SysAD[63:0] Data Cycle Encoding ..........................................................................104<br />
SysState[2:0] Encoding ........................................................................................................104<br />
SysResp[4:0] Encoding ........................................................................................................105<br />
Interrupts.........................................................................................................................................105<br />
Hardware Interrupts............................................................................................................105<br />
Software Interrupts ..............................................................................................................106<br />
Timer Interrupt.....................................................................................................................106<br />
Nonmaskable Interrupt.......................................................................................................106<br />
Protocol Abbreviations..................................................................................................................107<br />
System Interface Arbitration.........................................................................................................108<br />
System Interface Arbitration Rules....................................................................................109<br />
Uniprocessor System ...........................................................................................................110<br />
Multiprocessor System Using Cluster Bus .......................................................................111<br />
System Interface Request and Response Protocol.....................................................................112<br />
Processor Request Protocol.................................................................................................112<br />
Processor Block Read Request Protocol..................................................................113<br />
Processor Double/Single/Partial-Word Read Request Protocol........................115<br />
Processor Block Write Request Protocol.................................................................117<br />
Processor Double/Single/Partial-Word Write Request Protocol.......................119<br />
Processor Upgrade Request Protocol......................................................................121<br />
Processor Eliminate Request Protocol.....................................................................123<br />
Processor Request Flow Control Protocol ..............................................................125<br />
External Response Protocol ................................................................................................127<br />
External Block Data Response Protocol..................................................................127<br />
External Double/Single/Partial-Word Data Response Protocol........................129<br />
External Completion Response Protocol ................................................................130<br />
External Request Protocol...................................................................................................132<br />
External Intervention Request Protocol..................................................................133<br />
External Allocate Request Number Request Protocol ..........................................134<br />
External Invalidate Request Protocol......................................................................135<br />
External Interrupt Request Protocol........................................................................136<br />
Processor Response Protocol ..............................................................................................137<br />
Processor Coherency State Response Protocol ......................................................138<br />
Processor Coherency Data Response Protocol ......................................................139<br />
System Interface Coherency .........................................................................................................141<br />
External Intervention Shared Request ..............................................................................141<br />
External Intervention Exclusive Request..........................................................................141<br />
External Invalidate Request................................................................................................141<br />
External Coherency Request Action..................................................................................142<br />
Coherency Conflicts.............................................................................................................143<br />
Internal Coherency Conflicts....................................................................................143<br />
External Coherency Conflicts...................................................................................144<br />
External Coherency Request Latency......................................................................146<br />
<strong>MIPS</strong> <strong>R10000</strong> <strong>Microprocessor</strong> <strong>User's</strong> <strong>Manual</strong> Version 2.0 of January 29, 1997