MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Table of Contents xv
SysAD[63:0] Address Cycle Encoding....................................................................102
SysAD[63:0] Data Cycle Encoding ..........................................................................104
SysState[2:0] Encoding ........................................................................................................104
SysResp[4:0] Encoding ........................................................................................................105
Interrupts.........................................................................................................................................105
Hardware Interrupts............................................................................................................105
Software Interrupts ..............................................................................................................106
Timer Interrupt.....................................................................................................................106
Nonmaskable Interrupt.......................................................................................................106
Protocol Abbreviations..................................................................................................................107
System Interface Arbitration.........................................................................................................108
System Interface Arbitration Rules....................................................................................109
Uniprocessor System ...........................................................................................................110
Multiprocessor System Using Cluster Bus .......................................................................111
System Interface Request and Response Protocol.....................................................................112
Processor Request Protocol.................................................................................................112
Processor Block Read Request Protocol..................................................................113
Processor Double/Single/Partial-Word Read Request Protocol........................115
Processor Block Write Request Protocol.................................................................117
Processor Double/Single/Partial-Word Write Request Protocol.......................119
Processor Upgrade Request Protocol......................................................................121
Processor Eliminate Request Protocol.....................................................................123
Processor Request Flow Control Protocol ..............................................................125
External Response Protocol ................................................................................................127
External Block Data Response Protocol..................................................................127
External Double/Single/Partial-Word Data Response Protocol........................129
External Completion Response Protocol ................................................................130
External Request Protocol...................................................................................................132
External Intervention Request Protocol..................................................................133
External Allocate Request Number Request Protocol ..........................................134
External Invalidate Request Protocol......................................................................135
External Interrupt Request Protocol........................................................................136
Processor Response Protocol ..............................................................................................137
Processor Coherency State Response Protocol ......................................................138
Processor Coherency Data Response Protocol ......................................................139
System Interface Coherency .........................................................................................................141
External Intervention Shared Request ..............................................................................141
External Intervention Exclusive Request..........................................................................141
External Invalidate Request................................................................................................141
External Coherency Request Action..................................................................................142
Coherency Conflicts.............................................................................................................143
Internal Coherency Conflicts....................................................................................143
External Coherency Conflicts...................................................................................144
External Coherency Request Latency......................................................................146
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997