MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 119
Processor Double/Single/Partial-Word Write Request Protocol
A processor double/single/partial-word write request results from an uncached
store or incompletely gathered uncached accelerated block.
As shown in Figure 6-13, the processor issues a processor double/single/partialword
write request with a single address cycle immediately followed by a single
data cycle.
The address cycle consists of the following:
• negating SysCmd[11]
• driving the double/single/partial-word write command on
SysCmd[7:5]
• driving the write cause indication on SysCmd[4:3]
• driving the data size indication on SysCmd[2:0]
• driving the target indication on SysAD[63:60]
• driving the uncached attribute on SysAD[59:58]
• driving the physical address on SysAD[39:0]
• asserting SysVal*
The data cycle consists of the following:
• asserting SysCmd[11]
• driving the request last data type indication on SysCmd[4:3]
• driving the write data on SysAD[63:0]
• asserting SysVal*
The processor may only issue a processor double/single/partial-word write
request address cycle when the System interface is in master state and SysWrRdy*
was asserted two SysClk cycles previously.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997