MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

118 Chapter 6.
Cycle
SysClk
Master
SysReq*
SysGnt*
SysRel*
SysCmd(11:0)
SysCmdPar
SysAD(63:0)
SysADChk(7:0)
SysVal*
SysRdRdy*
SysWrRdy*
SysState(2:0)
SysStatePar
SysStateVal*
SysResp(4:0)
SysRespPar
SysRespVal*
The processor may negate SysVal* between data cycles of a processor block write
request only if the SCClk frequency is less than half of the SysClk frequency.
The processor may only issue a processor block write request address cycle when
the following are true:
• the System interface is in master state
• SysWrRdy* was asserted two SysClk cycles previously
• the processor is not the target of a conflicting outstanding external
coherency request
Figure 6-12 depicts two adjacent processor block write requests. Since the System
interface is initially in slave state, the processor must first assert SysReq* and then
wait until the external agent relinquishes mastership of the System interface by
asserting SysGnt* and SysRel*.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
EA EA EA EA - P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 BlkWr ReqDat ReqDat ReqLst
Adr Dat0 Dat14 Dat15
BlkWr ReqDat ReqDat ReqLst
Adr Dat0 Dat14 Dat15
Figure 6-12 Processor Block Write Request Protocol
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual