MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 117
Errata
Processor Block Write Request Protocol
A processor block write request results from the following:
• replacement of a DirtyExclusive secondary cache block due to a load,
store, or prefetch secondary cache miss
• a CACHE Index WriteBack Invalidate (S) or Hit WriteBack Invalidate
(S) instruction
• a completely gathered uncached accelerated block
As shown in Figure 6-12, the processor issues a processor block write request with
a single address cycle followed by 8 or 16 data cycles.
The address cycle consists of the following:
• negating SysCmd[11]
• driving the block write command on SysCmd[7:5]
• driving the write cause indication on SysCmd[4:3]
• driving the target indication on SysAD[63:60]
• driving the physical address on SysAD[39:0]
• asserting SysVal*
If the processor block write request results from the writeback of a secondary
cache block, the Dirty Exclusive secondary cache block former state is driven on
SysAD[2:1], the secondary cache block way is driven on SysAD[57] and
SysCmd[0] is asserted.
If the processor block write request results from a completely gathered uncached
accelerated block, the uncached attribute is driven on SysAD[59:58] and
SysCmd[0] is negated.
Each data cycle consists of the following:
• asserting SysCmd[11]
• driving the data quality indication on SysCmd[5]
• driving the data type indication on SysCmd[4:3]
• driving the data on SysAD[63:0]
• asserting SysVal*
The first 7 or 15 data cycles have a request data type indication, and the last data
cycle has a request last data type indication.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997