MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 115
Processor Double/Single/Partial-Word Read Request Protocol
A processor double/single/partial-word read request results from an uncached
instruction fetch or load.
The processor issues a processor double/single/partial-word read request with a
single address cycle. The address cycle consists of:
• negating SysCmd[11]
• driving a free request number on SysCmd[10:8]
• driving the double/single/partial-word read command on
SysCmd[7:5]
• driving the read cause indication on SysCmd[4:3]
• driving the data size indication on SysCmd[2:0]
• driving the target indication on SysAD[63:60]
• driving the uncached attribute on SysAD[59:58]
• driving the physical address on SysAD[39:0]
• asserting SysVal*
The processor may only issue a processor double/single/partial-word read
request address cycle when:
• the System interface is in master state
• SysRdRdy* was asserted two SysClk cycles previously
• the maximum number of outstanding processor requests specified by
the PrcReqMax mode bits is not exceeded
• there is a free request number
A single processor may have a maximum of one processor double/single/partialword
read request outstanding on the System interface at any given time.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997