MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

112 Chapter 6.
6.17 System Interface Request and Response Protocol
Processor Request Protocol
The following sections detail the System interface request and response protocol.
A 32-word secondary cache block size is assumed in the examples below.
A processor request is generated when the R10000 processor requires a system
resource.
The processor may only issue a processor request when the System interface is in
master state. If the System interface is in master state, the processor may issue a
processor request immediately. Processor requests may occur in adjacent SysClk
cycles. If the System interface is not in master state, the processor must first assert
SysReq*, and then wait for the external agent to relinquish mastership of the
System interface bus by asserting SysGnt* and SysRel*.
When multiple, nonconflicting processor requests and/or coherency data
responses are ready and meet all issue requirements, the processor uses the
following priority:
• block read and upgrade requests have the highest priority, followed by
• processor coherency data responses,
• processor eliminate and typical block write requests,
• processor double/single/partial-word read/write and uncached
accelerated block write requests, which have the lowest priority.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual