MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

110 Chapter 6.
Uniprocessor System
Cycle
SysClk
Master
SysReq*
SysGnt*
SysRel*
SysCmd(11:0)
SysVal*
Figure 6-6 shows how the System interface arbitration signals are used in a
uniprocessor system. Note that this same configuration would be used in a
multiprocessor system using dedicated external agents.
R10000
SysReq*
SysGnt*
SysRel*
Figure 6-6 Arbitration Signals for Uniprocessor System
Figure 6-7 is an example of the operation of the System interface arbitration in a
uniprocessor system. The Master row in the following figures indicates which
device is driving the System interface bidirectional signals (P 0 and EA in
Figure 6-7). When this row contains a dash (-), as shown in Cycle 12 of Figure 6-7,
mastership of the System interface is changing and no device is driving the System
interface bidirectional signals for this one dead SysClk cycle.
The external agent generally asserts the SysGnt* signal, which allows the
processor to issue requests at any time.
When the external agent needs to return an external data response, it negates
SysGnt* for a minimum of one cycle, waits for the processor to assert SysRel*, and
then begins driving the System interface bus after one dead SysClk cycle.
Figure 6-7 Arbitration Protocol for Uniprocessor System
SysReq*
SysGnt*
SysRel*
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
External
Agent
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 - EA EA EA - P0 BlkRd DSPWr ReqLst BlkRd BlkRd
Minimum of 1 Cycle
BlkRd RspDat RspDat RspLst BlkRd