MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

xiv Table of Contents
6
System Interface Operations
Request and Response Cycles.......................................................................................................80
System Interface Frequencies .......................................................................................................80
Register-to-Register Operation.....................................................................................................80
System Interface Signals................................................................................................................81
Master and Slave States .................................................................................................................81
Connecting to an External Agent .................................................................................................81
Cluster Bus ......................................................................................................................................82
System Interface Connections.......................................................................................................83
Uniprocessor System ...........................................................................................................83
Multiprocessor System Using Dedicated External Agents ............................................84
Multiprocessor System Using the Cluster Bus.................................................................85
System Interface Requests and Responses..................................................................................86
Processor Requests...............................................................................................................86
External Responses...............................................................................................................87
External Requests .................................................................................................................87
Processor Responses ............................................................................................................87
Outstanding Requests and Request Numbers .................................................................87
Request and Response Relationship..................................................................................88
System Interface Buffers................................................................................................................89
Cluster Request Buffer.........................................................................................................89
Cached Request Buffer ........................................................................................................89
Incoming Buffer....................................................................................................................90
Outgoing Buffer....................................................................................................................91
Uncached Buffer ...................................................................................................................92
System Interface Flow Control .....................................................................................................93
Processor Write and Eliminate Request Flow Control ...................................................93
Processor Read and Upgrade Request Flow Control......................................................93
Processor Coherency Data Response Flow Control ........................................................93
External Request Flow Control ..........................................................................................93
External Data Response Flow Control ..............................................................................93
System Interface Block Data Ordering ........................................................................................94
External Block Data Responses ..........................................................................................94
Processor Coherency Data Responses...............................................................................94
Processor Block Write Requests .........................................................................................94
System Interface Bus Encoding ....................................................................................................95
SysCmd[11:0] Encoding ......................................................................................................95
SysCmd[11] Encoding ...............................................................................................95
SysCmd[10:0] Address Cycle Encoding..................................................................95
SysCmd[10:0] Data Cycle Encoding ........................................................................99
SysCmd[11:0] Map .....................................................................................................101
SysAD[63:0] Encoding .........................................................................................................102
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual