MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

106 Chapter 6.
Software Interrupts
Timer Interrupt
Nonmaskable Interrupt
SysAD(4:0)
Interrupt Value
4
3 2 1 0
19 18 17 16
Figure 6-5 Hardware Interrupts
The two software interrupts are accessible as bits 9:8 of the Cause register, as shown
in Figure 6-5. An MTC0 instruction is used to write these bits.
The timer interrupt is accessible as bit 15 of the Cause register, IP[7], as shown in
Figure 6-5. This bit is set when one of the following occurs:
• the Count register is equal to the Compare register
• either one of the two performance counters overflows
A nonmaskable interrupt is accessible to an external agent as the SysNMI* signal.
To post a nonmaskable interrupt, an external agent asserts SysNMI* for at least
one SysClk cycle.
The processor recognizes the nonmaskable interrupt on the first SysClk cycle that
SysNMI* is asserted. After the nonmaskable interrupt is serviced, an external
agent may post another nonmaskable interrupt by first negating SysNMI* for at
least one SysClk cycle, and reasserting SysNMI* for at least one SysClk cycle.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
20
SysAD(20:16)
Write Enables
8
9
10
11
12
13
14
15
IP[0]
IP[1]
IP[2]
IP[3]
IP[4]
IP[5]
IP[6]
IP[7]
Interrupt register
Cause(15:08)
Software
Interrupts
Hardware
Interrupts
Timer
Interrupt