MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

104 Chapter 6.
SysAD[63:0] Data Cycle Encoding
SysState[2:0] Encoding
During System interface data cycles, when less than a doubleword is transferred
on the SysAD[63:0] bus, the valid byte lanes depend on the request address and
the MemEnd mode bit.
For example, consider the data cycle for a byte request whose address modulo 8 is
1. When MemEnd is negated (little endian), the SysAD[15:8] byte lane is valid.
When MemEnd is asserted (big endian), the SysAD[55:48] byte lane is valid.
The processor provides a processor coherency state response by driving the
targeted secondary cache block tag quality indication on SysState[2], driving the
targeted secondary cache block former state on SysState[1:0] and asserting
SysStateVal* for one SysClk cycle. Table 6-24 presents the encoding of the
SysState[2:0] bus when SysStateVal* is asserted.
Table 6-24 Encoding of SysState[2:0] when SysStateVal* Asserted
SysState[2] Secondary cache block tag quality indication
0 Tag is good
1 Tag is bad
SysState[1:0] Secondary cache block former state
0 Invalid
1 Shared
2 CleanExclusive
3 DirtyExclusive
When SysStateVal* is negated, SysState[0] indicates if a processor coherency data
response is ready for issue. Table 6-25 presents the encoding of the SysState[2:0]
bus when SysStateVal* is negated.
Table 6-25 Encoding of SysState[2:0] When SysStateVal* Negated
SysState[2:1] Reserved
SysState[0] Processor coherency data response indication
0 Not ready for issue
1 Ready for issue
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual