MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 103
SysAD[57]
SysAD[56:40]
SysAD[39:0]
During the address cycle of processor block read, typical block write, upgrade,
and eliminate requests, SysAD[57] contains the secondary cache block way
indication. This information may be useful for system designs implementing a
duplicate tag or a directory-based coherency protocol.
When processor is in master state, it drives SysAD[56:40] to zero during address
cycles.
During the address cycle of processor and external requests, SysAD[39:0] contain
the physical address.
Table 6-22 presents the processor request address cycle address alignment.
Table 6-22 Processor Request Address Cycle Alignment
Processor Request Type Address Alignment
Address Bits Which
Are Driven to 0
Block read Quadword 3:0
Doubleword read/write Doubleword 2:0
Singleword read/write Singleword 1:0
Halfword read/write Halfword 0
Byte, tribyte, quintibyte, sextibyte,
septibyte read/write
Byte -
Block write Secondary cache block
5:0 (SCBlkSize = 0)
6:0 (SCBlkSize = 1)
Upgrade Quadword 3:0
Eliminate Secondary cache block
Table 6-23 presents the external coherency request address cycle address
alignment.
Table 6-23 External Coherency Request Address Cycle Alignment
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
5:0 (SCBlkSize = 0)
6:0 (SCBlkSize = 1)
External Request Type Address Alignment
Address Bits Which
Are Ignored
Intervention Quadword 3:0
Invalidate Secondary cache block
5:0 (SCBlkSize = 0)
6:0 (SCBlkSize = 1)