MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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100 Chapter 6. During data cycles, SysCmd[4:3] indicate the data type, as shown in Table 6-17. Processor block write and double/single/partial-word write requests use request data and request last data type indications. External data and processor coherency data responses use response data and response last data type indications. Table 6-17 Encoding of SysCmd[4:3] for Data Cycles SysCmd[4:3] Data type Indication 0 Request data 1 Response data 2 Request last 3 Response last During data cycles of an external block data response or processor coherency data response, SysCmd[2:1] contain the state of the cache block, as shown in Table 6-18. Table 6-18 Encoding of SysCmd[2:1] for Block Data Responses SysCmd[2:1] Cache Block State 0 Reserved 1 Shared 2 CleanExclusive 3 DirtyExclusive During data cycles, SysCmd[0] specifies whether ECC checking and correcting is to be performed for the SysAD[63:0] bus, as shown in Table 6-19. During processor data cycles, the processor asserts SysCmd[0]. Consequently, in a multiprocessor system using the cluster bus, ECC checking and correcting will be enabled for external block data responses resulting from processor coherency data responses. Table 6-19 Encoding of SysCmd[0] for External Data Cycles SysCmd[0] ECC check indication 0 ECC checking and correcting disable 1 ECC checking and correcting enable Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual
System Interface Operations 101 Cycle Type Processor address cycles Processor data cycles External address cycles External data cycles SysCmd[11:0] Map Table 6-20 presents a map for the SysCmd[11:0] bus. Table 6-20 SysCmd[11:0] Map Command 11 10 9 8 7 SysCmd[11:0] Bit 6 5 4 3 2 1 0 Coherent block read shared 0 0 0 Coherent block read exclusive Noncoherent block read Request number 0 0 0 1 1 0 Read cause Block state 1 Double/single/partial-word read 0 1 1 Data size Block write Double/single/partial-word write 0 0 1 1 0 0 0 1 Write cause Block state Data size 1 Upgrade Request number 1 1 0 Upgrade cause Block state 1 Reserved Reserved 0 0 Reserved Special Eliminate Reserved 0 Reserved 1 1 1 0 1 1 1 0 1 Block state Reserved 1 Double/single/partial-word write Block write Coherency data response 1 0 Request number 0 0 Data quality Data type 0 Block state 1 Intervention shared Intervention exclusive Allocate request number NOP 0 Request number X 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 X ECC X Invalidate Request number 1 1 0 ECC Special NOP Interrupt X 1 1 1 0 0 1 0 1 0 X X ECC NOP 1 1 X Block data response Double/single/partial-word data response 1 Request number X Data quality MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997 Data type Block state X ECC
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MIPS R10000 Microprocessor User’s
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Acknowledgments This book represent
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About This Manual Glossary Stylisti
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Table of Contents vii Contents Ackn
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Table of Contents ix Superscalar In
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Table of Contents xi 3 Interface Si
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Table of Contents xiii 5 Secondary
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Table of Contents xv SysAD[63:0] Ad
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Table of Contents xvii 7 Clock Sign
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Table of Contents xix 9 Error Prote
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Table of Contents xxi 11 JTAG Inter
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Table of Contents xxiii 13 Packagin
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Table of Contents xxv Branch on Cop
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Table of Contents xxvii 16 Memory M
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Table of Contents xxix 18 A Cache T
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1. Introduction to the R10000 Proce
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Introduction to the R10000 Processo
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2. System Configurations The R10000
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System Configurations 35 2.2 Multip
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3. Interface Signal Descriptions Th
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Interface Signal Descriptions 39 3.
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4. Cache Organization and Coherency
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Cache Organization and Coherency 47
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Page 89 and 90: 5. Secondary Cache Interface The pr
Page 91 and 92: Secondary Cache Interface 61 5.2 Se
Page 93 and 94: Secondary Cache Interface 63 Indexi
Page 95 and 96: Secondary Cache Interface 65 Errata
Page 97 and 98: Secondary Cache Interface 67 SCTag(
Page 99 and 100: Secondary Cache Interface 69 4-Word
Page 101 and 102: Secondary Cache Interface 71 16 or
Page 103 and 104: Secondary Cache Interface 73 5.7 Wr
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Page 107 and 108: Secondary Cache Interface 77 Tag Wr
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Page 129: System Interface Operations 99 Erra
Page 133 and 134: System Interface Operations 103 Sys
Page 141 and 142: System Interface Operations 111 Mul
Page 143 and 144: System Interface Operations 113 Err
Page 145 and 146: System Interface Operations 115 Pro
Page 157 and 158: System Interface Operations 127 Ext
Page 161 and 162: System Interface Operations 131 Cyc
Page 173 and 174: System Interface Operations 143 Coh
Page 177 and 178: System Interface Operations 147 The
Page 179 and 180: System Interface Operations 149 In
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System Interface Operations 151 Cyc
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System Interface Operations 153 6.2
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7. Clock Signals The R10000 process
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Clock Signals 157 7.2 Secondary Cac
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8. Initialization This section desc
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Initialization 161 Errata Vcc VccQ[
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Initialization 163 8.4 Soft Reset S
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Initialization 165 Table 8-1 (cont.
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9. Error Protection and Handling Th
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Error Protection and Handling 169 9
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Error Protection and Handling 177 D
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Error Protection and Handling 179 T
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Error Protection and Handling 181 E
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Error Protection and Handling 183 W
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Error Protection and Handling 185 P
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10. CACHE Instructions This chapter
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CACHE Instructions 189 TLB Refill a
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CACHE Instructions 191 Op Field Enc
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CACHE Instructions 193 10.4 Index W
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CACHE Instructions 195 10.7 Index L
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CACHE Instructions 197 10.11 Hit In
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CACHE Instructions 199 10.15 Hit Wr
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CACHE Instructions 201 10.17 Index
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11. JTAG Interface Operation Errata
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JTAG Interface Operation 205 11.2 I
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JTAG Interface Operation 207 ‡ Wi
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12. Electrical Specifications This
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Electrical Specifications 211 DCOk
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Electrical Specifications 213 Unuse
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Electrical Specifications 215 12.2
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Electrical Specifications 217 12.3
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13. Packaging The R10000 microproce
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Packaging 221 Electrical Characteri
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Packaging 223 Figure 13-1 R10000 59
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Packaging 225 Table 13-3 (cont.) Si
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Packaging 231 Figure 13-3 599LGA PW
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Packaging 233 Figure 13-5 599LGA Bo
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14. Coprocessor 0 This chapter desc
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Coprocessor 0 237 14.1 Index Regist
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Coprocessor 0 239 14.3 EntryLo0 (2)
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Coprocessor 0 241 14.4 Context (4)
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Coprocessor 0 243 14.6 Wired Regist
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Coprocessor 0 245 14.9 EntryHi Regi
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Coprocessor 0 247 CU2 CU2 CU1 CU1 C
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Coprocessor 0 249 Diagnostic Status
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Coprocessor 0 251 Coprocessor Acces
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Coprocessor 0 253 Table 14-13 Cause
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Coprocessor 0 255 14.13 Processor R
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Coprocessor 0 257 14.15 Load Linked
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Coprocessor 0 259 14.17 XContext Re
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Coprocessor 0 261 14.19 Diagnostic
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Coprocessor 0 263 Errata There are
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Coprocessor 0 265 Errata Errata The
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Coprocessor 0 267 Event 1 for Count
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Coprocessor 0 269 Event 6 for Count
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Coprocessor 0 271 Event 14 for Coun
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Coprocessor 0 273 14.21 ECC Registe
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Coprocessor 0 275 CacheErr Register
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Coprocessor 0 277 CacheErr Register
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Coprocessor 0 279 Errata Primary In
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Coprocessor 0 281 Errata Errata Sec
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Coprocessor 0 283 Primary Data Cach
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Coprocessor 0 285 14.25 CP0 Instruc
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Coprocessor 0 287 14.27 CACHE Instr
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Coprocessor 0 289 Cache CACHE (cont
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Coprocessor 0 291 14.29 DMTC0 Instr
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Coprocessor 0 293 14.31 MFC0 Instru
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Coprocessor 0 295 MTPS 31 Format: M
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Coprocessor 0 297 14.34 TLBP Instru
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Coprocessor 0 299 14.36 TLBWI Instr
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15. Floating-Point Unit This sectio
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Floating-Point Unit 303 15.2 Floati
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Floating-Point Unit 305 Load and St
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Floating-Point Unit 307 63 63 Doubl
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Floating-Point Unit 309 Floating-Po
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Floating-Point Unit 311 Loading the
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Floating-Point Unit 313 Moves and C
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16. Memory Management This section
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Memory Management 317 Addressing Mo
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Memory Management 319 32-bit User M
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Memory Management 321 32-bit Superv
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Memory Management 323 32-bit Kernel
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Memory Management 325 0X BFFFFFFF 0
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Memory Management 327 64-bit Virtua
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Memory Management 329 Using the TLB
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17. CPU Exceptions This chapter des
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CPU Exceptions 333 17.3 TLB Refill
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CPU Exceptions 335 Priority of Exce
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CPU Exceptions 337 Soft † Reset E
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CPU Exceptions 339 NMI Exception Ca
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CPU Exceptions 341 TLB Exceptions T
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CPU Exceptions 343 TLB Invalid Exce
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CPU Exceptions 345 Cache Error Exce
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CPU Exceptions 347 Integer Overflow
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CPU Exceptions 349 System Call Exce
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CPU Exceptions 351 Reserved Instruc
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CPU Exceptions 353 Floating-Point E
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CPU Exceptions 355 Interrupt Except
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CPU Exceptions 357 17.5 COP0 Instru
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18. Cache Test Mode The R10000 proc
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Cache Test Mode 361 18.3 Entering C
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Cache Test Mode 363 18.5 SysAD(63:0
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Cache Test Mode 365 Auto-Increment
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Cache Test Mode 367 Auto-Increment
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A. Glossary The following terms are
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A.6 Dynamic Scheduling The R10000 p
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A.11 Nonblocking Loads and Stores M
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A.13 Logical and Physical Registers
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Index I-1 Index Numerics 16-word, c
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Index I-3 uncached accelerated, des
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Index I-5 branch on CP0 instruction
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Index I-7 F fetch pipeline 6, 17 fe
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Index I-9 TLBWR 285, 300 unsupporte
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Index I-11 NMI see also nonmaskable
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Index I-13 CP0 (description of) 235
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Index I-15 SysAD[20:16] interrupt r
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Index I-17 SysWrRdy, signal 41, 118
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