MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 99
Errata
SysCmd[10:0] Data Cycle Encoding
During the address cycle of external special requests, SysCmd[4:3] contain the
external special cause indication, as shown in Table 6-13. This information is used
to differentiate between the various external special requests.
Table 6-13 Encoding of SysCmd[4:3] for External Special Requests
SysCmd[4:3] Special Cause Indication
0 Reserved
1 NOP
2 Interrupt
3 Reserved
During external address cycles, SysCmd[0] specifies whether ECC checking and
correcting is to be performed for the SysAD[63:0] bus, as shown in Table 6-14.
During the address cycle of processor block read, data typical block write,
upgrade, and eliminate requests, the processor asserts SysCmd[0]. Consequently,
in a multiprocessor system using the cluster bus, ECC checking and correcting is
enabled for external coherency requests resulting from processor coherent block
read and upgrade requests.
Table 6-14 Encoding of SysCmd[0] for External Address Cycles
SysCmd[0] ECC check indication
0 ECC checking and correcting disable
1 ECC checking and correcting enable
During the data cycles of an external data response or a processor coherency data
response, SysCmd[10:8] contain the request number associated with the original
request, as shown in Table 6-15.
Table 6-15 Encoding of SysCmd[10:8] for Data Responses
SysCmd[10:8] Request Number
During data cycles, SysCmd[5] indicates the data quality, as shown in Table 6-16.
Table 6-16 Encoding of SysCmd[5] for Data Cycles
SysCmd[5] Data quality indication
0 Data is good
1 Data is bad
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997