MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

96 Chapter 6.
During the address cycle of processor requests, SysCmd[7:5] contain the
command, as shown in Table 6-4.
Table 6-4 Encoding of SysCmd[7:5] for Processor Requests
SysCmd[7:5] Command
0 Coherent block read shared
1 Coherent block read exclusive
2 Noncoherent block read
3 Double/single/partial-word read
4 Block write
5 Double/single/partial-word write
6 Upgrade
7 Special
During the address cycle of processor read requests, SysCmd[4:3] contain the read
cause indication, as shown in Table 6-5. This information is useful in handling the
associated external response.
Table 6-5 Encoding of SysCmd[4:3] for Processor Read Requests
SysCmd[4:3] Read Cause Indication
0 Instruction access
1 Data typical access
2 Data LL/LLD access
3 Data prefetch access
During the address cycle of processor write requests, SysCmd[4:3] contain the
write cause indication, as shown in Table 6-6. This information is useful in
handling the associated write data.
Table 6-6 Encoding of SysCmd[4:3] for Processor Write Requests
SysCmd[4:3] Write Cause Indication
0 Reserved
1 Data typical access
2 Data uncached accelerated sequential access
3 Data uncached accelerated identical access
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual