MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

94 Chapter 6.
6.12 System Interface Block Data Ordering
External Block Data Responses
Processor Coherency Data Responses
Processor Block Write Requests
During block data transfers on the System interface SysAD[63:0] bus, even
doublewords (Dat0, Dat2,...) always correspond to SCData[127:64], and odd
doublewords (Dat1, Dat3,...) always correspond to SCData[63:0].
During the address cycle of processor block read and upgrade requests, the
processor specifies a quadword-aligned address. The processor expects the
external block data response to be supplied in a subblock order sequence,
beginning at the specified quadword-aligned address.
The address of external intervention requests are internally aligned by the
processor to a quadword address. If the processor determines that it must issue a
processor coherency data response, it supplies the data in a subblock order
sequence beginning at the quadword-aligned address specified by the
corresponding external coherency request.
During the address cycle of processor block write requests, the processor specifies
a cache block-aligned address. During the subsequent data cycles for typical
processor block write requests, the processor supplies the data in sequence,
beginning with the secondary cache block-aligned address.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual