MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

System Interface Operations 93
6.11 System Interface Flow Control
The System interface supports a maximum request rate of one request per SysClk
cycle, and a maximum data rate of one doubleword per SysClk cycle.
Various flow control mechanisms are provided to limit these rates, as described
below.
Processor Write and Eliminate Request Flow Control
Processor Read and Upgrade Request Flow Control
Processor Coherency Data Response Flow Control
External Request Flow Control
External Data Response Flow Control
The processor can only issue a processor write or eliminate request if:
• the System interface is in master state
• SysWrRdy* was asserted two SysClk cycles previously
The processor can only issue a processor read or upgrade request if:
• the System interface is in master state
• SysRdRdy* was asserted two SysClk cycles previously
• the maximum number of outstanding processor requests specified by
the PrcReqMax mode bits is not exceeded
• there is a free request number
The processor can only issue a processor coherency data response if:
• the System interface is in master state
• SysWrRdy* was asserted two SysClk cycles previously
When the System interface is in Slave state, it is capable of accepting external
requests. An external agent may issue external requests in adjacent SysClk cycles.
Since the processor has an incoming buffer, an external agent may supply external
data response data in adjacent SysClk cycles, without regard to cache bandwidth
or internal resource availability.
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997