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MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

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88 Chapter 6.<br />

Request and Response Relationship<br />

‡ External completion response is required to free the request number.<br />

The relationship between processor and external requests, and their acceptable<br />

responses, is presented in Table 6-1. The data in this table is given with respect to<br />

a single processor, in either a uni- or multiprocessor system (independent of<br />

cluster/non-cluster configuration).<br />

Table 6-1 Request and Response Relationship<br />

Request Acceptable Response Sequences<br />

Processor block read request<br />

External NACK or ERR completion response<br />

0 or more external block data responses followed by a final external block<br />

data response with a coincidental or subsequent external ACK, NACK, or<br />

ERR completion response<br />

External NACK or ERR completion response<br />

Processor double/single/partial- 0 or more external double/single/partial-word data responses followed<br />

word read request<br />

by a final external double/single/partial-word data response with a<br />

coincidental or subsequent external ACK, NACK, or ERR completion<br />

response<br />

Processor block write request None<br />

Processor double/single/partial-<br />

None<br />

word write request<br />

External ACK, NACK, or ERR completion response<br />

Processor upgrade request<br />

0 or more external block data responses followed by a final external block<br />

data response with a coincidental or subsequent external ACK, NACK, or<br />

ERR completion response<br />

Processor eliminate request None<br />

External intervention request<br />

External allocate request number<br />

request<br />

Processor coherency state response followed by processor coherency data<br />

response (if DirtyExclusive) with a coincidental or subsequent external<br />

ACK, NACK, or ERR completion response ‡<br />

External ACK, NACK, or ERR completion response *<br />

External invalidate request<br />

Processor coherency state response followed by external ACK, NACK, or<br />

ERR completion response *<br />

External interrupt request None<br />

Version 2.0 of January 29, 1997 <strong>MIPS</strong> <strong>R10000</strong> <strong>Microprocessor</strong> <strong>User's</strong> <strong>Manual</strong>

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