MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

80 Chapter 6.
6.1 Request and Response Cycles
6.2 System Interface Frequencies
6.3 Register-to-Register Operation
The System interface supports the following request and response cycles:
• Processor requests are generated by the processor, when it requires a
system resource.
• External responses are supplied by an external agent in response to a
processor request.
• External requests are generated by an external agent when it requires a
resource within the processor.
• Processor responses are supplied by the processor in response to an
external request.
The System interface operates at SysClk frequency, supplied by the external agent.
The internal processor clock, PClk, is derived from this same SysClk.
The SysClkDiv mode bits select a PClk to SysClk divisor of 1, 1.5, 2, 2.5, 3, 3.5, or
4, using the formula described in Chapter 7, the section titled “System Interface
Clock and Internal Processor Clock Domains.”
The System interface is designed to operate in the following register-to-register
fashion with the external agent:
• all System interface outputs are sourced directly from registers clocked
on the rising edge of SysClk
• all System interface inputs directly feed registers that are clocked on
the rising edge of SysClk
This allows the System interface to run at the highest possible clock frequency.
Version 2.0 of January 29, 1997 MIPS R10000 Microprocessor User's Manual