MIPS R10000 Microprocessor User's Manual - SGI TechPubs Library

Secondary Cache Interface 75
8-Word Write Sequence
Cycle
SCClk
SC[A,B]Addr(18:0)
SCTagLSBAddr
SC[A,B]DWay
SCData(127:0)
SCDataChk(9:0)
SC[A,B]DOE*
SC[A,B]DWr*
SC[A,B]DCS*
SCTWay
SCTag(25:0)
SCTagChk(6:0)
SCTOE*
SCTWr*
SCTCS*
An 8-word write sequence writes back a dirty block from the primary data cache
to the secondary cache.
Figure 5-8 depicts a secondary cache 8-word write sequence. SC(A,B)DWay are
driven with the way bit obtained from the primary data cache tag. The secondary
cache tag is not written since it was previously updated when the primary data
cache block was modified.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Adr0 Adr1
X
Dat0
Figure 5-8 8-Word Write Sequence
MIPS R10000 Microprocessor User's Manual Version 2.0 of January 29, 1997
Dat1