2005 PhD Research in Microelectronics and Electronics - Lirmm

2005 PhD Research 

in Microelectronics and Electronics 

PRIME 

Proceedings 

of the Conference 

- Volume I - 

Lausanne, Switzerland 

July 25 - 28, 2005 

PhD Research in Microelectronics and Electronics

2005 PhD Research 

in Microelectronics and Electronics 


of the Conference 

- Volume I - 

Lausanne, Switzerland 

July 25 - 28, 2005 

Organization Technical Co-Sponsorship 

PRIME 

PhD Research in Microelectronics and Electronics

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are 

permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those 

articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee 

indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, 

MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights 

Manager, IEEE Operations Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. All 

rights reserved. Copyright ©2005 by the Institute of Electrical and Electronics Engineers, Inc. 

IEEE Catalog Number: 05EX1148 

ISBN: 0-7803-9345-7 

Library of Congress Number: 2005928249 

I

Dear PhD Student, Dear Participant, 

Foreword 

We are pleased to welcome you to the very first edition of the PRIME Conference, held in Lausanne, 

Switzerland in 2005. Lausanne is located in a beautiful setting on the shores of the Lake of Geneva. 

We hope that you will take the opportunity to discover this attractive place combining great quality 

of life, culture, and an international touch. 

The Electronics Laboratories (LEG) of the Swiss Federal Institute of Technology (EPFL), Lausanne, 

has organized this Conference with the active help of the Electronics Micro-system Laboratory of the 

University of Pavia, Italy. 

PRIME 2005 is the 1st Edition of a new approach aiming at supporting the dissemination of results 

of PhD Research In Microelectronics and Electronics. The main goals are the following: 

� Friendly competition between the PhD Students. 

� Benchmark of the most promising PhD Students thanks to the ranking of the articles (e.g. 

acknowledgment of the gold leaf certificate to the first 10% PhD Students). 

� Creation of a network of excellence between the PhD Students. 

The authors of PRIME presentations come from Asia, North America and Europe. Italy (27 articles), 

Switzerland (18 articles) and France (13 articles) are the three main contributors. A number of PhD 

Students work in close collaboration with worldwide key industrial players in microelectronics (e.g. 

STMicroelectronics). 

The technical Program Committee selected 111 oral presentations out of 175 proposals, 

corresponding to an overall acceptance rate of 63%. 

The main topics of the 2005 PRIME conference are analog integrated circuits (ICs), RF and 

communication ICs, digital ICs, ICs applied to biomedical applications, ADCs, sensors and 

interfaces, CAD tools, FPGAs, Systems on Chip, device modeling, MEMs components, and optical 

devices. 

The Technical Program Committee is formed by 26 internationally recognized experts in the above 

mentioned topics, distributed between the industrial world, the academic world and research centers. 

We would like to thank all the members of this Committee for the hard and competent work in timely 

reviewing the submitted PRIME summaries. 

We would also like to acknowledge the important role played by the technical sponsor IEEE Circuits 

and Systems (CAS) Society for support and the advertisement of this Conference. 

We do hope that the Gala dinner will give you the opportunity to meet each other in a friendly 

atmosphere and that you will enjoy your stay in Switzerland. 

Prof. Michel Declercq Dr. Catherine Dehollain Prof. Franco Maloberti 

General Chair Technical Program Co-Chair Technical Program Co-Chair 

II

Technical Committee 

General Chair: 

Professor Michel Declercq 

Director of the Electronics Lab. and Dean of the School of Engineering at EPFL 

E-mail: michel.declercq@epfl.ch 

Address: EPFL, STI, IMM, LEG, ELB Ecublens, CH-1015 Lausanne, Switzerland. 

Phone : +41 (0)21 693 69 61 ; +41 (0)21 693 39 74 

Fax : +41 (0)21 693 36 40 

Program Chairs: 

Dr. Catherine Dehollain 

Head of the RF ICs Group at the Electronics Lab. of EPFL 

E-mail: catherine.dehollain@epfl.ch 


Phone: +41 (0)21 693 69 71 

Fax : +41 (0)21 693 36 40 

Professor Franco Maloberti 

Microelectronics Chair Professor 

E-mail: franco.maloberti@unipv.it 

University of Pavia, Electronic Department, Via Ferrata 1, 27100 Pavia, Italy 

Phone : (+39) 0382-985-205 

Local Chair: 

Isabelle Buzzi 

E-mail: isabelle.buzzi@epfl.ch 


Phone: +41 (0)21 693 39 75 

Fax : +41 (0)21 693 36 40 

Other Members of the Committee: 

Dr. Thierry Arnaud 

Head of the RF ICs group 

E-mail: thierry.arnaud@st.com 

Address: ST Microelectronics-NV, 39 Chemin du champ des filles, Case Postale 21 

CH-1228 Plan-les-Ouates, Switzerland. 

Phone: +41 (0)22 929 58 84 

Professor Erik Bruun 

E-mail: eb@oersted.dtu.dk 

Address: Technical University of Denmark 

rsted-DTU 

Building 348, DK-2800 Kgs. Lyngby, Denmark 

Phone: (+45) 4525 3906 

John Gerrits 

Staff Engineer 

E-mail: john.gerrits@csem.ch 

Address: CSEM, Advanced Systems Engineering 

Rue Jaquet-Droz 1, CH-2007 Neuchatel, Switzerland 

Phone : +41 (0)32 720 56 52 

Professor Kari Halonen 

E-mail: karih@ecdl.hut.fi 

Address: Helsinki University of Technology 

Electronic Circuits Laboratory, FIN-02015, Finland 

III

Frank Henkel 

Head of the RF ICs group 

E-mail: henkel@imst.de 

Address: IMST GmbH 

Carl-Friedrich-Gauss Strasse 

D-47475 Kamp-Lintfort, Germany 

Phone: +49 (0) 28 42 981 270 

Professor Maher Kayal 

E-mail: maher.kayal@epfl.ch 


Phone : +41 (0)21 693 39 81 

Professor Yususf Leblebici 

Director of the LSM Laboratory 

E-mail: yusuf.leblebici@epfl.ch 

Address: EPFL, STI, IMM, LSM, ELB Ecublens, CH-1015 Lausanne, Switzerland. 

Phone : +41 (0)21 693 69 51 

Dr. Jean-René Lequepeys 

Head of the RF ICs Group at the LETI 

E-mail: LEQUEPEYS@chartreuse.cea.fr 

CEA/Grenoble, Laboratoire d’Electronique et de Technologie de l’Information 

Address : CEA/Grenoble, 17 Rue des Martyrs, 38054 Grenoble Cedex 9, France 

Phone : +33 (0) 438 78 37 49 

Professor Gaelle Lissorgues-Bazin 

Address: School of Engineering ESIEE, Signal and Telecom. Department 

Cite Descartes, BP 99, Boulevard Blaise Pascal no 2 

F-93162 Noisy-Le-Grand, Cedex, France 

Phone : +33 (0) 1 45 92 66 96 

Professor Piero Malcovati 

E-mail: piero.malcovati@unipv.it 

Address: University of Pavia, Electronic Department, Via Ferrata 1, 27100 Pavia, Italy 

Professor F. Xavier Moncunill 

e-mail: moncunill@tsc.upc.es 

Address: Department of Signal Theory and Communications 

Universitat Politcnica de Catalunya 

Mdul D4-208 

Jordi Girona 1-3 

08034 Barcelona, Spain 

Phone: + 34 93 40 17 072 

Dr. Pierre Nicole 

E-mail: pierre.nicole@fr.thalesgroup.com 

Project Leader (Dept. optique, hyperfréquences et microtechnologies) 

Address: THALES systèmes aéroportés, 2 Avenue Gay Lussac 

78851 Elancourt, Cedex, France 

Phone : + 33 (0) 1 34 59 57 98 

Dr. Patrice Senn 

E-mail : patrice.senn@francetelecom.com 

Address: France Telecom/BD/FTR&D/DIH/OCF 

ZIRST - BP 98, 38 243 Meylan Cedex, France 

Phone: (33) (0)4 76 76 41 32 

IV

Professor Gilles Sicard 

E-mail : gilles.sicard@imag.fr 

Address : TIMA-CMP 

46 avenue Felix Viallet, 38031 Grenoble Cedex, France 

Phone: +33 4 76 57 46 15 

Professor Hannu Tenhunen 

Dean of the School of Information Technology 

E-mail: hannu@ele.kth.se 

Address: School of Information Technology 

Royal Institute of Technology (KTH) 

IT-University, IMIT/LECS/ESDlab 

Isafjordsgatan 39 

Box 229, 16440 Kista, Sweden 

Phone: 46-8-7904119 

Professor Bill Redman-White 

E-mails: bill.redman-white@philips.com, wrw@ecs.soton.ac.uk 

University of Southampton, United Kingdom 

Philips Company, United Kingdom 

Professor Gerhard Wachutka 

E-mail: gw@tep.ei.tum.de 

Munich University, Germany 

Dr. Herman Casier 

E-mail: herman_casier@amis.com 

AMI Semiconductor, BELGIUM 

Dr. Didier Belot 

RF Integrated System Design Program Manager 

E-mail: didier.belot@st.com 

Address: ST Microelectronics, Crolles, France 

Phone: 0033 476 92 62 61 

Professor Michael Peter Kennedy 

E-mail: peter.kennedy@ucc.ie 

Address: University College Cork, Department of Microelectronic Engineering 

Butler Building, North Mall, Cork, Ireland 

Phone: +353 21 490 4570 

Professor Willy Sansen 

Head of ESAT-MICAS 

E-mail: willy.sansen@esat.kuleuven.ac.be 

Address: K.U. Leuven, Kast. Arenberg 10, B-3001 Leuven, Belgium 

Phone: +32 16 321 077 

Professor Andrea Baschirotto 

E-mail: andrea.baschirotto@unile.it 

Address: University of Lecce - Dept. of Innovation Engineering, Via per Monteroni, 

73100 Lecce, Italy 

Phone: (+39) 0832 297 213 (Lab 353) 

Professor Mihai-Dan Steriu 

E-mail: dan.steriu@dce.pub.ro 

Address: University "Politehnica" of Bucharest - Faculty of Electronics, Telecommunications and Information 

Technology, 1-3, Bd. luliu Maniu, sector 6, Bucharest, Romania 

Phone: (+40) 21 402 4840 

V

Volume I 

Monday, 25th July 2005 

Morning 

Registration – Building CO, in front of the auditorium CO2 - http://plan.epfl.ch 

All presentations will take place in building CO (CO1 and CO2) 

Auditorium CO2 

DEHOLLAIN Catherine, DECLERCQ Michel 

Electronics Laboratories, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland 

Welcome address 

Overview of the School of Engineering of the Swiss Federal Institute of Technology (EPFL) 

Time Topic Chairperson 

10:30 - 12:00 Analog ICs F. Henkel, IMST GmbH, Germany 

SCANDURRA Graziella 1 , CIOFI Carmine 1 , ZITO Domenico 2 

1 University of Messina, Messina, Italy, 2 University of Pisa, Pisa, Italy 

A New Topology for Transformer Based CMOS Active Inductances 

VOGRIG D. 1 , GEROSA A. 1 , NEVIANI A. 1 ,GRAELL I AMAT A. 2 , MONTORSI G. 2 , 

2 1 

BENEDETTO S. 

1 2 

University of Padova, Padova, Italy, Politecnico di Torino, Torino, Italy 

A 0.35 um CMOS Analog Turbo Decoder for a 40-bit Rate 1/3 UMTS Channel Code 

YAZICIOGLU Refet Firat 1,2 , MERKEN Patrick 1 , VAN HOOF Chris 1,2 

1 IMEC, Leuven, Belgium, 2 K.U.Leuven, Leuven, Belgium 

Effect of Electrode Offset on the CMRR of the Current Balancing Instrumentation Amplifiers 

VASILOPOULOS Athanasios, VITZILAIOS Georgios, THEODORATOS Gerasimos, 

PAPANANOS Yannis, 

National Technical University of Athens (NTUA), Athens, Greece 

A Low-Voltage, Highly Linear, Integrated, Active-RC Filter 


10:30 - 12:00 RF ICs A. Baschirotto, University of Lecce, Italy 

D'AMICO S. 1 . GRASSI T. 1 , RYCKAERT Julien 2 , BASCHIROTTO A. 1 

1 University of Lecce, Lecce, Italy, 2 IMEC, Leuven, Belgium 

A Up to 1GHz Low-Power Continuous-time "3rd-order Filter+Integrator" Chain for Wireless 

Body-Area Network Receivers 

WELLIG Armin, 

STMicroelectronics, Geneva, Switzerland 

Energy-Efficient Baseband Receiver Design in Deep Sub-um Technology 

GHITTORI N. 1 , VIGNA A. 1 , MALCOVATI P. 1 , D'AMICO S. 2 , BASCHIROTTO A. 2 

1 University of Pavia, Pavia, Italy, 2 University of Lecce, Lecce, Italy 

A Low-Voltage, Low-Distortion (1.2V, 29.5 dBm OIP3) Reconfigurable Baseband Block for 

Mobile Applications 

1 VIDOJKOVIC Maja, 1 VAN DER TANG Johan, 2 BALTUS Peter, 1 VAN ROERMUND Arthur 

1 Eindhoven University of Technology, Eindhoven, The Netherlands, 

2 ASL Philips, Eindhoven, The Netherlands 

Adaptive Mixers with a Discretely and a Continuously Ajustable performance space 

VI 

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P 25 

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Volume I 


Afternoon 


13:50 - 15:45 ADCs F. Maloberti, University of Pavia, Italy 

MOVAHEDIAN Hamid, BAKHTIAR Mehrdad Sharif, 

Sharif University of Technology, Tehran, Iran 

A 1.5V 8-Bit Low-Power Self-Calibrating High-Speed Folding ADC 

CATLI Burak 1,2 , BAYAM Fidel 1,2 , CAVUS Bilal Tarik 1 , KEPKEP Asim, ZEKI Ali 1, 

1 Istanbul Technical University, Istanbul, Turkey, 2 ETA-IC Design Center, Istanbul, Turkey 

A 4 GSa/s 7-Bit Two-Way Time-Interleaved Bipolar Track-and-Hold Amplifier Based on a 

Novel Analog Switch 

TALAY Selçuk, DUNDAR Günhan, 

Bogaziçi University, Istanbul, Turkey 

A Sigma-Delta ADC Design Automation Tool 

TESTONI Nicola, CISTERNI Marco, FRANCHI Eleonora, 

University of Bologna, Bologna, Italy 

A Regular Modular Architecture for Pipelined Binary Tree Multipliers Based on a SOG 

Structure 

HANNON Jason, WEGENER Carsten, KENNEDY Michael Peter, 

University College Cork, Cork, Ireland 

Developing an Strategic Error Source Based Design Evaluation for ADC’s 


13:50 - 15:45 Digital ICs A. Baschirotto, University of Lecce, Italy 

WANG Yu, YANG Huazhong, WANG Hui, 

Tsinghua University, Beijing, China 

Signal-path Level Assignment for Dual-Vt Technique 

PETTENGHI Hector, AVEDILLO Maria J., QUINTANA José M., 

Instituto de Microelectrónica de Sevilla, Sevilla, Spain 

Novel Improved RTD-Based Implementation of Multi-Threshold Logic Gates 

BOUQUET Valéry 1,2 , CANET Pierre 1 , LALANDE Frédéric 1 , DEVIN Jean 2 , 

LECONTE Bruno 2 , MARIEMA Nicolas 1 , 

1 IMT Technopole de Château Gombert, Marseille, France. 2 STMicroelectronics, Rousset, France 

Variation of Flash Memory Threshold Voltage Correlated With Applied Voltage Slope in 

Fowler Nordheim Erase Mode 

HATIRNAZ Ilhan, BADEL Stéphane, LEBLEBICI Yusuf 

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland 

Towards a Unified Top-Down Design Flow for Fully Differential Logic Blocks with Improved 

Speed and Noise Immunity 

WEY I-Chyn, CHEN You-Gang, WU Chia-Tsun, WANG Wei, and WU An-Yeu, 

National Taiwan University, Taipei, Taiwan 

A High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for SoC 

Applications 

VII 

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P 56 

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P 63 

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Volume I 


Afternoon 


16:15 – 17:05 ADCs F. Maloberti, University of Pavia, Italy 

GHARBIYA Ahmed, JOHNS David A., 

University of Toronto, Ontario, Canada 

Fully Digital Feedforward Delta-Sigma Modulator 

CALDWELL Trevor C., JOHNS David A., 

University of Toronto, Ontario, Canada 

A High-Speed Technique for Time-Interleaving Continuous-Time Delta-Sigma Modulators 


16:15 – 17:30 Analog ICs C. Dehollain, EPFL, Switzerland 

PIOMBO Davide, ZUNINO Rodolfo, 

University of Genova, Genova, Italy 

Analog Soft Max Circuit with Dynamic Gain Control 

1,2 1 2 2 

CAUCHETEUX Damien , BEIGNE Edith , RENAUDIN Marc , CROCHON Elisabeth , 

1 2 

CEA, Grenoble, France, TIMA Lab., Grenoble France 

Toward Asynchronous and High Data Rates Passive Contactless Systems 

LIU Chengxin, Mc NEILL John, 

Worcester Polytechnic Institute, Worcester, MA, USA 

A Digital-PLL-Based True Random Number Generator 

VIII 

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Volume I 

Tuesday, 26th July 2005 



8:30 - 10:00 RF ICs A. Koukab, EPFL, Switzerland 

TEDESCO Annamaria, BONFANTI Andrea, PANSERI Luigi, LACAITA Andrea 

Politecnico di Milano, Milano, Italy 

A 11-15 GHz CMOS /2 Frequency Divider For Broad-Band I/Q Generation 

NIELSEN Michael, LARSEN Torben, 

Aalborg University, Denmark 

A 4.2 GHz CMOS Quadrature VCO using Injection Locking for WLAN 802.11a 

VON BÜREN George, ELLINGER Frank, JAECKEL Heinz, 

Swiss Federal Institute of Technology (ETHZ), Zürich, Switzerland 

A Very Low Power Consuming 5 GHz CMOS VCO Core with 800 MHz Frequency Tuning 

Range 

LEI Yu, KOUKAB Adil, DECLERCQ Michel, 


Design and Optimization of CMOS Prescaler 


8:30 - 10:00 FPGAs A. Schmid, EPFL, Switzerland 

MEINDL Tassilo, MONIACI Walter, GALLESIO Davide, PASERO Eros 

Politecnico di Torino, Torino, Italy 

Embedded Hardware Architecture for Statistical Rain Forecast 

DENNING Daniel, IRVINE James, DEVLIN Malachy, 

Alba Centre, Livingston, UK 

A High Throughput FPGA Camellia Implementation 

RAMACCIOTTI Tommaso 1 , SERAFINI Luca 1 , FANUCCI Luca 1 , BALDACCI Stefano 2 . 

1 University of Pisa, Pisa, Italy, 2 Kayser Italia Srl, Livorno, Italy 

A Novel Approach Based on Dynamic Reconfiguration for Process Controls with FPGA 

MAN K.L., 

Eindhoven University of Technology, Eindhoven, The Netherlands 

An Overview of SystemC FL 

IX 

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Volume I 




10:30 – 12:00 RF ICs J. Gerrits, CSEM, Switzerland 

DE MATTEIS M., D'AMICO S., BASCHIROTTO A. 

University of Lecce, Lecce, Italy 

A 600mV 1.32mW 75dB-DR 4th-order Baseband Analog Filter for UMTS Receivers 

CURTY Jari-Pascal, JOEHL Norbert, DEHOLLAIN Catherine, DECLERCQ Michel, 


A 2.45GHz Remotely Powered RFID System 

D'AMICO S., CHIRONI V., BASCHIROTTO A. 

University of Lecce, Lecce, Italy 

A 0.13 um CMOS VGA for Multistandard Receivers 

ZITO Domenico, D'ASCOLI Francesco, NERI Bruno, 

University of Pisa, Pisa, Italy 

Fully Integrated RF Front-End for WLAN: a New Step Toward Single-Chip Transceivers 


10:30 – 12:00 FPGAs A. Schmid, EPFL, Switzerland 

MARRAKCHI Zied, MRABET Hayder, MEHREZ Habib, 

Université Paris 6, Paris, France 

Hierarchical FPGA Clustering to Improve Routability 

YANG M. 1 , ALMAINI A.E.A. 1 , WANG L. 2 , WANG P.J. 3 , 

1 Napier University, Scotland, UK, 2 Fudan University, China 

3 Ningbo University, China 

An Evolutionary Approach for Symmetrical Field Programmable Gate Array Placement 

STERPONE Luca, SONZA REORDA Matteo, VIOLANTE Massimo, 


RoRa: A Reliability-oriented Place and Route Algorithm for SRAM-based FPGAs 

GOLOFIT Krzystof, 

Warsaw University of Technology, Warsaw, Poland 

Efficient VLSI Implementation of Multiplication in GF(2") 

X 

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P 147 

P 151

Volume I 


Afternoon 


13:50 - 15:45 MEMs M. Mazza, EPFL, Switzerland 

KRZEMIENIECKI Dariusz 1 , HERMANOWICZ Ewa 2 , 

1 GZT Telekom-Telmor, Gdansk, Poland, 2 Gdansk University of Technology, Gdansk, Poland 

Multidirectional CATV Transformers 

PISANI Marcelo, HIBERT Cyrille, BOUVET Didier, DEHOLLAIN Catherine, 

IONESCU Adrian M., 


Fabrication and Electrical Characterization of High Performance Copper/Polyimide Inductors 

PERRUISSEAU-CARRIER Julien, FRITSCHI Raphaël, SKRIVERVIK Anja, 


Design of Enhanced Multi-Bit Distributed MEMS Variable True-Time Delay Lines 

SCUDERI A. 1 , BIONDI T. 2 , RAGONESE E. 1 , PALMISANO G. 1 , 

1 University of Catania, Catania, Italy, 2 STMicroelectronics, Catania, Italy 

Inductance Calculation of Thick-Metal Inductors 

VILLARROYA Maria 1 , VERD Jaume 1 , TEVA Jordi 1 , ABADAL, G. 1 PEREZ Francesc 2 , 

ESTEVE Jaume 2 , BARNIOL Nùria 1 , 

1 2 

Universitat Autònoma de Barcelona, Barcelona, Spain, Instituto de Microelectrónica de Barcelona, 

Bellaterra, Spain 

Cantilever Based MEMS for Multiple Mass Sensing 


13:50 - 15:45 CAD Tools F. Henkel, IMST GmBh, Germany 

HEINZL R., SPEVAK M., SCHWAHA P., GRASSER T. 

Technical University Vienna, Vienna, Austria 

A Novel Technique for Coupling Three Dimensional Mesh Adaptation with an a Posteriori 

Error Estimator 

LATTUADA Mauro, POSEGA Renzo, MATTAVELLI Marco, MLYNEK Daniel, 


Efficient Error Correction Solutions for OFDM-Based Wireless Video 

MELANI Massimiliano, FANUCCI Luca, SAPONARA Sergio, 


Algorithmic/Architectural Design for H.264/MPEG-4 AVC Low-Power Video CODEC 

MORGENTSTERN H. 1 , GROOS G. 2 , KOEHNE H. 1 , STECHER M. 3 , JOHN W. 1 , 

REICHEL H. 1 , 

1 Frauenhofer IZM, Berlin, Germany, 2 Universität der Bundeswehr, Neubiberg, Germany 

3 Infineon Technologies, Munich, Germany 

Algorithm for the Automatic Verification of Complex Mixed-Signal ICs regarding ESD-Stress 

RUIZ-DE-CLAVIJO P., BELLIDO M.J., JUAN J., 

Universidad de Sevilla, Sevilla, Spain 

Halotis-High Accurate Logic Timing Simulator 

XI 

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Volume I 


Afternoon 


16:15 – 17:45 MEMs M. Mazza, EPFL, Switzerland 

DELMONTE Nicola 1 ,WATTS Bernard Enrico 2 , ROSA Lorenzo 1 , CHIERBOLI Giovanni 1 , 

COVA Paolo 1 , MENOZZI Roberto 1 , 

1 University of Parma, Parma, Italy, 2 Instituto IMEM/CNR, Parma, Italy 

Test Pattern for Microwave Dielectric Properties of SrBi2TA2O9 

DESPESSE Ghislain 1 , JAGER Thomas 1 , CHAILLOUT Jean-Jacques 1 , LEGER Jean Michel 1 , 

BASROUR Skandar 2 , 

1 CEA-LETI, Grenoble, France, 2 TIMA, Grenoble, France 

Design and Fabrication of a New System for Vibration Energy Harvesting 

LEO Elisabetta, BRAGHIN Francesco, RESTA Ferruccio, 

Politecnico di Milano, Milano, Italy 

Nonlinar Vibrations of a MEMS Translational Device 

SAHA Shimul Chandra, SINGH Tajeshwar, SOETHER Trond, 

Norwegian University of Science and Technology, Trondheim, Norway 

Design and Simulation of RF MEMS Switches for High Switching Speed and Moderate Voltage 

Operation 


16:15 – 17:25 Sensors and 

Interfaces 

P.A. Besse, EPFL, Switzerland 

MAJEED Bivragh, VAN SINTE Jean-Baptiste, INDRAJIT Paul, BARTON John, 

C O’MATHUNA Sean, DELANEY Kieran 

Tyndall National Institute and Cork Institute of Technology, Cork, Ireland 

Material Characterisation and Process Development for Miniaturised Wireless Sensor Network 

Module 

ZORLU O., KEIJIK P., VINCENT F., POPOVIC, R.S., 


A Novel Planar Magnetic Sensor Based on Orthogonal Fluxgate Principle. 

CHAEHOI A., LATORRE L., .MAILLY F., NOUET P. 

Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, France 

A Monolithic CMOS 3-Axis Accelerometer Combining Piezoresistive and Heat Transfer Effects 

GALA DINNER AT HOTEL BEAU-RIVAGE 

OUCHY – LAUSANNE FROM 7.30 PM 

XII 

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Volume II 

Wednesday, 27th July 2005 



8:30 - 10:00 RF ICs C. Dehollain, EPFL, Switzerland 

MAK Pui-In, U Seng-Pan 1 , MARTINS R.P. 2 , 

University of Macau, Macao, China, 1 Also with Chipidea Microelectronics, Macao, China, 2 On 

leave from Instituto Superior Técnico, Lisbon, Portugal 

Multistandard-Compliant Receiver Architecture with Low-Voltage Implementation 

LOPEZ Joan Lluis, TEVA Jordi, TORRES Francesc, ABADAL Gabriel, URANGA Arantxa, 

BARNIOL Nùria, 

Universitat Autònoma de Barcelona, Barcelona, Spain 

Frequency Synthesis Using On-Chip Micromechanical Resonator 

BURG A. HAENE S., PERELS D., LUETHI P., FELBER N., FICHTNER W., 


Receiver Design for Multi-Antenna Wireless Communications 

SCUDERI A. 1,2 , CARRARA F. 1 , PALMISANO G. 1 , 

1 University of Catania, Catania, Italy, 2 STMicroelectronics, Catania, Italy 

A Soft-Slope Output Power Control Circuit for RF Power Amplifiers 


8:30 - 10:00 CAD Tools A. Koukab, EPFL, Switzerland 

MENDEZ Miguel, MATEO Diego, RUBIO Antonio, GONZALEZ José Luis, 

Universitat Politècnica de Catalunya, Barcelona, Spain 

Characterization of the Substrate Noise Spectrum for Mixed-Signal ICs 

WANG Q., VAN DER MEIJS, 

Delft University of Technology, Delft, The Netherlands 

An Efficient Method for Substrate Impedance Extraction 

KARAMPATZAKIS D.P., EVMORFOPOULOS N.E., STAMOULIS G.I., 

University of Thessaly, Volos, Greece 

A Statistically-Based Engine for P/G Network Optimization 

COULIBALY L.M., KADIM H.J., 

Liverpool JM University, Liverpool, UK 

Electromagnetic Signatures: A Virtual Test and Verification Tool for SoC Signal Integrity 

XIII 

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Volume II 




10:30 – 12:00 RF ICs M.P. Kennedy, University College Cork, Ireland 

TASSIN Claire 1,2 , GARCIA Patrice 1 , BEGUERET Jean-Baptiste 2 , TOUPE Romaric 2 , DEVAL 

Yann 2 , BELOT Didier 1 

1 STMicroelectronics, Crolles, France, 2 Bordeaux University, Talence, France 

A Mixed-Signal Cartesian Feedback Linearization System for a Zero-IF WCDMA Transmitter 

Handset IC 

COLLARD BOVY Anne 1 , COURMONTAGNE Philippe 2 , 

1 STMicroelectronics, Rousset, France, 2 L2MP CNRS UMR, Marseille, France 

An All-Digital Signal Receiver for Transmission/Reception of Radio-Frequency Architectures 

HOLLIS Timothy, COMER David, COMER Donald, 

Brigham Young University, Provo, Utah, USA 

Reduction of Duty Cycle Distortion Through Band-Pass Filtering 

ITALIA Alessandro, CARRARA Francesco, RAGONESE Egidio, PALMISANO Giuseppe, 

University of Catania, Catania, Italy 

The Transformer Characteristic Resistance and its Application to the Design of RF Circuits 

P 255 

P 259 

P 263 

P 267 


10:30 – 12:00 Device Modeling F.X. Moncunill, Universitat Politècnica de Catalunya, 

Spain 

CANEPARI Anna 1,2 , BERTRAND Guillaume 1 , MINONDO Michel 1 , JOURDAN Nathalie 1 , 

CHANTE Jean-Pierre 2, 

1 STMicroelectronics, Crolles, France, 2 CEGELY, INSA de Lyon, Villeurbanne, France 

DC/HF Circuit Model for LDMOS Including Self-Heating and Quasi-Saturation 

BECKRICH Hélène 1,2 , SCHWARTZMANN Thierry 1 , CELI Didier 1 , ZIMMER Thomas 2 , 

1 STMicroelectronics, Crolles, France, 2 Université Bordeaux I, Talence, France 

A Spice Model for Predicting Static Thermal Coupling between Bipolar Transistors 

SHEIKHOLESLAMI A. 1 , HOLZER S. 3 , HEITZINGER C. 1 , LEICHT M. 2 , HAEBERLEN O. 2 , 

FUGGER J. 2 , GRASSER T. 3 , SELBERHERR S. 1 , 

1 Technical University Vienna, Vienna, Austria, 2 Infineon Technologies, Villach, Austria, 

3 Christian Doppler Laboratory, Technical University Vienna, Austria 

Inverse Modeling of Oxid Deposition Using Measurements of a TEOS CVD Process 

OCKET I. 1 , NAUWELAERS B. 1 , CARCHON G 2 ., DE RAEDT W. 2 , 

1 K.U.Leuven, Leuven, Belgium, 2 IMEC, Leuven, Belgium 

Integration of High-Q Resonators With MCM-D for Millimeter Wave Applications 

XIV 

P 271 

P 275 

P 279 

P 283

Volume II 


Afternoon 


13:50 - 15:45 Sensors and Interfaces P.A. Besse, EPFL, Switzerland 

BRACKE Wouter, MERKEN Patrick, PUERS Robert, VAN HOOF Chris, 

IMEC, Leuven, Belgium, ESAT, K.U.Leuven, Leuven, Belgium 

Ultra Low Power Capacitive Sensor Interface With Smart Energy Management 

FRIEDRICH Nils, BOEHM Markus, 

University of Siegen, Siegen, Germany 

A Locally Autocompensating Image Sensor 

PASTRE Marc, KAYAL Maher, 


A Hall Sensor-Based Current Measurement Microsystem with Continuous Gain Calibration 

SCHNEIDER Verena, 

Institute for Microelectronics Stuttgart (IMS), Stuttgart, Germany 

Fixed-Pattern Correction of HDR Image Sensors 

PANCHERI Lucio 1 , DALLA BETTA Gian-Franco 1 , STOPPA Davide 2 , SCANDIUZZO Mauro 2 , 

VIARANI Luigi 2 , SIMONI Andrea 2 

1 University of Trento, Trento, Italy, 2 ITC-irst, Trento, Italy 

CMOS Distance Sensor Based on Single Photon Avalanche Diode 

P 287 

P 291 

P 295 

P 299 

P 303 


13:50 - 15:45 CAD Tools F.X. Moncunill, Universitat Politècnica de Catalunya, 

Spain 

GJERMUNDNES Øystein, AAS Einar J. 

Department of Electronics and Telecommunications, NTNU, Trondheim, Norway 

Design of a Path Delay Fault Simulator for Evaluation of Abist Generated Stimuli 

MACHADO Felipe, TORROJA Yago, RIESGO Teresa, 

Universidad Politécnica de Madrid, Madrid, Spain 

Exploiting VHDL-RTL Features to Reduce the Complexity of Power Estimation in Combinational 

Circuit 

MARINO C., FORLITI M., ROCCHI A., GIAMBASTIANI A., IOZZI F., DE MARINIS M., 

FANUCCI L., 


Mixed Signal Behavioral Verification using VHDL-AMS 

TELESCU M., BREHONNET P., TANGUY N., VILBE P., CALVEZ L.C., 

LEST UMR CNRS, Brest, France 

Laguerre-Gram Reduced Order Modeling Applied to VLSI Circuit Interconnects 

BALZANI Marianna, REATTI Alberto, 

University of Florence, Florence, Italy 

Neural Network Based Model of a PV Array for the optimum performance of PV system 

XV 

P 307 

P 311 

P 315 

P 319 

P 323

Volume II 


Afternoon 


16:15 – 17:45 Optical Devices and 

Applications 

P. Dainesi, EPFL, Switzerland 

GENSOLEN Fabrice 1,2 , CATHEBRAS Guy 2 , MARTIN Lionel 1 , ROBERT Michel 2 , 

1 2 

STMicroelectronics, Rousset, France, Université de Montpellier II, CNRS, Montpellier, 

France 

Focal Plane Integration of Image Texture Coding for Pixel Correspondence 

UPENDRANATH Vanam 1 , GOTTARDI Massimo 2 , ZORAT Alessandro 3 , 

1 2 3 

Digital Systems, CEERI Pilani, India, ITC-irst, Trento, Italy, University of Trento, Trento, 

Italy 

A High-Speed and High-Resolution CMOS Optical Position Sensitive Device 

BEER Stephan, SEITZ Peter, 

Swiss Center for Electronics and Microtechnology (CSEM), Zürich, Switzerland 

Real-Time Tomographic Imaging Without X-Rays: a Smart Pixel Array with Massively Parallel 

Signal Processing for Real-Time Optical Coherence Tomography Performing Close to the Physical 

Limits 

GAILLARD Arc'hanmael 1 , MOHAMED-BRAHIM Tayeb 1 , ROGEL Régis 1 , CRAND Samuel 1 , 

PRAT Christophe 2 , LEROY Philippe 2 , 

1 Université de Rennes I, Rennes, France, 2 THOMSON R&D FRANCE, Cesson-Sévigné, France 

Development of Microcrystalline Silicon Active Matrix for OLED Displays 


16:15 – 17:25 Sensors and 

Interfaces 

F. Maloberti, University of Pavia, Italy 

BIROL Hansu, MAEDER Thomas, BOERS Marc, JACQ Caroline, CORRADINI Giancarlo, RYSER 

Peter, 


Millinewton Force Sensor Based on Low Temperature Co-Fired Ceramic (LTCC) Technology 

PACZESNY Daniel 1 , WEREMCZUK Jersy 1 , JACHOWICZ Ryszard S. 1 , RAPIEDJKO Piotr 2 , 

1 2 

Warsaw University of Technology, Warsaw, Poland, Military Medical Institute, Warsaw, 

Poland 

Construction of Fast Dew Point Hygrometer With Integrated Semiconductor Detector for Medical 

Applications 

GOMRI Sami, SEGUIN Jean-Luc, AGUIR Khalifa, 

L2MP, Université Aix-Marseille III, Marseille, France 

Gas Sensor Selectivity Enhancement by Noise Spectroscopy: a Mode of Adsorption-Desorption 

Noise 

XVI 

P 327 

P 331 

P 335 

P 339 

P 343 

P 347 

P 351

Volume II 

Thursday, 28 th July 2005 



8:30 - 10:00 Analog ICs F. Maloberti, University of Pavia, Italy 

BADEL Stéphane, HARTINAZ Ilhan, LEBLEBICI Yusuf, 


Semi-Automated Design of a MOS Current-Mode Logic Standard Cell Library from 

Generic Components 

TOPRAK Zeynep, LEBLEBICI Yusuf, 


Low-Power Adaptive Bias/Clock Generator Using 0.18 um CMOS Technology for Multi-Core 

Continuous Voltage and Frequency Scaling 

TSAKIRIDIS O., ZERVAS E., STONHAM J., 

Brunel University, Uxbridge, UK 

Voltage Control Chaotic Colpitts Oscillator 

SIVIERO Claudio, STIEVANO I.S., MAIO I.A., 


Behavioral Modeling of IC Output Buffers: A Case Study 


8:30 - 10:00 Digital ICs M.P. Kennedy, University College Cork, Ireland 

GUO Xinyu, SECHEN Carl, 

University of Washington, Seattle, WA, USA 

High Throughput Divider Using Output Prediction Logic 

MILLAN Alejandro, BELLIDO Manuel J., JUAN J., 

Instituto de Microelectrónica de Sevilla, Sevilla, Spain 

Optimization Techniques for Dynamic Behavior of Digital CMOS VLSI Circuits in 

Nanometric Technologies 

IOZZI Francesco, SAPONARA Sergio, MORELLO Alexander J., FANUCCI Luca, 


8051 CPU Core Optimization for Low Power at Register Transfer Level 

DASYGENIS Minas, SOUDRIS, Dimitrios, THANAILAKIS Antonios, 

Democritus University of Thrace, Xanthi, Greece 

A Data and Instruction Memory Performance and Energy Optimization Technique 

XVII 

P 355 

P 359 

P 363 

P 366 

P 370 

P 374 

P 378 

P 382

Volume II 

Thursday, 28th July 2005 



10:30 – 12:00 Analog ICs C. Dehollain, EPFL, Switzerland 

MOEZ Kambiz K., ELMASRY Mohamed I., 

University of Waterloo, Ontario, Canada 

A Novel Inductor-Free CMOS Broadband Amplification Technique 

NIZZA Nicolò, MONDINI Alessio, BRUSCHI Paolo, 


A Current Feedback Adaptive Biasing Method for Class-AB OTA Cells 

SALMEH Roghoyed, MAUNDY Brent, JOHNSTON Ronald, 

University of Calgary, Calgary, Canada 

Effects of Input Matching Inductor on the Minimum Noise Figure of a Low Noise 

Amplifier Designed Based on Noise Optimization Technique 

SIN Sai-Weng, U Seng-Pan 1 , MARTINS R.P. 2 , 

University of Macau, Macao, China, 1 Also with Chipidea Microelectronics, Macao, China, 2 On 

leave for Instituto Superior Técnico, Lisbon, Portugal 

Novel Low-Voltage Circuit Techniques for Fully-Differential Reset and Switched- 

Opamps 


10:30 – 12:00 ICs applied to 

biomedical 

applications 

A. Schmid, EPFL, Switzerland 

MITRA Srinjoy, INDIVERI Giacomo 

University of Zürich and Swiss Federal Institute of Technology (ETHZ), Zürich, Switzerland 

A Low-Power Dual-Threshold Comparator for Neuromorphic Systems 

LICHTSTEINER P., DELBRUCK T., 

Institute of Neuroinformatics, University of Zürich, Zürich, Switzerland 

A 64x64 AER Logarithmic Temporal Derivative Silicon Retina 

VALENTE G. 1 , DE MARTINO F. 2 , BALSI M. 1 , FORMISANO E. 2 , 

1 2 

"La Sapienza" Universita degli Studi di Roma, Italy, University of Maastricht, The 

Netherlands 

Optimizing ICA Using Generic Knowledge of the Sources 

CURRY Richard, JOHNSON Simon, 

University of Durham, Durham, England 

A Versatile Low Power Integrated Circuit for the Recording and Analysis of In- 

Vivo and In-Vitro Neural Signals 

XVIII 

P 386 

P 390 

P 394 

P 398 

P 402 

P 406 

P 410 

P 414

Volume II 

Thursday, 28th July 2005 

Afternoon 


13:50 - 15:00 System on Chip M.P. Kennedy, University College Cork, Ireland 

LAYER Christophe, PFEIDERER Hans-Jörg, 

University of Ulm, Ulm, Germany 

A Scalable Highly Parallel VLSI Architecture Dedicated to Associative Computing Algorithms 

GÜRKAYNAK F.D., FELBER N., KAESLIN H., FICHTNER W. 


Area, Throughput and Security Considerations for AES Crypto-ASICs 

GEELEN Bert 1,2 , BROCKMEYER Erik1, LAFRUIT Gauthier 1 , LAUWEREINS Rudy 1,2 , VERKEST 

Diedrik 1,2,3 

1 2 3 

IMEC, Leuven, Belgium, K.U.Leuven, Leuven, Belgium, Vrije Universiteit, Brussel, 

Belgium 

Exploration of System-Level Trade-Offs for Application Mapping in Multi-Processor System-on- 

Chips. 


13:50 - 15:00 CAD Tools C. Dehollain, EPFL, Switzerland 

KUJANPÄÄ Tuomo, ROOS Janne, HONKALA Mikko, 

Helsinki University of Technology, Hut, Finland 

Experimental Comparison of Optimization Methods in ANN Training 

MALATESTA Alessandro 1 , CARDARILLI Gian Carlo 1 , RE Marco 1 , ARNONE Luigi 2 , BOCCHIO 

Sara 2 , 

1 University of Rome “Tor Vergata”, Rome, Italy, 2 STMicroelectronics, Agrate Brianza, Italy 

Development and Validation of Hardware Architectures for Real-Time High-Performance Speech 

Recognition Systems 

NDIP Ivan 1,2 , JOHN Werner 1 , REICHL Herbert 1 , THIEDE Andreas 2 , 

1 Frauenhofer IZM, Berlin, Germany, 2 University of Paderborn, Paderborn, Germany 

A Novel Approach for RF/Microwave Modeling and Optimization of BGA Packages 

15:10-15:20 Auditorium CO2 

DEHOLLAIN Catherine 

Electronics Laboratories, Swiss Federal Institute of Technology (EPFL), Lausanne, 

Switzerland 

Closing Session 

XIX 

P 418 

P 422 

P 426 

P 430 

P 434 

P 437

AUTHOR INDEX 

AAS Einar J. P 307 COMER David P 263 

ABADAL Gabriel P 171, 227 COMER Donald P 263 

AGUIR Khalifa P 351 CORRADINI Giancarlo P 343 

ALMAINI A.E.A. P 143 COULIBALY L.M. P 251 

ARNONE Luigi P 434 COURMONTAGNE Philippe P 259 

AVEDILLO Maria J. P 56 COVA Paolo P 195 

BADEL Stéphane P 63, 355 CRAND Samuel P 339 

BAKHTIAR Mehrdad Sharif P 33 CROCHON Elisabeth P 83 

BALDACCI Stefano P 115 CURRY Richard P 414 

BALSI M. P 410 CURTY Jari-Pascal P 127 

BALTUS Peter P 29 DALLA BETTA Gian-Franco P 303 

BALZANI Marianna P 323 D'AMICO S P 17, 25, 131 

BARNIOL Nùria P 171, 227 D'ASCOLI Francesco P 135 

BARTON John P 211 DASYGENIS Minas P 382 

BASCHIROTTO A. P 17, 25, 123, 131 DE MARINIS M. P 315 

BASROUR Skandar P 199 DE MARTINO F. P 410 

BAYAM Fidel P 37 DE MATTEIS M. P 123 

BECKRICH Hélène P 275 DE RAEDT W. P 283 

BEER Stephan P 335 DECLERCQ Michel P 103, 127 

BEGUERET Jean-Baptiste P 255 DEHOLLAIN Catherine P 127, 159 

BEIGNE Edith P 83 DELANEY Kieran P 211 

BELLIDO M.J. P 191, 374 DELBRUCK T. P 406 

BELOT Didier P 255 DELMONTE Nicola P 195 

BENEDETTO S. P 5 DENNING Daniel P 111 

BERTRAND Guillaume P 271 DESPESSE Ghislain P 199 

BIONDI T. P 167 DEVAL Yann P 255 

BIROL Hansu P 343 DEVIN Jean P 60 

BOCCHIO Sara P 434 DEVLIN Malachy P 111 

BOEHM Markus P 291 DUNDAR Günhan P 40 

BOERS Marc P 343 ELLINGER Frank P 99 

BONFANTI Andrea P 91 ELMASRY Mohamed I. P 386 

BOUQUET Valéry P 60 ESTEVE Jaume P 171 

BOUVET Didier P 159 EVMORFOPOULOS N.E. P 247 

BRACKE Wouter P 287 FANUCCI L. P 115, 183, 315, 378 

BRAGHIN Francesco P 203 FELBER N. P 231, 422 

BREHONNET P. P 319 FICHTNER W. P 231, 422 

BROCKMEYER Erik P 426 FORLITI M. P 315 

BRUSCHI Paolo P 390 FORMISANO E. P 410 

BURG A. P 231 FRANCHI Eleonora P 44 

C O’MATHUNA Sean P 211 FRIEDRICH Nils P 291 

CALDWELL Trevor C. P 75 FRITSCHI Raphaël P 163 

CALVEZ L.C. P 319 FUGGER J. P 279 

CANEPARI Anna P 271 GAILLARD Arc'hanmael P 339 

CANET Pierre P 60 GALLESIO Davide P 107 

CARCHON G. P 283 GARCIA Patrice P 255 

CARDARILLI Gian Carlo P 434 GEELEN Bert P 426 

CARRARA Francesco P 235, 267 GENSOLEN Fabrice P 327 

CATHEBRAS Guy P 327 GEROSA A. P 5 

CATLI Burak P 37 GHARBIYA Ahmed P 71 

CAUCHETEUX Damien P 83 GHITTORI N. P 25 

CAVUS Bilal Tarik P 37 GIAMBASTIANI A. P 315 

CELI Didier P 275 GJERMUNDNES Øystein P 307 

CHAEHOI A. P 219 GOLOFIT Krzystof P 151 

CHAILLOUT Jean-Jacques P 199 GOMRI Sami P 351 

CHANTE Jean-Pierre P 271 GONZALEZ José Luis P 239 

CHEN You-Gang P 67 GOTTARDI Massimo P 331 

CHIERBOLI Giovanni P 195 GRAELL I AMAT A. P 5 

CHIRONI V. P 131 GRASSER T. P 175, 279 

CIOFI Carmine P 1 GRASSI T. P 17 

CISTERNI Marco P 44 GROOS G. P 187 

COLLARD BOVY Anne P 259 GUO Xinyu P 370 

XX

GÜRKAYNAK F.D. P 422 MAK Pui-In P 223 

HAEBERLEN O. P 279 MALATESTA Alessandro P 434 

HAENE S. P 231 MALCOVATI P. P 25 

HANNON Jason P 48 MAN K.L. P 119 

HATIRNAZ Ilhan P 63, 355 MARIEMA Nicolas P 60 

HEINZL R. P 175 MARINO C. P 315 

HEITZINGER C. P 279 MARRAKCHI Zied P 139 

HERMANOWICZ Ewa P 155 MARTIN Lionel P 327 

HIBERT Cyrille P 159 MARTINS R.P. P 223, 398 

HOLLIS Timothy P 263 MATEO Diego P 239 

HOLZER S. P 279 MATTAVELLI Marco P 179 

HONKALA Mikko P 430 MAUNDY Brent P 394 

INDIVERI Giacomo P 402 Mc NEILL John P 87 

INDRAJIT Paul P 211 MEHREZ Habib P 139 

IONESCU Adrian M. P 159 MEINDL Tassilo P 107 

IOZZI Francesco P 315, 378 MELANI Massimiliano P 183 

IRVINE James P 111 MENDEZ Miguel P 239 

ITALIA Alessandro P 267 MENOZZI Roberto P 195 

JACHOWICZ Ryszard S. P 347 MERKEN Patrick P 9, 287 

JACQ Caroline P 343 MILLAN Alejandro P 374 

JAECKEL Heinz P 99 MINONDO Michel P 271 

JAGER Thomas P 199 MITRA Srinjoy P 402 

JOEHL Norbert P 127 MLYNEK Daniel P 179 

JOHN Werner P 187, 437 MOEZ Kambiz K. P 386 

JOHNS David A. P 71, 75 MOHAMED-BRAHIM Tayeb P 339 

JOHNSON Simon P 414 MONDINI Alessio P 390 

JOHNSTON Ronald P 394 MONIACI Walter P 107 

JOURDAN Nathalie P 271 MONTORSI G. P 5 

JUAN J. P 191, 374 MORELLO Alexander J. P 378 

KADIM H.J. P 251 MORGENTSTERN H. P 187 

KAESLIN H. P 422 MOVAHEDIAN Hamid P 33 

KARAMPATZAKIS D.P. P 247 MRABET Hayder P 139 

KAYAL Maher P 295 NAUWELAERS B. P 283 

KEIJIK P. P 215 NDIP Ivan P 437 

KENNEDY Michael Peter P 48 NERI Bruno, P 135 

KEPKEP Asim P 37 NEVIANI A. P 5 

KOEHNE H. P 187 NIELSEN Michael P 95 

KOUKAB Adil P 103 NIZZA Nicolò P 390 

KRZEMIENIECKI Dariusz P 155 NOUET P. P 219 

KUJANPÄÄ Tuomo P 430 OCKET I. 

LACAITA Andrea P 91 PACZESNY Daniel P 347 

LAFRUIT Gauthier P 426 PALMISANO Giuseppe P 167, 235, 267 

LALANDE Frédéric P 60 PANCHERI Lucio P 303 

LARSEN Torben P 95 PANSERI Luigi P 91 

LATORRE L. P 219 PAPANANOS Yannis P 13 

LATTUADA M. P 179 PASERO Eros P 107 

LAUWEREINS Rudy P 426 PASTRE Marc P 295 

LAYER Christophe P 418 PERELS D. P 231 

LEBLEBICI Yusuf P 63, 355, 359 PEREZ Francesc P 171 

LECONTE Bruno P 60 PERRUISSEAU-CARRIER J. P 163 

LEGER Jean Michel P 199 PETTENGHI Hector P 56 

LEI Yu P 103 PFEIDERER Hans-Jörg P 418 

LEICHT M. P 279 PIOMBO Davide P 79 

LEO Elisabetta P 203 PISANI Marcelo P 159 

LEROY Philippe P 339 POPOVIC, R.S. P 215 

LICHTSTEINER P. P 406 POSEGA Renzo P 179 

LIU Chengxin P 87 PRAT Christophe P 339 

LOPEZ Joan Lluis P 227 PUERS Robert P 287 

LUETHI P. P 231 QUINTANA José M. P 56 

MACHADO Felipe P 311 RAGONESE Egidio P 167, 267 

MAEDER Thomas P 343 RAMACCIOTTI Tommaso P 115 

MAILLY F. P 219 RAPIEDJKO Piotr P 347 

MAIO I.A. P 366 RE Marco P 434 

MAJEED Bivragh P 211 REATTI Alberto P 323 

XXI 

P 283

REICHL Herbert P 187, 437 TOPRAK Zeynep P 359 

RENAUDIN Marc P 83 TORRES Francesc P 227 

RESTA Ferruccio P 203 TORROJA Yago P 311 

RIESGO Teresa P 311 TOUPE Romaric P 255 

ROBERT Michel P 327 TSAKIRIDIS O. P 363 

ROCCHI A. P 315 U Seng-Pan P 223, 398 

ROGEL Régis P 339 UPENDRANATH Vanam P 331 

ROOS Janne P 430 URANGA Arantxa P 227 

ROSA Lorenzo P 195 VALENTE G. P 410 

RUBIO Antonio P 239 VAN DER MEIJS P 243 

RUIZ-DE-CLAVIJO P. P 191 VAN DER TANG Johan P 29 

RYCKAERT Julien P 17 VAN HOOF Chris P 9, 287 

RYSER Peter P 343 VAN ROERMUND Arthur P 29 

SAHA Shimul Chandra P 207 VAN SINTE Jean-Baptiste P 211 

SALMEH Roghoyed P 394 VASILOPOULOS Athanasios P 13 

SAPONARA Sergio P 183, 378 VERD Jaume P 171 

SCANDIUZZO Mauro P 303 VERKEST Diedrik P 426 

SCANDURRA Graziella P 1 VIARANI Luigi P 303 

SCHNEIDER Verena P 299 VIDOJKOVIC Maja P 29 

SCHWAHA P. P 175 VIGNA A. P 25 

SCHWARTZMANN Thierry P 275 VILBE P. P 319 

SCUDERI A. P 167, 235 VILLARROYA Maria P 171 

SECHEN Carl P 370 VINCENT F. P 215 

SEGUIN Jean-Luc P 351 VIOLANTE Massimo P 147 

SEITZ Peter P 335 VITZILAIOS Georgios P 13 

SELBERHERR S. P 279 VOGRIG D. . 

P 5 

SERAFINI Luca P 115 VON BÜREN George P 99 

SHEIKHOLESLAMI A. 

P 279 WANG Hui P 52 

SIMONI Andrea P 303 WANG L. P 143 

SIN Sai-Weng P 398 WANG P.J. P 143 

SINGH Tajeshwar P 207 WANG Q. P 243 

SIVIERO Claudio P 366 WANG Wei P 67 

SKRIVERVIK Anja P 163 WANG Yu P 52 

SOETHER Trond, P 207 WATTS Bernard Enrico P 195 

SONZA REORDA Matteo P 147 WEGENER Carsten P 48 

SOUDRIS, Dimitrios P 382 WELLIG Armin P 21 

SPEVAK M. P 175 WEREMCZUK Jersy P 347 

STAMOULIS G.I. P 247 WEY I-Chyn P 67 

STECHER M. P 187 WU An-Yeu P 67 

STERPONE Luca P 147 WU Chia Tsu P 67 

STIEVANO I.S. P 366 YANG Huazhong P 52 

STONHAM J. P 363 YANG M. 

P 143 

STOPPA Davide P 303 YAZICIOGLU Refet Firat P 9 

TALAY Selçuk P 40 ZEKI Ali P 37 

TANGUY N. P 319 ZERVAS E. P 363 

TASSIN Claire P 255 ZIMMER Thomas P 275 

TEDESCO Annamaria P 91 ZITO Domenico P 1, 135 

TELESCU M. P 319 ZORAT Alessandro P 331 

TESTONI Nicola P 44 ZORLU O. P 215 

TEVA Jordi P 171, 227 ZUNINO Rodolfo P 79 

THANAILAKIS Antonios P 382 

THEODORATOS Gerasimos P 13 

THIEDE Andreas P 437 

XXII

0-7803-9345-7/05/$20.00©2005 IEEE. 

A NEW TOPOLOGY FOR TRANSFORMER 

BASED CMOS ACTIVE INDUCTANCES 

Graziella Scandurra 1 , Carmine Ciofi 1 , Domenico Zito 2 

1 Dipartimento di Fisica della Materia e TFA, University of Messina, 

Salita Sperone 31, I-98166 Messina, Italy. 

2 Dipartimento di Ingegneria dell’Informazione, University of Pisa, 

Via Caruso, I-56122 Pisa, Italy. 

E-mail: gscandurra@ingegneria.unime.it 

ABSTRACT 

The possibility of realizing the analog block of an RF 

front end in CMOS technology is quite attractive, since it 

would lead to the ability of implementing both the digital 

and the analog sections onto a single chip. The 

availability of high quality factor (Q) inductors in CMOS 

technologies is mandatory in order to achieve this goal. 

This in not an easy task and it is for this reason that 

several researchers have started to explore the possibility 

of employing active circuits as part of the inductor itself, 

in order to compensate for the passive inductor’s losses. 

In this paper, we propose a new topology for the design of 

integrated transformer based high quality active inductors. 

As an example, we have designed an active inductor 

circuit based on a 0.35 µm CMOS technology and 

capable of behaving as a pure inductance above 2.4 GHz. 

1. INTRODUCTION 

Integrated passive inductors, especially in the case of 

standard CMOS processes, have typical values of Q that 

are too low for implementing several fundamental RF 

functions (for example highly selective filters)[1]. This 

fact represents today one of the most serious obstacles 

toward the realization of fully integrated CMOS front 

ends. Although the quality factor can be improved by 

resorting to special fabrication steps, the additional 

processing cost and complication make such an approach 

quite unsatisfactory. It is for this reason that there is a 

strong interest in the possibility of realizing high quality 

inductances by employing active circuits. 

A few topologies of active inductors have been proposed 

in the literature, which can be divided into three main 

categories: a first one in which no actual inductance is 

used but an inductive effect is obtained exploiting the 

impedance transformation capabilities of circuit such as 

the “gyrator” [2], a second one in which a bi-pole with a 

negative resistance behavior is put in series to the inductor 

in order to compensate for the losses and increase the 

resulting quality factor Q[3], and a third one which 

exploits the magnetic coupling between the coils of a 

transformer and the current amplification introduced by an 

the active device as in [4] or as in the case of the Boot- 

Strapped Inductor (BSI) technique[5], which has found its 

1 

applications only in bipolar technology[6-8]. As far as the 

first approach is concerned, using no actual inductors do 

result in a smaller occupied area with respect to other 

solutions. However, inductorless circuits introduce a 

relatively high level of noise that makes them useless for 

the most demanding applications [6]. Also the second 

approach, the “negative resistance” technique, has several 

drawbacks: it causes a significant increase of the noise 

figure, it suffers from a strong dependence on the 

temperature and causes the potential instability of the 

circuit. It is for these reasons that starting from the 

problem of the application of the BSI technique to the case 

of CMOS technology, we developed a new topology that 

significantly simplifies the realization of high Q 

equivalent inductances while possibly retaining the 

advantages connected to the use of actual inductances, that 

is a low level of noise . 

2. CMOS BOOT STRAPPED 

INDUCTOR TOPOLOGY 

The circuit in Fig. 1 can be considered as the most obvious 

implementation of the BSI technique, described in [5], to 

the case of CMOS technology. 

1 

2 

M 

V DD 

Z V 

L 2 

L 1 

R 2 

R 1 

R R 

L R 

V B 

Q 2 

V DD 

Figure 1.A possible implementation of a CMOS 

BSI. 

Q 1


1 

2 

R 1 

i L1 

v L1 

L 1 

L R 

R R 

C GS 

V GS 

g m V GS 

Figure 2. Simplified small signal equivalent 

circuit for the CMOS BSI in Fig. 1. 

The circuit exploits the magnetic coupling between two 

spiral inductors, L 1 and L 2, that are represented in series 

with their respective loss resistances, R 1 and R 2. The 

inductor L R, with its loss resistance R R, acts as 

compensation network together with the equivalent input 

capacitance C GS of Q 1. Note that at the frequency at which 

L R and C GS resonate, the current I 1 which flows trough L 1 

results in phase with the gate to source voltage of Q1. In 

this case, assuming that the equivalent transconductance 

gain (g m) of the cascade stage is real, then the current I 1 is 

in phase with the current I 2 which flows in the secondary 

spiral (L 2). 

As can be easily calculated from the circuit in fig.2, the 

impedance seen between the nodes 1 and 2, i.e. the input 

impedance of the CMOS BSI, results: 

R 2 

v L2 

( jω 

) = R + jωL 

+ Z ( 1+ 

j Mg ) 

Zin 1 1 P ω m (1) 

where the impedance Z P is defined as follows: 

Z 

P 

() s ( R + sL ) 

GS 

L 2 

i L2 

1 

= R R || 

(2) 

sC 

Writing explicitly the real and imaginary parts of Z in we 

get: 

⎧ R 

⎨ 

⎩X 

in 

( jω) 

= R + RP 

( jω) 

− ωMg 

m X P ( jω) 

( jω) 

= ωL 

+ ωMg 

R ( jω) 

+ X ( jω) 


1 (3) 

1 

In order to obtain a purely inductive behaviour for Z in at a 

given frequency, we should be able to simultaneously 

obtain a null real part R in and an inductive (positive) 

imaginary part X in for Z in. It can be noted that below the 

resonance frequency of Z P (that is quite close to the 

frequency ω 0R=(L RC R) -1/2 ), the reactance X P is certainly 

positive. Therefore, as it is clear from Eq. (3), below the 

resonance frequency of Z P it is possible to obtain, at a 

given angular frequency ω D, very small values (even 0) for 

the real part of the equivalent impedance, provided that we 

use proper values for g m and M. However, in order not to 

end up with a negative real part for the equivalent 

m 

P 

P 

2 

impedance for frequencies above ω D, also the condition 

that the resistance assumes the minimum value for ω=ω D 

must be satisfied. In conclusion, in order to obtain a purely 

inductive behaviour for Z in in a frequency range around ω D 

(ω D

Z IN 


( Z + R + jωL 

)( 1+ 

jωMg 

) 

P 

1 

1+ 

1 

2 2 2 

M gm 

= (5) 

ω 

Note that in Fig.3 C R plays the role of C GS in fig.2. 

Comparing this expression to the one in (1), it can be 

noted that ZIN, in the case of the new topology, presents a 

higher positive phase contribution, since the term 

(1+jωMgm) does now multiply the sum of ZP with R1 and 

jωL rather than ZP alone, as it happens in the case of the 

previous topology. It must be noted that both the bias 

voltage VR and the value of the capacitance CR (that can 

be implemented by means of a CMOS varicap) can be 

used in order to compensate for process variations and non 

ideal behaviour of the active devices. 

In order to appreciate the advantages of the new approach, 

we have designed an active inductor using both topologies 

in a AMS 0.35µm CMOS technology. Using for the 

parameters the reasonable values LR=2.6 nH with a quality 

factor QR=5, L1=LR=L2, R1=RR, and M=2 nH, we obtained 

that, at a work frequency of 2.4 GHz, a gm of about 

20mA/V is needed in the case of the BSI topology in order 

to have an ideal inductive behaviour, while in the case of 

the new approach we propose, the value of gm of 11 mA/V 

is sufficient. Clearly, a lower value of gm results in a lower 

bias current for the active device and, therefore, in a lower 

power consumption. This is particularly important in the 

case of CMOS devices that have a lower value of the 

transconductance with respect to bipolar devices for the 

same bias current. 

3. RESULTS 

As an example of the performances that can be obtained 

by using the new approach, we have been able to design 

an active inductance of about 6 nH at the work frequency 

of 2.4 GHz by employing an AMS 0.35 µm CMOS 

technology and circuit parameters quite close to the ones 

used for the example in the previous paragraph (the width 

of the transistors was 100 µm). The results of the 

simulations are synthesized in the plots in fig. 4. 

The bias current needed to obtain this performance is less 

than 1 mA for a voltage supply of 3.3 V. 

The condition of ideal inductance can be reached in a 

significantly wide frequency range, from about 2.2 up to 

2.8 GHz, as it is shown in Fig. 5, by setting proper values 

for the two available control voltages. 

This result is quite encouraging as it suggests that, by 

designing a proper control system such as the one used in 

[9], such a wide tuning range can be exploited in order to 

compensate for process and temperature variations. The 

possibility of designing such a control system, together 

with a detailed analysis of the deviation from the ideal 

behaviour as can be expected in the actual realization of 

the circuit, is currently being investigated 

m 

3 

. 

450 

400 

350 

300 

250 

Q 

200 

150 

100 

50 

0 

0 

1 2 3 4 

f(GHz) 

Figure 4. Q factor and inductance of the active 

inductor. 

500 

450 

400 

350 

300 

250 

Q 

200 

150 

100 

50 

0 

1.0 1.5 2.0 2.5 3.0 3.5 

f(GHz) e 

Figure 5. Q factor and inductance of the active inductor. 

4. CONCLUSION 

In this paper the possibility of realizing high quality 

integrated active inductors by employing circuit 

techniques relying on integrated transformers has been 

explored. We started our investigation trying to extend to 

the MOS technology the BSI techniques successfully 

applied to the case of bipolar technology. A new topology 

has been presented that, while considerably reducing the 

requirements in terms of gain, transition frequencies and 

power consumption, provides for two control voltages that 

can be used in order to accurately tune the circuit during 

its actual operation. 

An AMS 0.35 µm CMOS technology has been used to 

demonstrate the validity of the solution we proposed 

which allowed to reach the condition of zero series 

equivalent resistance (that is a virtually infinite Q) for an 

12 

10 

8 

6 

4 

2 

L(nH)

inductance value of about 6 nH at 2.4 GHz by properly 

acting on the above mentioned control voltages. A 

problem which has to be investigated in the future is the 

robustness of the proposed approach versus the process 

tolerances and temperature effects. However, it has been 

already shown in the case of bipolar technology that these 

problems can be solved with an accurate design and some 

supplemental circuitry. For this reason we believe that the 

work we have done so far can be considered quite 

encouraging in view of the possibility of realizing a fully 

integrated CMOS RF front end and that it is worth to 

further investigate on the actual performances that can be 

expected out of the new topology we have developed. 

Moreover, it can be expected that by following the very 

same approach, and provided that up to date technologies 

are employed, almost ideal inductances could be obtained 

at higher frequencies and particularly in the 5 GHz 

frequency range, which may soon become the most 

interesting frequency range requiring the realization of 

high quality, fully integrated CMOS RF front ends for 

single chip, low cost, WLAN interfaces. 


5. REFERENCES 

[1] F. Mernyei, F. Darrer, M. Pardoen, A. Sibrai, 

“Reducing the Substrate Losses for RF Integrated 

Inductors”, IEEE Microwave and Guided Wave 

Letters, Vol.8, pp. 300-301, September 1998 

[2] A. Thanachayanont, “CMOS Transistor-Only Active 

Inductor for IF/RF Applications”, IEEE ICIT ’02, 

Bangkok, Thailand. 

[3] W.B. Kuhn, N.K. Yunduru, A.S. Wyszynski, “Q- 

Enhanced LC Bandpass Filters for Integrated 

Wireless Applications”, Trans. On Microwave 

Theory and Techniques, vol. 46, n.12, Dec.1998, pp. 

2577-2586; 

[4] Y.C. Wu, M.F. Chang, “On-Chip High Q (>3000) 

Transformer-Type Spiral Inductors),” Electronics 

letters, 31 st January 2002, Vol. 38, No.3 

[5] G.D’Angelo, L.Fanucci, A. Monorchio, 

A.Monterastelli, B.Neri,, “High Quality Active 

Inductors”, IEE Electronics Letter, N.20, 30th Sept. 

1999, pp.1727-1728 . 

[6] L. Fanucci, G. D’Angelo, A. Monterastelli, M. 

Paparo, B. Neri , “Fully Integrated Low-Noise 

Amplifier with High Quality Factor L-C Filter for 

1.8GHz Wireless Applications”, ISCAS 2001, the 

2001 IEEE International Symposium on Circuits and 

Systems, vol. 4 , 6-9 May 2001, pp.462 - 465 

[7] D. Zito, L. Fanucci, B. Neri, S. Di Pascoli, G. 

Scandurra , “Single Chip 1.8GHz Band Pass LNA 

with Temperature Self-Compensation ”, SCS 2003, 

International Symposium on Signals, Circuits and 

Systems, vol. 1 , 10-11 July 2003, pp.121 - 124 

[8] L. Fanucci, A. Hopper, B. Neri, D. Zito , “A Novel 

Fully Integrated Antenna Switch for Wireless 

Systems”, ESSDERC '03, 33rd Conference on 

European Solid-State Device Research, 16-18 Sept. 

2003, pp.553 – 556. 

[9] D. Zito, F. De Bernardinis and B. Neri, “Modeling 

and Design of a Tunable high Q LNA for WLAN”, 

4 

Proceedings of IEEE International Conference on 

Signals and Electronic Systems 2004 (ICSES 2004), 

Poznan (PL), 13-15 Sept. 2004, pp.253-256;


A 0.35 μm CMOS ANALOG TURBO DECODER 

FOR A 40-BIT, RATE 1/3, UMTS CHANNEL CODE 

D. Vogrig 1 , A. Gerosa 1 , A. Neviani 1 , A. Graell i Amat 2 , G. Montorsi 2 , S. Benedetto 2 

1 DEI, Università di Padova, Via Gradenigo 6/B, 35131 Padova, Italy 

{daniele.vogrig, gerosa, neviani}@dei.unipd.it 

2 CERCOM, Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy 

{alex.graell, montorsi, benedetto}@polito.it 

ABSTRACT 

In this work we present the design and preliminary testing 

results of the first reported CMOS analog turbo decoder 

for a code of realistic complexity, a parallel concatenated, 

rate 1/3, code defined in the 3GPP standard with 

interleaver size of 40 bits and a codeword size of 132 bits. 

The preliminary test results demonstrated a data rate of 2 

Mbit/s, with a power consumption of 6.6 mW (decoder 

core alone) and an energy per decoded bit and trellis state 

of only 1.36 nJDifferent short range low power wireless 

data transmission systems for ISM (Industrial Scientific 

and Medical) applications are compared with respect to 

their performances (power consumption, distance range, 

architecture well suited to integration, etc). 


After the first successful implementations of analog 

iterative decoders [1, 2] in BiCMOS technology, a full 

CMOS solution for a very simple Hamming (8,4) code 

was proposed in [3]. Shortly after, Gaudet et al. [4] 

realized the first analog turbo decoder, which is a 

significant step ahead with respect to a decoder for a 

single convolutional code, but still far from a real 

application due to the limited interleaver size (16 bit). 

These prototypes have shown an outstanding improvement 

in the power efficiency with respect to their digital 

counterparts, with some error-correcting performance loss. 

Their success fully justifies a further research effort to 

demonstrate that analog decoders for very high 

performance codes are feasible and maintain their 

superiority over the digital implementation. 

In this work, we present the design and preliminary testing 

results of the first reported analog turbo decoder for a 

realistic application [5], a rate 1/3, parallel concatenated 

code defined in the 3GPP standard with interleaver size of 

40 bits. 

2. SYSTEM DESCRIPTION 

2.1 The 3GPP Turbo Code 

The code considered in this work is taken from the 3GPP 

standard and consists of the parallel concatenation of two 

identical Recursive Convolutional Systematic (RCS) 

constituent encoders whose rate is equal to 1/2, and whose 

5 

number of states equals 8. The two constituent encoders 

are connected in parallel through an interleaver that 

operates a permutation on blocks of information bits u k 

before they are fed to the second constituent encoder in 

order to enhance the error-correcting capability of the 

code. The value N B of the block size (or interleaver 

length) plays a fundamental role in setting the 

performance of the code in terms of coding gain. In this 

work, the minimum block size N B = 40 defined in the 

3GPP standard was considered. Two parity bits, c k (1) and 

c k (2) , are generated per every information bit uk. As a 

consequence, the rate of the code is R C = 1/3, so that a 

block of 40 information bits generates 120 code bits plus 

another N T = 12 termination bits. 

We assume that the code bit stream (u k, c k (1) , ck (2) ) 

generated by the encoder is BPSK-modulated, then 

transmitted through an Additive White Gaussian Noise 

(AWGN) channel, and finally demodulated before being 

processed by the analog decoder. Each block of 40 

information bits is thus turned into a channel output frame 

(y k u , yk c1 , yk c2 ) of real NC=132 numbers that is processed 

by the decoder in parallel. 

2.2 The Decoding Algorithm 

A block diagram of our decoder is depicted in Fig. 1. As 

in the iterative decoding technique originally proposed 

Fig.1.Turbo decoder block diagram 

by Berrou et al. [6], two maximum a-posteriori (MAP) 

decoders matched to the two constituent encoders 

calculate and exchange information on bit probabilities of

the information bits pˆ ( u k ) based on the channel output 

observations (i.e. a frame of channel output symbols yk) 

and on the extrinsic information p~ ( u k ) coming from the 

companion MAP decoder. The interleavers (Π) and deinterleavers 

(Π -1 ) permute the channel, the extrinsic and 

the output information so that they match the order of the 

input information bits of the two constituent encoders. The 

equal gate at the output computes the a-posteriori 

probability pˆ ( u k ) from those coming from the two SISO 

decoders. 

In our work, the two identical MAP decoders (since 

identical are the constituent codes) are realized at the 

functional level as Soft-Input Soft-Output (SISO) 

decoders that implement the forward-backward algorithm 

(a.k.a. BCJR algorithm)[7, 8]. Our turbo decoder is based 

on the multiplicative version of the algorithm, that 

basically performs sum-of-product computations on bit 

probabilities, taking a frame of NC = 132 channel 

transition probabilities p(yk|xk=±1) at its input, and 

calculating the a-posteriori probabilities pˆ ( u k ) . 


Fig. 2.SISO decoder block diagram 

A block diagram of a single SISO decoder is shown in 

Fig. 2. It requires six different basic building blocks 

(identified with the letters A through F in Fig. 2) to 

perform all the different sum-of-product computations [8]. 

3. Analog decoder design 

The approach that was followed to implement the 

decoding algorithm outlined in the previous section with 

an analog circuit is basically that proposed by Loeliger et 

al. [9], and adopted in [1] and [3]. It is a current-mode 

technique, where the basic cells computing sum of 

products (sum-product cells) are derived directly from the 

well-known Gilbert multiplier cell. An example of a sumproduct 

cell at transistor-level is shown in Fig.3, reporting 

the CMOS implementation of an E cell. The nMOSFET at 

the bottom generates the normalization current I B. The 

nMOSFET in the middle are operated in the weak 

inversion region and generate every pair of products of the 

two input current vectors (I X0, I X1) and (I Y0, I Y2, I Y2, I Y3). 

In the upper part of the circuit, the currents representing 

the products are summed, by simply shorting the 

corresponding wires, or discarded, connecting the wire to 

V DD, if they are not needed in the sum. The upper 

6 

pMOSFET’s mirror the output currents (IZ0, I Z1) to make 

them available to the cascaded stages. 

Fig.3.CMOS implementation of an E cell 

The transistor network needed to implement a SISO 

decoder is realized by directly connecting the sum-product 

cells according to the diagram reported in Fig. 2. When 

two cells are cascaded, high-output-impedance, saturated 

pMOSFET’s drive the output currents into diodeconnected 

nMOSFET’s. 

The interleaver is realized as a network of independent 

metal paths that permute the SISO1 and the channel 

output currents before they are fed to the SISO2 input 

terminals according to the same permutation scheme 

adopted in the encoder. The deinterleaver is an identical 

network performing the opposite operation on the 

information flowing from SISO2 to SISO1. 

The prototype also includes an I/O interface whose basic 

function is to store a frame of channel output symbols yk on an analog memory, convert them to currents 

representing the channel transition probabilities 

p(yk|xk=±1), perform decisions on the a-posteriori 

probabilites computed by the decoder, and manage the 

output of the decoded bits û k . 

In order to ease the testing phase, the channel output is fed 

to the circuit in a 6-bit digital representation and is 

converted to a differential voltage by a programmable 

gain DAC. A pseudo-differential buffer is placed at the 

DAC output in order to drive the large parasitic 

capacitance of the long interconnections that distribute the 

signal across the analog memory banks. This is organized 

into separate memory banks for the two SISO decoders, 

each including 86 storage elements, 40 for the symbols 

corresponding to the information bits uk, another 40 for 

the parity check symbols, and 6 for the termination. The 

storage elements are realized with a pseudo-differential 

architecture based on sampling capacitors buffered with 

pMOSFET source followers. Transmission gates 

multiplex the output voltage of the two arrays connecting 

them to a pMOSFET differential pair (DP) biased in weak 

inversion, which converts the differential voltage 

proportional to the channel output into a current pair 

proportional to the channel transition probabilities 

p(yk|xk=±1) [9].

Fig.4.Simplified timing diagram of the decoder 

At the decoder output, a bank of 40 current comparators 

make the final decision on the a-posteriori probabilities 

pˆ ( u k ) . 

A simplified timing diagram of the decoder is shown in 

Fig.4. All operations are synchronized on a twononoverlapping-phase 

clock, internally generated from an 

external master clock. Loading an input frame takes 132 

clock cycles. Thanks to the double array of memory 

elements, the loading and decoding operation are 

performed in parallel. The correct sequence of signals to 

drive the S/H’s in the analog memory banks is generated 

using circular buffers. Hard decision on the decoder 

output is taken in the last two clock cycles, and the 40 

resulting hard bits û k are multiplexed on an 8-bit output 

port in the next five clock cycles. In the first two cycles 

the SISO modules are reset to uniform probability, which 

leaves 128 clock cycles for the decoding operation. 

Due to the complexity of the circuit, it was not possible to 

predict the error correcting-performance of the design by 

transistor-level simulations. 

TABLE I 

cell bias current IB, (μA) 1 

tail current nMOSFET W/L, (μm/μm) 4/4 

multiplier nMOSFET W/L, (μm/μm) 5/0.5 

mirror pMOSFET W/L, (μm/μm) 2/2 

S/H capacitance, (fF) 305 

S/H nMOSFET switch W/L, (μm/μm) 2.4/0.3 

S/H buffer bias current, (μA) 2 

DP bias current, (μA) 1 

DP pMOSFET W/L, (μm/μm) 40/0.5 

Transistors in the sum-product cells have been sized for 

6-bit matching accuracy on differential input voltages. 

This figure comes from the precision used in digital 

decoders working with log-likelyhood ratios [10]. This 

choice was verified using a high-abstraction-level 

software description of the analog decoder [5] including a 

simple mismatch model similar to that reported in [11], in 

which the input matching data were derived from 

transistor-level simulations of the sum-product cells. The 

model predicts a performance loss between 0.2 and 0.4 

dB, which was considered acceptable. With transistor 

sizing set by matching requirements, the cell bias current 

(I B in Fig.3) was set in order to guarantee operation 

between weak and moderate inversion of the devices. A 

small number of lengthy transient simulations of the 

decoder core at transistor level were performed to verify 

that the design satisfied the speed requirements. Finally, 


7 

layout solutions to keep under control the maximum 

interconnection length were adopted in order to limit the 

amount of parasitic capacitance at critical nodes. A 

summary of the design main features is listed in Table I. 

4. Experimental results 

The circuit was designed and fabricated in a three-metal, 

double-poly, 0.35 μm CMOS technology. A 

microphotograph of the chip is shown in Fig. 5. 

Fig.5.Chip microphotograph 

The experimental setup to characterize the decoder 

performance consisted of a personal computer emulating 

the encoder and the AWGN channel, connected to an 

logic analyzer/pattern generator. A measurement cycle is 

made up of three steps: (1) generation of the test input 

stream; (2) decoding of the input stream by the device 

under test; (3) decoder output post-processing. In step (1) 

a given number of frames of channel output symbols is 

generated on the PC in a 6-bit digital representation, and 

then transferred to the pattern generator. In step (2), the 

pattern generator feeds the digital input port of the analog 

decoder. As mentioned in section 3, decoding and loading 

a new frame are performed in parallel. The decoded bits 

are captured and stored by the logic analyzer. The two 

synchronization signals that drive the pattern generator 

(READ) and the logic analyzer (OUTPUT_READY) are 

generated internally by the chip based on an external 

master clock. In step (3), the decoded bits are transferred 

to the PC for post-processing. In the nominal testing 

conditions, the master clock frequency is F clock=2 MHz 

(that corresponds to the maximum channel data rate in a 

UMTS system), the power supply is V DD=3.3 V and the 

sum-product cell bias current IB=1 μA. 

The bit and frame error rate (BER, FER) curves vs signalto-noise 

ratio (SNR) measured on a chip samples are 

reported in Fig.6 (solid lines), together with the 

benchmark BER and FER curves (dashed lines). The 

benchmark is a software implementation of a digital 

version of the decoder, and yields the ideal performance 

of the decoding algorithm provided a large enough 

number of iterations are executed. The performance of the 

sample have a loss of about 0.5 dB at a BER of 10 -3 , and 

this loss stays constant until the vicinity of 

BER=10 -6 .More measurement are under way to validate 

this observation.

BER/FER 

1.E+00 

1.E-01 

1.E-02 

1.E-03 

1.E-04 

1.E-05 

FER (ideal) 

BER (ideal) 


FER (measurement) 

0.5dB 

1.E-06 

0 1 2 3 4 5 6 

SNR (dB) 

BER (measurement) 

0.5dB 

Fig.6.BER and FER curves vs SNR measured 

(solid lines) compared to the ideal BER and FER. 

As mentioned in section 3, high-abstraction-level 

simulations including mismatch predict a loss between 0.2 

and 0.4 dB. We have also executed a set of BER 

measurements at a SNR = 2.5 dB with different cell bias 

current I B and clock frequency F clock, whose results are 

reported in Fig.7. As expected, a significant increase of 

BER can be observed at lower I B and higher F clock, due to 

the decrease of the decoder speed with the bias current. 

However, no significant performance gain was obtained 

moving from the nominal testing conditions to lower clock 

frequency and higher bias current. This confirms the 

validity of the design choices and rules out that finite 

decoder speed or operation in moderate inversion 

contribute significantly to the BER performance loss 

observed in Fig.7. 

nominal 

testing 

conditions 

Fig.7.BER measured as function of cell bias 

current I B and clock frequency F clock. 

A deeper experimental investigation is under way to 

understand the actual performance limitations of the 

prototype. A summary of the chip measured performance 

is reported in Table II. The energy per decoded bit and 

trellis state of the decoder core is 2.5 times lower than that 

reported in [4], with also a lower performance loss. 

5. Conclusions 

This work reports the design and testing of the first analog 

turbo decoder for a code of realistic complexity. The 

decoder was realized in a plain CMOS technology and 

was tested at a data rate of 2 Mbit/s, with a power 

8 

TABLE II 

decoder whole 

core chip 

area excl. pads, (mm 2 ) 3.7×1.1 4.5×2.0 

number of transistors 30.000 70.000 

VDD, (nominal, V) 3.3 3.3 

Power, (mW) 6.8 10.3 

Energy/dec. bit/trellis state, (nJ) 1.4 2.1 

data throughput, (Mbit/s) 2 

consumption of 6.6 mW (decoder core alone), an energy 

per decoded bit and trellis state of 1.4 nJ, with a 

performance loss of 0.5 w.r.t. the ideal algorithm.. 

6. Bibliography 

[1] F. Lustenberger, M. Helfenstein, G. S. Moschytz, H.- 

A. Loeliger, F. Tarköy, “All-Analog Decoder for a Binary 

(18, 9, 5) Tail-Biting Trellis Code”, in Proc. ESSCIRC, 

pp. 362-365, Duisburg, Germany, Sep. 1999 

[2] M. Moerz, T. Gabara, R. Yan, J. Hagenauer, “An 

Analog 0.25 um BiCMOS Taibiting MAP Decoder”, in 

Proc. IEEE ISSCC, pp. 356-357, San Francisco, CA, Feb. 

2000 

[3] C. Winstead, J. Dai, S. Yu, C. Myers, R. R. Harrison, 

C. Schlegel, “CMOS Analog MAP Decoder for (8,4) 

Hamming Code”, IEEE J. Solid-State Circ., vol. 39, no.1, 

pp. 122-131, Jan. 2004 

[4] V. C. Gaudet, P. G. Gulak, "A 13.3-Mb/s 0.35-um 

CMOS Analog Turbo Decoder IC with a Configurable 

Interleaver", IEEE J. Solid-State Circ., vol. 38, no. 11, pp. 

2010-2015, Nov. 2003 

[5] A. Graell i Amat, S. Benedetto, G. Montorsi, D. 

Vogrig, A. Neviani, A. Gerosa, "An Analog Turbo 

Decoder for the UMTS Standard", to be presented at 2004 

IEEE ISIT, Chicago, IL USA, June 27 - July 2, 2004 

[6] C. Berrou, A. Glavieux, P. Thitimajshima, "Near 

Shannon limit error-correcting coding and decoding: 

Turbo codes", in Proc. of ICC, Geneva, pp. 1064-1070, 

May 1993. 

[7] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, 

“Optimal decoding of linear codes for minimizing symbol 

error rate,” IEEE Trans. Inform. Theory, vol. 20, pp. 284– 

287, Mar. 1974. 

[8] S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, 

"Soft-input soft-output modules for the construction and 

distributed iterative decoding of code networks," 

European Trans. Telecommuncations, vol. 9, pp.155-172, 

Mar. 1998. 

[9] H.-A. Loeliger, F. Lustenberger, M. Helfenstein, F. 

Tarköy, “Probability Propagation and Decoding in Analog 

VLSI”, IEEE Trans. Inform. Theory, vol.47, no.2, pp. 

837-843, Feb. 2001 

[10] G. Montorsi, S. Benedetto, "Design of fixed-point 

iterative decoders for concatenated codes with 

interleavers", IEEE J. Sel. Areas Comm., vol. 19, n. 5, pp. 

871-882, May 2001. 

[11] F. Lustenberger, H.-A. Loeliger, "On Mismatch 

Errors in Analog-VLSI Error Correcting Decoders", Proc. 

of ISCAS '01, Sydney, Australia, vol. IV, pp. 198-201, 

2001.


EFFECT OF ELECTRODE OFFSET ON THE 

CMRR OF THE CURRENT BALANCING 

INSTRUMENTATION AMPLIFIERS 

Refet Firat Yazicioglu 1,2 , Patrick Merken 1 , Chris Van Hoof 1,2 

1 IMEC, Kapeldreef 75, 3001 Leuven, Belgium 

2 K. U. Leuven, ESAT-INSYS, Kasteelpark Arenberg 10, 3001 Leuven, Belgium 

E-mail: Refet.Firat.Yazicioglu@imec.be 

ABSTRACT 

This paper describes the effect of the electrode-offset 

voltage on the CMRR of the current balancing 

instrumentation amplifiers (CBIA). Calculated CMRR 

behavior of the implemented instrumentation amplifier 

(IA) in 0.5 µm CMOS technology is compared with the 

simulated and measured results. Finally, a technique for 

improving the CMRR of IA under electrode-offset is 

proposed. 


The most important challenge for extracting the low-level 

biopotential signals is rejecting the high-level commonmode 

signals coupled to the human body from the mains. 

This common-mode signal can be 4-5 orders of magnitude 

higher than the biopotential signals. Therefore, an IA, 

which has a high CMRR, is a vital component for 

biopotential acquisition systems. 

Another main problem for biopotential acquisition 

systems is the electrode offset. In addition to high 

common mode signals, biopotential signals have large DC 

offsets due to the mismatches between the electrodes. A 

commonly used electrode type for biopotential 

measurements is the Ag/AgCl electrode. Fig. 1 shows the 

measured offset voltages from several Ag/AgCl electrodes 

relative to the ground. Unless the electrode-offset voltage 

is filtered, it will lead to the saturation of the IA. 

Therefore, a high performance IA should filter the DC 

offset voltage as well as rejecting the common-mode 

signals coupled to the human body. 

An integrated IA is first presented by [1]. This IA does not 

need any matched resistors or trimmed components for 

achieving high CMRR. Operation of the circuit is based 

on balancing the currents of the input pair transistors, and 

gain is defined by the ratio of the two resistors. The 

technique, use of current balancing for achieving high 

CMRR, is later applied to many monolithic 

instrumentation amplifiers ([2]-[7]), where together with a 

high pass filter ([5], [7]) these CBIAs can be used to filter 

the DC electrode offset . 

In this paper, we present the effect of the DC electrode 

offset on the CMRR of the CBIAs. Mechanisms 

responsible for the reduction of the CMRR under the DC 

electrode offset are defined and equations describing the 

9 

CMRR of the CBIA architecture of [5] are derived and 

compared with the simulated and measured results. 

Finally, a technique for improving the CMRR of the 

CBIAs under electrode offset is proposed. 

Figure 1. Measured DC electrode offset voltages 

from different Ag/AgCl electrodes relative to 

ground. 

2. CMRR MODEL OF THE CBIA 

ARCHITECTURE 

Fig. 2 shows the simplified schematic of one of the recent 

CBIAs [5], where CMRR of the IA is improved by [6]. 

Circuit consists of two feedback loops. First feedback loop 

converts the differential input voltage into current. This 

current is copied to the second feedback loop, where it is 

converted into voltage. Therefore, the gain of the circuit is 

defined by the ratio R2/R1. It is important to note that any 

current passing through resistor R1 is supplied by the 

current sources M3 and M4. Hence, any DC input will 

only affect the quiescent operating points of the current 

mirrors M1-M6. Therefore, in our analysis we have 

assumed that input differential electrode offset is only 

affecting the transconductances of the transistors of the 

current mirrors, M1-M6. Moreover, we have also assumed 

that transconductance of a MOS transistor is much larger 

than its output transconductance. 

CMRR analysis of the circuit is divided into two groups. 

First one is the systematic CMRR of the circuit, which 

defines the limit of the CMRR due to the topology, and 

second one is the reduction of the CMRR due to the 

mismatches introduced by the DC electrode offset.

Figure 2. Simplified schematic of the IA proposed 

by [5]. 

2.1 Systematic CMRR 

Systematic CMRR is defined by the topology of the circuit 

and finite unless circuit is fully differential. Fig. 3 shows 

the low-frequency small signal model of the first feedback 

loop of the IA of Fig. 2. Assuming matched transistor 

parameters and large gmi, common mode gain of the first 

feedback loop can be written as: 

I I g g ( 2g 

+ g ) 

A 


1 2 dsl o 1 m 

CM = = − = 

(1) 

v v 2 g m g ml 

where gml and gdsl is the transconductance and output 

transconductance of the NMOS current mirrors of Fig. 2, 

go is the total output transconductance of current sources 

M3 and M4, gm is the transconductance of the input pair 

transistors, and g1 is the transconductance of the first gain 

resistance, R1. Fig. 4 shows the small signal model of the second 

feedback loop. Similar to the previous analysis, 

differential gain of the circuit can be written as: 

vout 1 

= 

(2) 

I − I 2g 

( 2 1 ) 2 

assuming a large open-loop opamp gain, A v. 

Figure 3. Low-frequency small signal model of 

the first feedback loop of IA of Fig. 2. 

Systematic CMRR of the circuit can be found by 

combining Equations (1), (2), and the differential gain of 

the IA, which is g 1/g 2. 

10 

Figure 4. Low-frequency small signal model of 

the second feedback loop of IA of Fig. 2. 

CMRR 

A 

2 g 

g 

DM 

1 m ml 

sys = = 

(3) 

A CM g dsl g o ( 2 g1 

+ g m ) 

Equation (3) states that in order to maximize the CMRR of 

the IA, transconductance of first gain resistance, g 1, and 

transconductances of the input pair transistors should be 

maximized. In addition to that, output resistances of the 

current sources M3-M6 should be as high as possible, 

which is already demonstrated by [6]. It is important to 

note that systematic CMRR defines the maximum limit of 

CMRR under ideal conditions and will be reduced by the 

process related mismatches. 

2.2 CMRR Limit Due to Electrode Offset 

Even if the transistors are perfectly matched, the 

differential DC electrode offset voltage introduces 

operating point mismatches to the IA presented in the 

previous section. Assuming that common-mode to 

common-mode gain of the first stage is infinitesimally 

small, mismatches due to the electrode offset can be 

divided into two groups. First one is due to the mismatch 

of the drain-to-source voltages of the input pair transistors 

and second one is the mismatch of the output 

transconductances of the current sources M3 and M4. 

Due to the fact that CBIAs are forcing the input pair 

transistors to operate at the same quiescent current, gateto-source 

voltages of the input pair transistors are 

equalized. Therefore, any DC offset at the gate of the input 

transistors will affectively create a mismatch at the source 

voltages of these transistors. As a consequence, a 

mismatch of drain-to-source voltage is created, leading to 

a mismatch of the output transconductances of the input 

transistors. Fig. 3 shows the introduced mismatch 

parameter of the output transconductances to the input pair 

transistors, ±∆gds/2. CMRR of the circuit due to the output 

transconductance mismatch can be written as: 

g1 

g2 

g m 

CMRR R ( Vin 

) = = 

∆ 

(4) 

∆g 

⋅g 

g ⋅ g ∆g 

( ds( 

) ) ( ) ∆Vin 

1 m 2 

ds( 

∆Vin 

) 

g

Assuming that the input transistors are always operating in 

saturation region, output transconductance of a MOS 

transistor can be written as: 

I ds 

g ds = (5) 

V + V 


E 

where Ids is the drain-to-source voltage of the MOS 

transistor, VE is the early voltage, and Vds is the drain-tosource 

voltage. Equation 5 can be used to derive the 

change of gds, ∆gds, with respect to ∆Vds and can be 

written as: 

Ids 

∆Vds 

∆ gds 

= 2 

(6) 

V 

E 

assuming that V A is much larger than V ds. ∆V ds of the 

input transistors have two components. First one is due to 

the source voltage mismatch, which equals to the input 

DC voltage mismatch, and second one is due to the finite 

g mi, of the transconductance amplifier. Therefore, ∆V ds 

can be written as: 

ds 

⎛ g ⎞ 1 

∆V 

= ∆ 

⎜ + 

⎟ 

ds Vin 

1 

(7) 

⎝ gmi 

⎠ 

Combining equations (4), (6), and (7) gives the CMRR 

equation of the IA as: 

CMRR 

g 

V 

2 

m E 

R ( ∆ Vin 

) = 

(8) 

Ids 

( 1 + g1 

g mi ) ∆Vin 

As a result, in order to maximize CMRR R, g 1 should be 

much smaller than the g mi, and input pairs should be 

designed as long and wide transistors to maximize both 

g m/I ds and V E 2 . Under low power dissipation, gmi will be 

small, therefore g 1 should be decreased to compensate the 

small value of g mi. 

Second mismatch due to the input DC offset voltage is the 

mismatch of the output transconductances of the current 

sources M3 and M4. Due to the fact that any DC current 

passing through the first gain resistance is supplied by 

current sources, matching of their quiescent operating 

point is disturbed by the input DC offset voltage. If the 

circuit is designed for low power dissipation, any 

electrode offset will disturb the quiescent currents of these 

current sources in the order of µA range, resulting in a 

large output transconductance mismatch depending on the 

topology of the current mirrors. Fig. 3 shows the added 

parameter, ±∆g o/2, representing the mismatch of the 

output transconductances of the current sources, M3 and 

M4. CMRR equation of the circuit considering only the 

mismatches of the current sources can be written as: 

CMRR 

A 

g 

g 

DM 

1 2 

1 

M ( ) = = 

= 


(9) 

ACM 

∆go 

( Vin 

) 2g 

2 ∆g 

∆ 

o( 


) 

1 

2g 

where ∆g o(∆V in) depends on the current mirror topology. 

For a cascode current mirror, similar to [6], and assuming 

equal sized mirror transistors, ∆g o(∆V in) can be written as: 

1. 

5 

1. 

5 

[ ( Ids 

+ ∆Vin 

g1 

) − ( Ids 

− Vin 

g1 

) ] 

2 

1 VE 

∆ go = 

∆ 

(10) 

2K 

n 

11 

where K n is the MOS transistor transconductance 

parameter. Therefore, CMRR M equation describing the 

CMRR of the IA based on the mismatches of the current 

sources can be written as: 

CMRR 

∆V 


M ( ∆Vin 

) 

g < I 

1 

ds 

= 

1. 

5 

( I + ∆V 

g ) − ( I − ∆V 

g ) 

ds 

2g1 


1 

V 

2 

E 

2K 

ds 

n 


1. 

5 

1 

(11) 

Function CMRR M is an increasing function with 

increasing g 1. However, if g 1 is selected to be large, then 

input stage of the IA could only accept small values of 

electrode offset under low power dissipation. Therefore, 

an ideal solution will be maximizing the first gain 

resistance according to Equation (8) and maximizing 

CMRR M by using active current mirrors, where the total 

output transconductance is divided by the feedback. 

Therefore, use of active current mirrors will multiply the 

CMRR M with the open-loop gain of the feedback path. 

As a result, total CMRR of the circuit can be written as the 

superposition of the three mechanisms, systematic CMRR, 

CMRR due to the transconductance mismatch of the input 

transistors, and CMRR due to the mismatch of the output 

transconductance of the current sources. 

1 1 1 1 

= + + 

(12) 

CMRR CMRR CMRR CMRR 

T 

SYS 

Although equations are derived for a single CBIA 

topology, It can be applied to all the CBIA topologies [2]- 

[7], knowing that the mechanisms affecting the CMRR 

under electrode offset are the mismatch of the output 

transconductances of the input pair and the current sources 

connected to the first gain resistor. 

2.3 Verification of the Model 

In order to verify the presented model, a CBIA similar to 

the circuit shown in Fig.2 is implemented in 0.5-µm 

CMOS technology. Circuit uses active current mirrors for 

implementing M1-M6, which increases the CMRR M. 

Circuit is optimized for low power dissipation and for 

achieving high CMRR under high electrode offset 

voltages (up to 50 mV). Circuit dissipates 110 µA from a 3 

V supply, and bias current of the input transistors are 12 

µA each. Gain of the IA is 10 V/V with a first gain 

resistance of 10 kΩ. 

Fig. 5 shows the comparison of simulated, calculated, and 

measured CMRR of the IA at 50 Hz with changing input 

offset voltage. Components of the total CMRR equation, 

Equation (12), are also shown in Fig. 5 to demonstrate 

their effect on the total CMRR. Simulated, calculated, and 

measured CMRR fits well in the large offset regions. Use 

of the active current mirrors increases the CMRR M, 

leaving CMRR R as the dominant mechanism defining the 

total CMRR of the IA. Under low input electrode offset 

voltage, total CMRR of the IA is defined by the process 

related mismatches of the circuit. However, as the input 

DC offset increases, which is the case if the IA is used for 

R 

M

measuring biopotential voltages, total CMRR is defined 

by the mismatches introduced by the input DC offset. 

Figure 5. Comparison of the simulated, calculated, 

and measured CMRR of the fabricated IA. 

CMRR R is shifted by 5 dB to increase visibility. 


3. CMRR IMPROVEMENT 

CMRR of the IA can be further improved by actively 

adjusting the drain-to-source voltage of the input pair 

transistors, which ideally sets the CMRR R to infinity in the 

expense of reduced input common mode range. Fig. 6 

shows the improved IA circuit. Transistors M p3 and M p4 

act as a source follower and actively adjust the drain 

voltage of the transistors Mp 1 and Mp 2. Therefore, even if 

there is electrode-offset at the input, drain-to-source 

voltage of the input pair transistors will be equalized. DC 

level shifter [8] ensures that Mp1 and Mp2 stay in 

saturation. Since drain-to-source voltages are equalized, 

CMRR R component of the Equation (12) vanishes. 

Figure 6. Schematic of the modified circuit for 

improving the CMRR of IA under electrodeoffset. 

Fig. 7 shows the simulation result of the improved IA. 

Note that simulated CMRR is very close to the calculated 

CMRR M. Since all the causes for the lowered CMRR 

under electrode-offset are eliminated, CMRR will also be 

defined by the process related mismatches of the circuit as 

it is for the low offset region. 

12 

Figure 8. Comparison of calculated and simulated 

CMRR of the improved IA. 

4. CONCLUSIONS 

CMRR of the CBIAs is highly reduced by the electrodeoffset 

voltage. In this paper, we presented the mechanisms 

behind this CMRR reduction. Proposed model is 

compared with the simulated and measured CMRR of the 

implemented IA. CMRR of the implemented IA is 

improved under electrode-offset voltage using active 

current mirrors. Finally, a circuit technique is proposed for 

improving the CMRR of the IA under large DC electrode 

offset voltages. Although applied to a single IA topology, 

presented equations and circuit improvement technique 

can be used for all the CBIA structures. 

5. REFERENCES 

[1] H. Krabbe, “A High-Performance Monolithic 

Instrumentation Amplifier,” IEEE ISSCC, vol. 14, 

pp. 186-187, Feb. 1971. 

[2] F. L. Eatock, “A Monolithic Instrumentation 

Amplifier with Low Input Current,” IEEE ISSCC, 

vol. 16, pp. 148-149, Feb. 1973. 

[3] A. P. Brokaw and M. P. Timko, “An Improved 

Monolithic Instrumentation Amplifier,” IEEE JSSC, 

vol.10, iss. 6, pp. 417-423, Dec. 1975. 

[4] R. J. Van de Plassche, “A Wide-Band Monolithic 

Instrumentation Amplifier,” IEEE JSSC, vol. 10, no. 

6, pp. 424-431, Dec. 1975. 

[5] R. Martins, S. Selberherr, and F. A. Vaz, “A CMOS 

IC for Portable EEG Acquisition Systems,” IEEE 

Trans. on Inst. and Meas., vol. 47, iss. 5, pp. 1191- 

1196, Oct. 1998. 

[6] P. A. dal Fabbro and C. A. dos Reis Filho, “An 

Integrated Instrumentation Amplifier with Improved 

CMRR,” 15 th Symp. On Int. Cir. And Sys. Design, 

pp. 57-61, Sept. 2002. 

[7] M. S. J. Steyaert, W. M. C. Sansen, and C. 

Zhongyuan, “A Micropower Low-Noise Monolithic 

Instrumentation Amplifier for Medical Purposes,” 

IEEE JSSC, vol. 22, iss. 6, pp. 1163-1168, Dec. 

1987. 

[8] J. Ramirez-Angulo, “Low Voltage Current Mirrors 

for Built-in Current Sensors,” ISCAS, vol. 5, pp. 529- 

532, 1994.


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A UP TO 1GHZ LOW-POWER CONTINUOUS-TIME “3RD-ORDER 

FILTER+INTEGRATOR” CHAIN 

FOR WIRELESS BODY-AREA NETWORK RECEIVERS 

S. D’Amico 1(Ph.D. Student) , T. Grassi 1 , Ryckaert Julien 2 , A. Baschirotto 1 

1 Department of Innovation Engineering,University of Lecce, Italy 

E-mail: stefano.damico@unile.it, teobaldograssi@libero.it, andrea.baschirotto@unile.it 

ABSTRACT 

A CMOS filter+integrator baseband chain 

embedded in a WBAN receiver is designed in a 

0.13µm CMOS technology at 1.2V. The 3 rd -order 

LP filter cut-off frequency and dc-gain can be tuned 

from 250MHz up to 1GHz and from 0dB up to 

15dB, respectively. The filter power consumption is 

limited to 3.2mW in the most stringent conditions, 

i.e. 1GHz cut-off frequency, 15dB dc-gain. For 

fo=250MHz and unitary dc-gain, the power 

consumption is 210µW. These results are obtained 

by using a very compact circuit design that allows to 

avoid parasitic poles and Common-Mode FeedBack 

circuit. A similar structure gives a 1GHz-UGB 

integrator with 120µW. 


The nodes of a Wireless Body Area Networks 

(WBANs) are usually placed close to the body on or 

in everyday clothing [1]. A WBAN topology 

comprises many transmit only sensor nodes, that 

have to be very simple, low cost and extremely 

energy efficient, some transceiver nodes, that afford 

a somewhat higher complexity to sense and act, and 

few high capability nodes, e.g. master nodes with 

high computational capabilities and support for 

higher data rates. Compared to other wireless 

networks a WBAN has some distinct features and 

requirements. Due to the close proximity of the 

network to the body, electromagnetic pollution 

should be extremely low. Thus, a non-invasive 

WBAN requires a low transmit power. In addition 

the transmission data-rate is very low. A possible 

technology for non-invasive WBAN communication 

is Low-Data-Rate Ultra-Wideband (LDR-UWB). A 

possible UWB receiver is shown in Fig. 1. The 

baseband chain is composed by a 3 rd -order LP filter 

2 IMEC-Belgium 

E-mail: ryckj@imec.be 

17 

and an integrator, in order to relax the A/D 

converter requirements [2]-[7]. Due to the LDR 

feature, the overall chain is required to feature a 

SNDR of about 30dB for maximum input signal 

amplitude of 100mVpp. 

90¡ 

Pulser 

Baseband chain 

3rd-order 

LPF 

3rd-order 

LPF 

Fig. 1 - UWB receiver architecture 

ADC 

ADC 

The relative simplicity of this implementation 

compared to the traditional super-heterodyne 

architecture. This receiver has no, Phase-Locked 

Loop (PLL) synthesizer, nor intermediate stage (IF) 

filtering. This simplicity translates to lower material 

costs and lower assembly costs. 

Even with the selection of an optimal 

communication system, the implementation is of 

extreme importance to reach ultra-low power 

consumption in the sensor node. The design of ultralow-power 

building blocks in advanced CMOS 

technologies is mandatory for this application. In the 

following circuit solutions for the blocks embedded 

in the baseband-chain receiver are proposed, which 

exploit the reduced DR requirement by adopting an 

aggressive implementation. 

2. THE 3 RD -ORDER LOW-PASS 

FILTER

Fig.2 shows the proposed 3 rd –order lowpass filter. 

It is composed by a transconductance input stage 

(the differential pairs M1-M2 and the additional 

M9-M10) and an active load (M3-…-M8 and C1- 

C2-C3). 


Fig. 2 - The filter design architecture 

The filter transfer function is: 

V 

V 

out 


= 

s 

3 

g 

CC 

C 

1 

g 

2 

3 

g 

m3 

m5 

m7 

(1) 

g 

m1 

g 

m5 

2⎛ 

C1C 

2 C3C 

⎞ ⎛ 2 C1 

C ⎞ 2 

+ s ⎜ 

⎟ ⎜ ⎟ 

⎜ 

+ 

⎟ 

+ s 

⎜ 

+ 

⎟ 

+ 1 

⎝ gm3gm7 

gm5gm7 

⎠ ⎝ gm3 

gm7 

⎠ 

The poles frequencies are given by: 

ω 1 =− g m3 

C 1 

ω 2/3 = g m5g m7 

C 2C 3 

while the gain and Q2/3-factor are: 

G = g m1 

g m5 

Q 2/3 = C 3 ⋅ g m7 

C 2 ⋅ g m5 

(2) 

(3) 

This structure presents the following advantages: 

� Compact structure: few transistors and only three 

capacitors are used. 

� Low power consumption: only two current 

branches are used for each polarity. 

� Accurate frequency response: no non-dominant 

poles are presented and all the transistors 

processing the signal are NMOS, guaranteeing 

also immunity to technological spread. 

� Absence of CMFB circuit: this avoids additional 

power consumption. The output DC voltage is 

fixed by the VGS of transistors M5 and M6. 

18 

� Good linearity vs. power: the load exhibits the 

opposite non-linear behavior of the driver, and 

so no linearization is necessary for the input 

pair. 

The dc-gain is programmed for the two levels (0dB 

& 15dB) by adding an additional input pair (Mn- 

Mn+1) to increment the gm1 value. Since this solution 

does not change the current level in the load devices, 

this dc-gain tuning strategy does not affect the filter 

poles position, as it is evident from (2), and (3). 

The cut-off frequency is tuned in the required 

250MHz-1GHz range by changing the bias current 

(I1 and I2): the transitors trasconductances are 

changed, and, thus, the cut-off frequency is tuned. 

The in-band noise remains constant (and also the 

SNR). On the other hand for lower curt-off 

frequencies the power consumption is strongly 

reduced. The drawback of this approach is the fact 

that the devices have to be guaranteed to operate in 

saturation region for all the tuning range. 

3. THE INTEGRATOR 

Fig. 3 shows the schematic of the proposed 

integrator. The complete transfer function is given 

by: 

g 

H(s)= m1⋅r o 

1 

⋅ 

1−(gm4−g m3)⋅r o 

r 

1+s⋅C⋅ o 

1−(gm4−g m3)⋅r o (4) 

Fig. 3 - The integrator structure 

The use of a positive feedback (M4) increases the 

low-frequency load and, thus, the dc-gain to almost 

70dB with a 1GHz-UGB. The linearity is guarantee 

by complementary non-linearity in the driving (M1) 

and load (M3//M4) device.


4. SIMULATIONS RESULTS 

The 3 rd order low-pass filter and the integrator have 

been designed in a standard 0.13µm CMOS 

technology with a 1.2V supply voltage. For the LPF 

non-minimum device sizes (5µm /0.3µm) have been 

used in order to avoid mismatch effects. For the 

same reason and in consideration that the load of the 

following block is about 100fF, all the capacitors 

have been designed to be 100fF. This results in a 

SNR in excess w.r.t. the specs. TABLE I summarizes 

the filter performances for the four limit cases. The 

minimum power consumption ranges between 

210µW (f0=250MHz, dc-gain=0dB), and 3.2mW 

(f0=1GHz, dc-gain=15dB). When the dc-gain is kept 

equal to 0dB, the input-referred noise decreases 

from 18 nV Hz to 10 nV Hz by passing from 

250MHz to 1GHz, at 15dB dc-gain. The THD is 

about —30dB for a tone at fo/3 with the maximum 

output signal amplitude (100mVpp). The SNR is 

comprised among 45dB to 53dB. Finally Table II 

summarizes the filter performances 

TABLE I –SUMMARY OF THE FILTER 

PERFORMANCES 

Case I II III IV 

fo [MHz] 250 1000 

DC-Gain [dB] 0 15 0 15 

IR-Noise Level [nV/ √Hz] 18 4.5 10 2.5 

IR-In-band Noise [µVrms] 285 71 320 80 

THD@100mVpp [dB] -30 -30 -32 -37 

SNR [dB] 45 53 44 53 

Power consumption 0.2 1.2 0.5 3.2 

[mW] 

1 9 

19 

Fig. 4 - Filter frequency response for four cases 

TABLE II -INTEGRATOR PERFORMANCE 

SUMMARY 

UGB [GHz] 1 

DC-Gain [dB] 69 

Phase Margine [degree] 88 

IR-Noise Level [nV/ √Hz] 5.4 

THD(@100mVpp, 1GHz) [dB] -47 

Cload [fF] 130 

Power consumption [mW] 0.12 


A low-power wide-band CMOS continuous-time 

baseband path (integrator+filter) to be embedded in 

a WBAN receiver is presented. The filter cut-off 

frequency and dc-gain can be tuned from 250MHz 

up to 1GHz and from 0dB up to 15dB, respectively. 

However, the maximum filter power consumption is 

limited to 3.2mW in the worst-case conditions (i.e. 

1GHz cut-off frequency, 15dB dc-gain). The 

integrator exhibits a UGB of 1GHz consuming 

120µW. These results are obtained by using a very 

compact circuit design that avoids parasitic poles 

and CMFB circuit. 

6. REFERENCES 

[1] S. DONNAY, C. VAN HOOF AND B. 

GYSELINCKX, “Body area sensor networks for 

health monitoring applications” 2 nd Int. Workshop

on Sensor and Actor Network Protocols and 

Applications (SANPA), Boston 2004. 

[2] F. REZZI, I. BIETTI, M. CAZZANIGA, and R. 

CASTELLO, “A 70-mW Seventh–Order Filter with 

7-50 MHz Cutoff Frequency and Programmable 

Boost and Group Delay Equalization” IEEE Journal 

of Solid-State Circuits, vol. 32, no. 12, December 

1997 

[3] I. MEHR and D. R. WELLAND, “A CMOS 

Continuous-Time Gm-C Filter for PRML Read 

Channel Applications at 150 Mb/s and Beyond” 

IEEE Journal of Solid-State Circuits, vol. 32, no. 4, 

April 1997 

[4] A. WYSZYNSKI and R. SCHAUMANN, 

“Using Multiple–Input Transconductors To Reduce 

Number of Components In OTA-C Filter Design” 

IEE Electronics Letters vol.28, no.3, January 1994. 

[5] S. D’AMICO and A. BASCHIROTTO “A 

compact High-Frequency Low-Power Continuous- 

Time Gm-C Biquad Cell” IEE Electronics Letters 

29 th May 2003, Vol 39, No.11, pp. 821-822. 

[6] A. BASCHIROTTO, U. BASCHIROTTO and 

R. CASTELLO, “High-frequency CMOS lowpower 

single-branch continuous-time filters” Proc. 

IEEE Int. Symp. Circ. Syst., 2000, pp. II-557, II-580. 

[7] A. L. COBAN and P.E. ALLEN: ‘Low-voltage 

CMOS transconductance cell based on parallel 

operation of triode and saturation transconductors’ 

IEE Electronics Letters. vol.30, no.14, July 1994. 


20


ENERGY-EFFICIENT BASEBAND RECEIVER 

DESIGN IN DEEP SUB-µm TECHNOLOGY 

Armin Wellig 

STMicroelectronics – Advanced System Technology 

39, Chemin du Champ-des-Filles, 1228 Plan-les-Ouates, Geneva, Switzerland 

E-mail: armin.wellig@st.com 

ABSTRACT 

Novel physical layer techniques (e.g., hybrid-ARQ) 

dramatically increase the embedded memory of baseband 

receivers. Frequent accesses to large memories are among 

the top dynamic power drainers. Moreover, shrinking 

form factors of portable devices pushes for deep sub-µm 

technology suffering from an increase in static leakage 

power. In this paper, we demonstrate the need to combine 

low power techniques at the system, architecture and 

device level to ensure energy-efficient designs in deep 

sub-µm. The 3GPP-HSDPA receiver implemented with 

STMicroelectronics’ 90nm CMOS technology serves as a 

case study, where energy reductions of up to 70% are 

observed compared to more conventional designs. 


A major challenge of portable device manufacturers is to 

guarantee long battery life despite the enormous increase 

in system-on-chip (SoC) complexity. To maximize the 

amount of computation delivered per battery life, the 

energy consumed per operation in a specified amount of 

time should be minimized. However, this only addresses 

one part of the “power crisis”. For most of today’s batteryoperated 

products, there will be times when the device is 

“on” but not in full active use. The cell phone in standby is 

the most notable example of this, where the phone does 

little more than monitor for an incoming call, and thus 

consumes less power than during phone calls or other 

activities. Since cell phones spend so much time in 

standby mode, the energy consumed during standby 

(mainly due to leakage current) often determines the 

overall battery life of the phone. 

To achieve energy-efficiency in deep sub-µm technology, 

designers are forced to use a combination of low power 

techniques at multiple levels (i.e., system, architecture, 

circuit and process) tailored to a particular application. In 

this paper, we focus on the design challenges of memorydominated 

building blocks of wireless baseband receivers; 

for example, the introduction of a physical layer 

retransmission scheme such as the H-ARQ [1] results in a 

6x memory increase. We show how power reduction 

techniques yield important dynamic and static energy 

savings at different design levels. In particular, the circuit 

activity can be reduced at the architectural level by 

application-specific access pattern transformations and 

memory partitioning strategies; at the system level, 

system-driven voltage scaling techniques are discussed as 

21 

a means of reducing the leakage power during standby and 

finally, at the device level, the need for low power 

standard cell library is demonstrated. 

We limit the analysis to embedded SRAMs implemented 

with different CMOS device geometries as part of 

STMicroelectronics’ process technology portfolio. Some 

process details will not be disclosed due to confidentially 

constraints. 

2. ENERGY DISSIPATION IN CMOS 

Neglecting the short circuit currents during signal 

transitions, the energy dissipation of CMOS circuits can 

be split into a dynamic and static part, formalized as [2] 

2 

E L DD leak DD 

= α ⋅ C ⋅ V + I ⋅ V ⋅ ∆t 

( 1 ) 

where α is the switching activity, CL the load capacitance, 

VDD the supply voltage, Ileak the total leakage current [3] 

caused by reverse bias PN junction leakage, subthreshold 

leakage, oxide tunneling, hot carrier injection, gate 

induced drain leakage and channel punchthrough, and ∆t 

the time interval during which (1) is applicable. 

As finer geometry devices have been developed, the trend 

has been to reduce supply voltages, which has the positive 

side effect to save energy (due to the quadratic effect of 

VDD on dynamic energy). However, voltage levels seem to 

be stabilizing in the 1.0-1.2 Volts range in deep sub-µm, 

which means that future technologies will not 

automatically result in energy savings. Moreover, finer 

device geometries are also affected dramatically by 

leakage current. With the physics of the semi-conductor 

working against the designer – by raising the voltage 

threshold of the transistors the leakage current can be 

reduced, but this comes at a corresponding decrease in the 

speed of the transistor – the designer must turn to circuit, 

architecture and algorithm exploration to find energyefficient 

SoC solutions. 

3. DYNAMIC ENERGY REDUCTION 

Due to the limited space in this paper we will focus our 

discussions on energy-efficient memory systems. To 

illustrate the potential for dynamic energy savings, the 

average energy per SRAM access is plotted in Figure 1 for 

different device geometries and memory data buses (or 

access bit widths). From Figure 1a we can draw the 

following conclusions: 1) The access energy increases 

with memory size. This motivates memory hierarchy

designs, where frequently accessed data are placed into 

small, energy-efficient memories (e.g., L1/2 caches), 

while rarely accessed information is stored in large 

memories with high cost per access [4]. Its simplest form 

consists of breaking a large memory down into smaller 

banks of the same size. 2) Because of the quadratic effect 

of V DD on the dynamic energy, supply voltage reductions 

as a result of technology scaling accounts for major energy 

savings (e.g., V DD = 1.8V for 0.18µm versus V DD = 1.2V 

for 0.13µm technology). Moreover, the switched node 

capacitance C L also decreases with constant field scaling – 

the electric field across the gate-oxide does not change for 

the scaled technology to avoid irreversible gate-oxide 

breakdown – which further reduces the energy dissipation. 

Moreover, we can observe that the energy savings are less 

important in case only C L scales down (here, going from 

0.13µm to 90nm keeping V DD at 1.2V). This observation is 

in line with equation (1), which predicts (only) a linear 

reduction of the dynamic energy with respect to C L 

scaling. 

Figure 1. Average access energy for (a) different 

sub-µm technologies and (b) access bit widths. 

From Figure 1b we conclude that the access energy 

increases less than linearly with access bit-width for a 

fixed memory size. For example, for a fixed SRAM size of 

32.8k bits, accessing four times 8-bit words is 2.6x more 

expensive than accessing only once a 32-bit word (with 

the same data content). Thus, application-specific access 

pattern transformations such as packing, where for 

example N 8-bit samples are transformed into one 8N-bit 

word, can significantly reduce the dynamic energy of 

memory systems. 

4. STATIC POWER REDUCTION 

Leakage power becomes increasingly troublesome in deep 

sub-µm (see Figure 2a) for applications characterized by 

low active-to-standby ratios, i.e. ∆t ≅ standby period, and 

high memory requirements. Various techniques have been 

proposed to reduce the leakage power of SRAM cells [5]. 

At the device level, leakage reduction can be achieved by 

controlling the dimensions (length, oxide thickness, 

junction depth, etc.) and doping profile in the transistors. 

At the circuit level, leakage reduction is achieved by 

controlling statically or dynamically the voltage of the 

different device terminals (i.e., gate, drain, source and 

substrate). From a system architect’s perspective these 

low-level techniques are a design constraint and part of the 


22 

low-power standard cell library specification. At the 

architectural level, one key concept is supply voltage 

scaling to operate the SRAM cell in the sub-threshold 

region (generally referred to as drowsy mode [6]) or gating 

off the V DD at the expense of destroying the cell state. The 

energy reduction of drowsy SRAMs in a low-power 90nm 

CMOS process is shown in Figure 2b, where the bars 

indicate the total leakage power (left ordinate) and the 

lines the relative leakage reduction (right ordinate) with 

respect to “full V DD” operation. 

Figure 2. Leakage power of (a) different sub-µm 

technologies and (b) drowsy SRAM cells in 90nm. 

Note that (parts of) the SRAM can only be operated in 

drowsy mode if the stability of the cell can be guaranteed; 

that is, the logic state of the cell does not flip when 

reducing V DD as will be explained next. 

4.1 Stability of Drowsy SRAMs in sub-µm 

The static noise margin (SNM) of a SRAM cell is defined 

[7] as the minimum dc noise voltage necessary to flip the 

state of the cell. An estimate of the SNM can be obtained 

by drawing the static “butterfly diagram” (or voltage 

transfer characteristic (VTC)) as illustrated in Figure 3 and 

finding the maximum possible square between them. We 

observe that the eye opening is larger for a SRAM cell in 

standby mode (i.e., access transistors are off) compared to 

a cell in active mode (i.e., access transistors are on). 

Intuitively, the cell is most vulnerable to noise during a 

read access, since the ‘0’ storage node rises to a voltage 

higher than ground due to the bit-line discharge. 

Figure 3. Voltage transfer characteristic (VTC) for 

SRAM cell in (a) active and (b) standby mode. 

To analyze the limitation of stable “drowsy mode 

operation” in deep sub-µm technology, the SNM of a 

basic 6T-SRAM cell [5] was simulated in SPICE based on 

BSIM4 models in a 90nm process. As pointed out earlier,

the worst-case situation is under “read-disturb” conditions 

as shown in Figure 4a. For instance, setting the stability 

criterion to SNM = 100 mV (application-specific), the 

SRAM cell can safely be operated at supply voltages as 

low as V DD = 0.7 V during read access (accounting for 

process variations of up to 3σ and an operating 

temperature of 85°C). In order to be able to further 

decrease V DD, without relaxing the stability criterion, more 

sophisticated devices and circuits would be needed to 

support stable read operations tailored for ultra-low power 

applications (e.g., [8]). 


σ 

σ 

Figure 4. Stability of a drowsy SRAM cell in (a) 

active and (b) standby mode in a 90nm process. 

In standby mode, an (off-the-shelf) low-power SRAM can 

be operated in the sub-threshold region even for a process 

variation of up to 3σ and an operating temperature of 

85°C. Thus, incorporating dynamic supply voltage control 

in memory-dominated SoC designs is of great interest for 

applications characterized by long idle periods such as cell 

phones during standby. Finally, it should be noted that an 

increase in temperature is considerably less disturbing 

(∆SNM ≅ 1mV/15°C) to the cell stability than variations in 

the die (∆SNM ≅ 50 - 65mV @ 3σ). A more detailed 

analysis can be found in [9]. 

5. 3GPP-HSDPA RECEIVER 

5.1 Evolution of 3GPP 

Wideband code division multiple access (WCDMA) is the 

most widely adopted air interface for third generation (3G) 

systems and specified within the 3GPP alliance [1]. It 

provides peak bit rates of 2 Mbps and variable data rate on 

demand in a 5 MHz bandwidth. Average user data rates in 

the order of 200-300 kbps are expected under loaded 

network conditions [10]. The use of CDMA access 

technology implies a radio receiver composed of multiple 

fingers using offsets of a common spreading code to 

receive and combine several multi-path time-delayed 

signals. It is generally referred to as RAKE receiver. Other 

enhancements (compared to 2G systems like GSM [10]) 

impacting the physical layer complexity include soft 

handover, fast power control, multiple interleaving stages 

and Turbo codes. To define and limit the processing and 

storage requirements of power-constraint portable devices, 

the notion of “User equipment (UE) Capability Class” was 

introduced in 3GPP. In the specifications of the Release 4 

the UE Capability classes range from 32 kbps to 2 Mbps. 

To satisfy even higher data traffic demands, the 3GPP 

system aims to gradually increase the spectral efficiency 

σ 

σ 

23 

and to support higher user data rates, especially on the 

downlink direction of the communication path due to its 

heavier load. In this context, the 3GPP introduces a new 

feature in the Release 5 specifications denominated High 

Speed Downlink Packet Access (HSDPA). The HSDPA 

concept appears as an umbrella of features to improve 

both user and system performance. The signal processing 

concepts impacting the receiver complexity include an 

Adaptive Modulation and Coding (AMC) scheme, 

physical layer Hybrid Automatic Repeat Request (H- 

ARQ) and latency-constraint physical control decoding. 

The UE Capability Classes in Release 5 are defined up to 

10 Mbps, which significantly increases the processing 

load and thus motivates a hardware implementation of the 

HSDPA receiver to satisfy the power-delay constraints. 

5.2 Energy-efficient HSDPA receiver design 

Although in principle the adoption of user-specific 

orthogonal codes should exempt WCDMA systems at 

least from intra-cell interference, multi-path dispersive 

channels provide the receiver with a combination of 

correlated time-shifted replicas of the codes, thus 

compromising the orthogonality. While conventional 

RAKE processing is sufficient to meet the compliance 

requirements in Release 4, channel equalization was 

implemented as part of the HSDPA receiver to guarantee 

the capacity improvements envisioned in the Release 5 

specifications. The equalization is done in the frequency 

domain to take advantage of low-complexity FFT 

processing. Due to the limited space we do not give more 

details of the inner receiver architecture, but can be found 

in [11]. The outer receiver is in charge of decoding the 

incoming coded sequence via a prescribed algorithm to 

provide the coding gain for operation over noisy channels. 

It consists of a channel deinterleaving stage followed by 

H-ARQ related processing and Turbo decoding. 

Preliminary synthesis results of the HSDPA receiver, 

based on STMicroelectronics’ ultra-low leakage processes 

in 0.13µm and 90nm, are given in Table 1. 

Table. 1. Preliminary synthesis results of the 

HSDPA receiver design. 

Process 0.13µm 90nm 

Area estimates 7.235mm 2 3.703mm 2 

Memory -% 71 % 66 % 

One immediate consequence of introducing a fast physical 

layer retransmission scheme is an increase in memory 

size. From Table 1 we conclude that roughly 70% of the 

HSDPA data-path is composed of memory, where the 

biggest storage requirements stem from the H-ARQ. 

The idea behind H-ARQ is to initially trying to transmit 

the information with little redundancy. If the decoding 

fails on the first attempt, the receiver keeps the soft bits of 

the inadequately received block in memory. The receiver 

then uses old and new soft bits in the next decoding 

attempt. Note that up to 8 independent Stop-and-Wait

ARQ processes are supported to guarantee continuous 

transmission. Since the input samples into the H-ARQ are 

in chronological order (i.e., after deinterleaving and rate 

matching) the 8-bit samples can be packed into 64-bit 

words. The choice of the packing factor N (= 8) depends 

on the packing efficiency, defined as the percentage of 

useful data out of the accessed 8N-bit word. Moreover, 

mapping each ARQ process onto a different SRAM bank 

not only reduces the dynamic energy, but also enables 

supply voltage scaling of different banks (see Figure 5). 

Depending on the radio link configuration, application 

requirements and system capacity, each SRAM bank can 

be either in Read/Write Mode, Standby or Sleep mode. 

The banks in Sleep mode (i.e., no ARQ process is 

assigned) are idle over a long period (seconds to minutes) 

and can be gated off. Conversely, the memory content 

during Standby mode must be preserved (∆t ≥ 10 ms) 

while operating the SRAM in sub-threshold. The projected 

energy savings with respect to a conventional multi-bank 

architecture without packing and drowsy mode support is 

shown in Figure 6. It is assumed that the network 

implements “Proportional Fair” packet scheduling [12] 

and that all users have the same application requirements 

(here 64 kbps). 

Access energy [uJ] 

Figure 5. H-ARQ Architecture template. 

Figure 6. Projected energy reduction of the 

HSDPA receiver design in a 90nm process. 

Note that as more users await new data packets the 

standby periods increase and so thus the leakage power. 

Depending on the number of users to be served in a cell, 

implementing a multi-bank SRAM architecture with 

packing and drowsy mode support results in an overall 

energy reduction of up to 70%. 


Leakage Red-% 

24 

6. CONCLUSION 

As deep sub-µm technology invades the market of 

portable devices, a profound knowledge of the application 

characteristics down to the silicon is critical to asses 

design choices. In this paper, we have demonstrated the 

need to combine low power design techniques at the 

levels of system (i.e., system-driven voltage scaling), 

architecture (i.e., access pattern transformations and 

memory partitioning) and device (i.e., low power standard 

cell library) to ensure energy-efficient designs of 

memory-dominated baseband receivers. Choosing a 

multi-bank SRAM architecture with packing and drowsy 

mode support to implement the H-ARQ as part of the 

HSDPA receiver design yields an energy reduction of up 

to 70% in STMicroelectronics’ 90nm CMOS technology 

over conventional designs. 

7. REFERENCES 

[1] 3 rd Generation Partner Project, www.3gpp.org. 

[2] A.P. Chandrakasan, S. Sheng and R.W. Broderson, 

Low-power CMOS digital design, IEEE J. of Solid- 

State Circuits, Vol. 27, No. 4, pp. 473-484, 1992. 

[3] K. Roy et al., Leakage Current Mechanisms and 

Leakage Reduction Techniques in Deep- 

Submicrometer CMOS Circuits. Proceedings of the 

IEEE, Vol. 91, No.2, pp. 305-327, 2003. 

[4] L. Benini et al., Increasing energy efficiency of 

embedded systems by application-specific memory 

hierarchy generation, IEEE Design & Test of 

Computers, vol. 17, no. 2, pp. 74-85, 2000. 

[5] Y. Nakagome et al., Review and future prospects of 

low-voltage RAM circuits, IBM J. Research & 

Development, Vol. 47, No. 5/6, pp. 525-551, 2003. 

[6] K. Flautner et al, Drowsy caches: simple techniques 

for reducing leakage power, Int. Symposium on 

Computer Architecture, pp. 25-29, 2002. 

[7] E. Seevinck et al., Static Noise Margin Analysis of 

MOS SRAM Cells, IEEE J. of Solid-State Circuits, 

Vol. 22, No. 5, pp. 748-754, 1987. 

[8] B.H. Calhoun and A. Chandrakasan, Characterizing 

and Modeling Minimum Energy Operation for 

Subthreshold Circuits, ISLPED, pp. 90 - 95, 2004. 

[9] A. Wellig and J. Zory, Static Noise Margin Analysis 

of Sub-threshold SRAM cells in deep sub-micron 

technology, submitted to PATMOS 2005. 

[10] T. Halonen et al., GSM, GPRS and EDGE 

Performance: Evolution Towards 3G/UMTS. Second 

Edition. John Wiley & Sons, Inc., New York, 2003. 

[11] D. Loiacono et al., Serial Block Processing for Multi- 

Code WCDMA Frequency Domain Equalization, 

IEEE WCNC, Vol. 1, pp. 164-170, 2005. 

[12] H.J. Kushner et al., Convergence of proportional-fair 

sharing algorithms under general conditions, IEEE 

Trans. on Wireless Communications, Vol. 3, Issue 4, 

pp. 1250-1259, 2004.


A LOW-VOLTAGE, LOW-DISTORTION (1.2V, 

29.5dBm OIP3) RECONFIGURABLE BASEBAND 

BLOCK FOR MOBILE APPLICATIONS 

Nicola Ghittori 1 , Andrea Vigna 1 , Piero Malcovati 2 , Stefano D’Amico 3 , Andrea Baschirotto 3 

1 Department of Electronics, 2 Department of Electrical Engineering, University of Pavia, Italy 

3 Department of Innovation Engineering, University of Lecce, Italy 

ABSTRACT 

This paper presents a reconfigurable baseband DAC 

system (current-steering D/A + transimpedance stage + 

low-pass reconstruction filter) operating in a low-voltage 

multistandard transmitter, while satisfying high linearity 

requirements. The implemented block can process the 

WLAN 802.11a/b/g and the UMTS signals. The device 

has been integrated in a 0.13µm CMOS technology and 

operates with a 1.2V supply voltage. Experimental results 

show that the proposed circuit achieves a 29.5dBm OIP3 

when configured for the WLAN setting, and a 31dBm 

OIP3 when configured for the UMTS setting. The current 

consumption, optimized for the two cases, is 

16.2mA/14mA for WLAN/UMTS, respectively. 


The design of analog blocks for wireless transceivers has 

always been focused on the power consumption 

minimization, which is an issue for portable devices. This, 

in conjunction with the diffusion of scaled-down 

technologies, leads to a progressive reduction of the 

supply voltage for mobile applications. However the use 

of low supply voltages implies also some drawbacks in the 

design of the analog blocks. These drawbacks mainly 

regard the limited achievable linearity performance and 

hence the reduced dynamic range. As a matter of fact, in 

the state-of-the-art literature [1], a supply voltage as low 

as 1.2V is actually never used in wireless transceivers, and 

an high linearity requirement represents a challenging 

bottleneck in particular for the baseband analog blocks. 

Another challenge in the present market of wireless 

systems is represented by the implementation of blocks 

able to change operation mode, exploiting the same 

circuitry. This feature allows the devices to meet the 

specifications of different standards, thus satisfying the 

growing demand of reconfigurable mobile terminals. 

In these fields of research, the aim of the presented work 

has been the realization of a 1.2V low-distortion DAC 

system to be embedded in a wireless transmitter, able to 

fulfil the requirements of the WLANs and UMTS 

standards. The proposed block has been fabricated in a 

0.13µm CMOS technology and is realized with a 

current-steering DAC followed by a transimpedance stage 

and a low-pass reconstruction filter. The filter bandwidth 

can be digitally programmed (11MHz/2.5MHz), according 

25 

to the selected operation mode (WLAN/UMTS). In 

addition, also the DAC sampling frequency can be 

changed (100MHz/50MHz for WLAN/UMTS, 

respectively) to satisfy the different resolution 

requirements of the two standards. The use of the 

transimpedance stage, as well as a number of proper 

design choices, allow the device to achieve a high 

linearity performance even with a supply voltage as low 

as 1.2V. 

The paper is organized as follows. In paragraph 2 the 

design of the reconfigurable system and the features of the 

functional blocks are described. Paragraph 3 presents the 

experimental results. Finally in paragraph 4 conclusions 

are drawn. 

2. DAC SYSTEM DESIGN 

The fully-differential architecture of the implemented 

reconfigurable block is reported in Fig. 1. An 8 bit 

current-steering DAC, based on a fully-thermometric 

differential structure, is driven by the digital controls 

coming from the binary-to-thermometric decoder. The 

DAC output current is transformed into a voltage signal 

by a transimpedance stage, realized with an operational 

amplifier and two feedback resistors (a similar 

architecture is used in [2]). This signal represents the input 

for the following 4 th -order Bessel low-pass reconstruction 

filter which generates the smoothed analog waveform. 

Thanks to a digital control signal, the filter transfer 

function can be programmed in order to accommodate the 

two considered standards. 

In the following subsections the three functional blocks 

(DAC, transimpedance stage and filter) are described in 

detail. The design of these blocks has been oriented to 

maximize the linearity, while optimizing the power 

consumption. 

2.1 The 8 bit current-steering DAC 

As shown in Fig. 1 the implemented DAC is based on an 8 

bit current-steering differential architecture. A 

fully-thermometric structure has been chosen to reduce the 

effect of glitches and the DNL errors. This is paid with an 

increase in the digital area, which is anyway negligible 

due to the low number of bits.

Digital 

controls 

Bias 

(255/2) 


I unit 

1.2 V 

255 unit cells 

Current-steering DAC 

(255/2) I unit 

DACout+ 

DACout- 

= 5µΑ 

I unit 

The achievable resolution in the signal bandwidth 

(10MHz for the WLAN standard, 2.11MHz for the UMTS 

standard) is higher than 8 bits, since the DAC has been 

designed to operate at conversion frequencies (F s) up to 

few hundreds of MHz and consequently the oversampling 

ratio can be exploited. According to the selected standard 

(WLAN/UMTS), F s can be set to 100MHz/50MHz 

respectively, thus leading to a resolution of 9 bit in the 

WLAN bandwidth and 9.5 bit in the UMTS bandwidth 

(due only to quantization noise). The required in-band 

resolutions, which result from a behavioural analysis of 

the WLAN/UMTS TX chains developed in the frame of 

this activity [3], are equal to 8 bit and 9 bit for WLAN and 

UMTS, respectively. As a consequence, the chosen 

sampling frequencies determine in both cases a design 

margin to account for other noise contributions due to real 

implementation. 

In order to maximize the linearity performance all the 

sources of distortion which affect a current-steering D/A 

converter have been taken into account: output 

impedance, matching and glitches of the current sources. 

Usually, when high linearity performance is required, the 

cascode structure [4] is used to implement the DAC 

current sources. In this case the low supply voltage of 

1.2V does not allow the use of this structure since the 

margin for all the transistors to avoid the triode region 

would be too small. The distortion effect due to the finite 

output impedance of the sources is anyway made 

negligible by the transimpedance stage. In fact the virtual 

ground forced by the stage at the DAC output nodes 

makes the unit currents of the converter much more 

independent of the input signal, if compared to a solution 

in which the DAC output voltage swing is directly 

produced at the output nodes of the current cells. 

Behavioral analysis shows that a relative matching of 2% 

for each single current source is allowable to ensure an 

high DNL-INL yield with 0.5LSB as upper limit. The low 

supply voltage of 1.2V limits to 70mV the overdrive 

voltage of the DAC unit current cell. Consequently, using 

the Pelgrom model [5], a proper area for the unit source 

220 Ohm 

220 Ohm 

Transimpedance 

stage 

Figure 1. Architecture of the baseband block. 

26 

Digital bandwidth 

selector 

UMTS 

WLAN 

Low-pass filter 

V out+ 

V out- 

needs to be found to achieve the required matching. This 

area has been determined in 36µm 2 . Once the unit current 

has been fixed to 5µA as a trade-off between saving 

power and fitting the required conversion frequency, W 

and L of the unit source both result equal to 6µm. 

To limit the effect of glitches, which causes dynamic 

distortion, a reduced voltage swing is used to drive the 

switches of the various current sources (the two used 

reference voltages are 300mV and 800mV). Moreover, 

also the virtual ground forced by the transimpedance stage 

further reduces the energy of glitches, providing an 

improvement in the dynamic behavior of the DAC. Finally 

the switches are set to minimum dimensions to limit their 

charge injection. 

2.2 The transimpedance stage 

The transimpedance stage is placed after the DAC and 

drives the following smoothing filter. Considering the 

DAC output current fixed above, the value of the two 

feedback resistances (220Ω, as shown in Fig. 1) has been 

determined in order to obtain a differential peak-to-peak 

swing of 0.56V at the DAC output. These resistances have 

been accurately matched with the resistance used to 

generate the DAC reference current, in order to ensure an 

output swing as much as possible independent of the 

technology process spread. 

The opamp used in the stage is a fundamental block for 

the entire system performance. It has to be able to drive 

the low feedback resistances without introducing 

additional distortion on the signal. At the same time its 

current consumption needs to be minimized. This goal has 

been achieved with a proper choice of the opamp structure 

(shown in Fig. 2) and with a careful design. A two-stage 

topology has been used: a folded cascode input stage and 

a class AB output stage. The folded cascode input stage 

guarantees the necessary DC gain of 50dB to the entire 

opamp. The class AB output stage allows to drive the 

220Ω resistances, without an excessive current 

consumption. The implemented opamp reaches a

gain-bandwidth product of 150MHz, while the total 

current consumption is limited to 7mA. 

Figure 2. The opamp used in the transimpedance stage. 

2.3 The low-pass reconstruction filter 

The reconfigurable reconstruction filter is a 4 th -order 

Bessel low-pass structure consisting of the cascade of two 

identical active-RC biquadratic cells and with a DC gain 

of 8dB. A schematic representation of the complete 

architecture is shown in [6]. The cut-off frequency of the 

filter can be programmed according to the selected 

standard (11MHz for the WLANs, 2.5MHz for the 

UMTS), using a digital word which properly changes the 

value of the resistors. Furthermore a digitally controlled 

tuning circuit is used to allow a fine adjustment of the 

value of the filter capacitors. This compensates the effect 

of technology process spread and consequently ensures a 

good accuracy for the cut-off frequency. 

The output noise of the entire filter, dominated by the 

white thermal noise of the resistors, has been designed to 

be negligible with respect to the quantization noise 

introduced by the DAC. 

The filter current consumption has been optimized for the 

two cases (4.7mA for WLAN, 2.5mA for UMTS), since 

the bias currents of the filter opamps can be changed, 

according to the selected mode, in order to save power 

when a smaller bandwidth (UMTS case) is required. 

3. EXPERIMENTAL RESULTS 

The reconfigurable DAC system has been integrated in a 

standard 0.13µm CMOS technology. Fig. 3 shows the 

microphotograph of the test-chip, whose active area is 

0.9mm 2 . The device consumes 16.2mA (when configured 

for WLAN) or 14mA (when configured for UMTS), from 

a single 1.2V supply voltage. 

The static DNL and INL of the DAC have been firstly 

evaluated. They are shown in Fig. 4. The measured static 

linearity higher than 8 bits (INL max = 0.25LSB) confirms 

the effectiveness of the mismatch dimensioning and the 

minimization, due to the transimpedance stage, of the 

distortion effect of the current sources output impedance. 

The dynamic behaviour of the baseband block has been 

proved with single tone tests as well as intermodulation 


27 

tests, with the DAC conversion frequency set to 100MHz 

for the WLAN case and 50MHz for the UMTS case. 

Fig. 5 and Fig. 6 show the filter output spectrum when a 

full-scale single tone and two -6dBFS tones are applied at 

the input (the device is set for the WLAN operation mode, 

which is the most critical). The measured SFDR is 58dB, 

while the IMD3 is 59dB, leading to an OIP3 performance 

of 29.5dBm. No 1dBCP measurement can be extracted 

due to the highly linear behaviour of the device. Fig. 7 and 

Fig. 8 show the output spectra measured with typical 

WLAN 802.11a and UMTS signals, respectively. For both 

cases, the I component of a quadrature signal is 

considered. In the WLAN case the spectrum is compared 

with the emission mask (defined by the standard for the 

I+Q RF signal) to verify the out-of-band linearity. 

Table 1 summarizes the measured performance of the 

fabricated device. In spite of the low supply voltage used 

and the limited power consumption, the achieved linearity 

performance is remarkable and proves the effectiveness of 

the proposed design. Regarding the noise performance, in 

both cases the achieved dynamic range fulfils the 

resolution requirements. 


In this paper a low-voltage reconfigurable DAC system 

(current-steering DAC + transimpedance stage + low-pass 

reconstruction filter) for wireless transmitters has been 

presented. The implemented block is capable to process 

WLAN a/b/g and UMTS signals, thanks to a digital 

control which properly changes the filter transfer function. 

The device has been integrated in a 0.13µm CMOS 

technology and operates with a 1.2V supply voltage. The 

use of the transimpedance stage, in conjunction with 

proper design choices, allows the low-voltage block to 

achieve high linearity performance (full-scale SFDR of 

58dB, OIP3 of 29.5dBm, for the WLAN case). The 

current consumption is limited to 16.2mA/14mA for the 

WLAN/UMTS mode respectively. 

Figure 3. Chip microphotograph.

LSB units (8 bit) 

0.3 

0.25 

0.2 

0.15 

0.1 

0.05 

-0.05 

-0.1 

-0.15 

-0.2 

-0.25 

-0.3 

0 50 100 150 200 250 

DAC input code / DAC code transition 


0 

INL 

DNL 

Figure 4. DAC DNL-INL. 

Power Spectral Density (dBm) 

10 

0 

-10 

-20 

-30 

-40 

-50 

-60 

-70 

-80 

RBW = 10kHz 

-90 

0 1 2 3 4 5 6 7 8 9 10 

Frequency (MHz) 

Figure 5. Output spectrum with a 3MHz FS tone 

(WLAN setting). 

Power Spectral Density (dBm) 

10 

0 

-10 

-20 

-30 

-40 

-50 

-60 

-70 

-80 

RBW = 10 kHz 

-90 

1 1.5 2 2.5 3 

Frequency (MHz) 

3.5 4 4.5 5 

Figure 6: Output spectrum with two -6dBFS tones 

(WLAN setting). 

Power Spectral Density [dBr] 

0 

-10 

-20 

-30 

-40 

-50 

WLAN signal spectrum 

Transmit spectrum mask 

-60 

0 5 10 15 20 25 30 35 

Frequency [MHz] 

Figure 7: Output spectrum with a WLAN 802.11a input 

signal. 

28 

Power Spectral Density [dBr] 

0 

-10 

-20 

-30 

-40 

-50 

-60 

-70 

1 2 3 4 5 6 7 8 9 10 

Frequency [MHz] 

Figure 8. Output spectrum with an UMTS input signal. 

Table. 1. Block performance summary. 

Technology CMOS 0.13µm 

Supply voltage 1.2V 

Core area 0.9mm 2 

DAC DNL/INL ≤ 0.1LSB / ≤ 0.25LSB 

Standard WLAN UMTS 

Conversion 

frequency 

100MHz 50MHz 

Filter bandwidth 11MHz 2.5MHz 

Differential 

output swing 

1.4Vpp 

1.4Vpp 

DR (@FS) 52dB (8.3 bit) 56dB (9 bit) 

SFDR (@FS) 58dB (@ 3MHz) 60dB (@0.6MHz) 

OIP3 29.5dBm 31dBm 

Total current 

consumption 

16.2mA 14mA 

5. REFERENCES 

[1] Digest of Technical Papers of the 2004 and 2005 

IEEE International Solid-State Circuits Conference – 

Session 5: WLAN Transceivers. 

[2] D. Giotta et al., “Low-Power 14-bit Current Steering 

DAC, for ADSL2+/CO Applications in 0.13µm 

CMOS”, Proc. of ESSCIRC 2004, pp. 163-166, 

September 2004. 

[3] “Enabling technologies for wireless reconfigurable 

terminals”, Italian National Program FIRB, Contract 

n°RBNE01F582 – web-site http://ims.unipv.it/firb/. 

[4] M. Albiol et al., “Mismatch and dynamic modeling 

of current sources in current-steering CMOS D/A 

converters: an extended design procedure”, IEEE 

Trans. on Circuits and Systems, vol. 51, No. 1, pp. 

159-169, January 2004. 

[5] M. J. M. Pelgrom et al., “Matching properties of 

MOS transistor”, IEEE J. Solid-State Circuits, vol. 

24, pp. 1433-1439, Oct. 1989. 

[6] S. D’Amico et al., “Low-power reconfigurable 

baseband block for UMTS/WLAN transmitters”, 

Proc. of NORCHIP, pp. 103-106, November 2004.


ADAPTIVE MIXERS WITH A DISCRETELY AND 

A CONTINUOUSLY ADJUSTABLE 

PERFORMANCE SPACE 

Maja Vidojkovic, Johan van der Tang, Peter Baltus*, Arthur van Roermund 

Eindhoven University of Technology, E.H. 5.06, P.O.Box 513, 5600MB, Eindhoven, The 

Netherlands, *ASL Philips, Eindhoven, The Netherlands 

E-mail: m.vidojkovic@tue.nl 

ABSTRACT 

The demands for multi-standard, multi-band mobile 

handsets have motivated the development of analog frontends 

with flexible circuit topologies that can support a 

range of applications via adjustability and configurability. 

Accordingly, Gilbert cell mixers with a discretely and a 

continuously adjustable performance space are presented 

and analyzed. A discretely adjustable Gilbert cell is 

designed in CMOS 0.25um technology and a 

continuously adjustable Gilbert cell is implemented in the 

same technology. At 2.5GHz the following ranges of 

performance of the discretely adjustable Gilbert cell are 

obtained: a voltage gain from 15dB to –2dB, a NF from 

16dB to 9dB and an IIP3 from 11dBm to –8dBm. The 

performance is achieved for supply currents in the range 

from 1mA to 10mA. At 2.5GHz measured ranges of 

performance of the continuously adjustable Gilbert cell 

are: a voltage gain from 11dB to 7.5dB, a NF from 

15.2dB to 12.7dB and an IIP3 from 4.2dBm to 0dBm. 

The performance is measured by adapting the supply 

current in the range from 3.3mA to 4.1mA. The combine 

of both, continuous tuning and discrete tuning is a 

promising solution for coverage of a large desired 

specification space. 


The coexistence of all wireless technologies in one system 

and cheap and quick solution for new standards require 

multi-mode, multi-band and multi-standard mobile 

terminals. Hence, the demands for multi-standard mobile 

handsets have motivated the development of analog frontends 

with flexible circuit topologies that can support a 

range of applications via adjustability and configurability. 

The concept of adjustability makes only sense if the reuse 

count of the flexible circuits (how many times the circuit 

is used while having a minimum amount of design effort) 

justifies the investment. This in turn, is strongly related to 

the performance space (the set of specifications that can be 

covered with one circuit, which is a sub-set of the total 

design space) that can be covered by the adjustable circuit. 

This paper is organized as follows. In section 2 the 

performance space of the Gilbert cell, (see fig. 1), one of 

the most common mixer topologies is investigated. An 

optimization procedure for its design is given in [1]. The 

impact of discrete variation on the performance of this 

29 

topology is investigated. In section 3, as an example, a 

Gilbert cell mixer with an extended continuously 

adjustable performance space is presented. In section 4 the 

combination of both, continuous tuning and discrete 

tuning is recommended as a future work, as a promising 

solution to cover a desired specification space. Section 5 is 

reserved for the conclusions. 

Figure 1. The Gilbert cell 

2. A GILBERT CELL WITH A 

DISCRETELY ADJUSTABLE 


A Gilbert cell with a discretely adjustable performance 

space (see fig 2) is based on the Gilbert cell. The 

switching stage is the same stage as in the Gilbert cell. It is 

a cross-coupled differential pair that consists of the 

transistors M3, M4, M5 and M6. The load resistors and the 

transconductance stage are programmable. To facilitate 

the discrete adjustability the NMOS transistors Msw1, Msw2, … M swN and 

M , M , …, M ; and PMOS 

sw1 

sw2 

swN 

transistors MR1, MR2, … MRN and M , M , …, M 

R1 

R2 

RN 

operate as switches. The transistors M11, M12, …, M1N and 

M21, M22, … M2N implement the N differential pairs of the 

transconductance stage. So, the transconductance stage 

consists of N differential pairs which could be switch ON 

and OFF. With a different combination of the switches 

different transistor sizes can be achieved. Each 

combination of the differential pairs can be biased by one 

of different current sources Ibias1, Ibias2, … IbiasN. Hence, 

there are 2 N combinations of (differential pairi, Ibias,l), where i=1...N, l=1...N. For each group of (differential

pair i, I bias,l), i=1...N, l=1...N there is a pair of load resistors 

R G1 and R L1, R G2 and R L2, …, R GN and R LN. R G,i is a load 

resistance that gives the maximum voltage gain for a 

certain group (differential pair i, I bias,l), i, l=1...N; and R L,i is 

load resistance that gives the maximum linearity for the 

same group. The biasing voltages (V rfdc, V lodc) differ for a 

different combination of (differential pair i, I bias,l , R G,n and 

R L,n), where i, l, n =1…N. In such a way different set of 

specification can be achieved. 

Figure 2. The Gilbert cell with a discretely 

adjustable performance space 

The optimization procedure for the discretely adjustable 

Gilbert cell is similar as for the Gilbert cell. For a desired 

NF a certain combination of (differential pair i, I bias,l), 

i=1...N, l=1...N, is chosen. In addition for each 

combination of (differential pair i, I bias,l) the biasing 

voltages (V rfdc, V lodc) and the load resistor value (R) are 

adjusted in such a way that a maximum voltage gain is 

achieved. In this way the value of R G,l is determined. 

Then, the value of R L,l for which the maximum inputreferred 

IIP3 is achieved, is determined. 

Theoretically the number N can be unlimited. In practice it 

is limited and is a trade-off between the degradation of 

mixer performance and a desirable resolution of the 

adjustability. In order to estimate the performance 

degradation the impact of the MOSFET switches on the 

mixer performance has to be considered. 

Less impact of the switches on the voltage gain and the 

NF can be expected by decreasing the resistance value of 

Rsw,i of the transistor Msw,i when it is ON and increasing the 

Z impedances of M . An increased W/L ratio of 

sw, 

i 

sw, 

i 

the transistor Msw,i decreases Rsw,i when the transistor in 

ON, but introduces more parasitics and results in increased 

chip area. A smaller W/L ratio of the transistor M 

sw, 

i 

increases Z when the transistor is OFF, but increases 

sw, 

i 

R when the transistor is ON. However, a high value of 

sw, 

i 

does not influence the voltage gain and the NF since 

R 

sw, 

i 

it is not in the signal path. The resistance values of RR,i and 

R of the transistors M 

, R,i and M , respectively, when 

, 

R i 

they are ON can be neglected, since are in series with high 


R i 

30 

load resistance. Parasitic capacitance when the transistors 

are OFF can be also neglected since the output signal is 

the intermediate frequency (IF) signal at relatively low 

frequencies. 

Assuming a perfect square wave for local oscillator (LO) 

voltage and neglecting the impact of the switches, the 

voltage gain of this topology can be calculated as: 

N ⎛ 2 ⎛ ⎞⎞ 

G = 20log ⎜ R⎜∑ gmi 

⎟⎟ 

(1) 

⎝π ⎝ i= 

1 ⎠⎠ 

where g mi is the transconductance of M i when the 

transistor is ON, R is R Gi or R Li depend on the desired 

performance. Taking noise folding from the frequency f RF 

+f lo into account and neglecting the thermal noise of the 

switching stage and the flicker (1/f) noise, the NF of this 

topology can be approximated by: 

⎛ ⎞ 

⎜ ⎟ 

R 4γ 

π 

NF = 10log 2 + 2 + + 

N 

2 

⎜ sw, i 

⎟ 

⎜ ∑ 

N 

2 

N 

i 1 R 

⎟ 

= s ⎜ ( gmi) R ⎛ ⎞ 

s 2RRs 

g ⎟ 

⎜ ∑ ⎜∑mi⎟ i = 1 

⎟ 

i = 1 

⎝ ⎝ ⎠ ⎠ 

The total inter-modulation in the discretely adjustable 

Gilbert cell can be approximated in a similar way as the 

total inter-modulation in the Gilbert cell. The total intermodulation 

is approximately equal to the sum of the intermodulation 

values that the transconductance and the 

switching stage would generate if the other stage were 

ideal, [3]. Hence, in the case RL,l is ON, the intermodulation 

is limited by the transconductance stage. In the 

case RG,l is ON, a high voltage drop at the drain of the 

transistors in the switching stage will turn them in the 

triode region. Then the inter-modulation is determined by 

both the transconductance and the switching stage. 

In order to make a comparison between the fixed and the 

discretely adjustable Gilbert cell, both topologies are 

simulated, by using the circuit simulator SpectreRF in 

CMOS 0.25um technology. For this specific case the 

transconductance stage of discretely adjustable Gilbert cell 

consists of 3 differential pairs where M11 has 

W/L=50/0.25; M12 and M13 have W/L=100/0.25. M12 and 

M13 can be switch ON and OFF. The combinations of 

transistor sizes, Ibias and load resistors used in this example 

are presented in Table 1. The sizes of switches are: Msw,i has W/L=100/0.25, M has W/L=10/0.25, and M 

, R,i and 

sw i 

M have W/L=100/0.25. The fixed Gilbert cell is 

R, 

i 

simulated separately for each combination. 

Increasing Ibias (more than 10mA) improves only slightly 

the NF while the power dissipation is very high. Further 

decrease of the transistor size (less than 50um) brings the 

transistors out of saturation for Ibias=10mA. Further 

increase of the transistor sizes (more than 250um) 

improves slightly the voltage gain and the NF while 

parasitics degrade circuit performances at higher 

frequencies. Increasing RGi does not improve the voltage 

gain any more. A lower value of RLi improves slightly the 

IIP3. 

(2)

Table 1. The chosen combinations for the 

discretely adjustable Gilbert cell 

transistor 

sizes 

Ibias=1mA 

Ibias=5mA 

Ibias=10mA 

M11 

50um 

RG1 =2.5K 

RL1 =2K 

RG2 =550 

RL2 =350 

RG3 ’ =180 

RL3 =100 


M11 and M12 

150um 

RG1 =2.5K 

RL1 =2K 

RG2 =550 

RL2 =350 

RG3 =250 

RL3 =100 

M11, M12, M13 

250um 

RG1 =2.5K 

RL1 =2K 

RG2 =550 

RL2 =350 

RG3 =250 

RL3 =100 

The simulated ranges for the voltage gain, the NF (the 

SSB NF is simulated at a 50Ω source impedance) and the 

IIP3 of the fixed Gilbert cell and the discretely adjustable 

Gilbert cell are given in Table 2. 

Table 2. Simulation results at 2.5GHz 

Fixed 

Gilbert cell 

Discretely 

adjustable 

Gilbert cell 

Gain [dB] NF [dB] IIP3 [dBm] 

Max =16 

Min =-2 

Max =15 

Min=-2 

Max =14 

Min=7 

Max =16 

Min=9 

Max=12 

Min =-8 

Max =11 

Min=-8 

From the obtained results the following can be concluded. 

Significant flexibility is achieved. Moreover, emerging 

standards can easily fit in predesigned discretely 

adjustable topologies, and hence, products are ready very 

quickly on the market. The price paid for programmability 

and adjustability is degradation of the circuit performance 

due to the parasitic capacitances and the resistance value 

of the switches biased in the triode region when it is ON. 

This is especially case when the number N is higher and at 

higher frequencies. 

3. A GILBERT CELL WITH A 

CONTINUOUSLY ADJUSTABLE 


A continuously adjustable Gilbert cell (see fig 3) is also 

based on the Gilbert cell mixer. The switching stage is the 

same stage as in the Gilbert cell. It is a cross-coupled 

differential pair that consists of the transistors M 3, M 4, M 5 

and M 6. The transconductance stage in the continuously 

adjustable topology differs from the transcoductance stage 

in the fixed Gilbert topology. It consists of two differential 

pairs. One of the differential pairs consists of transistors 

M 1 and M 2, and it is referred to as the fixed differential 

pair. It is biased by the current source I bias1, as in the 

Gilbert cell. The other differential stage consists of the 

transistors M 11 and M 22, and it is called the cross-coupled 

differential pair. It is biased by the current source I bias2. 

The optimisation procedure of the continuously adjustable 

Gilbert cell is the same as for the fixed topologies. In the 

case I bias2 is zero, the adjustable Gilbert cell behaves as a 

conventional Gilbert cell. In the case I bias2 is non-zero, the 

optimisation technique is the following. The biasing 

voltages (V rfdc, V lodc), sizes of all transistors, and the load 

resistor value (R) are adjusted such that all transistors are 

31 

in saturation. The next step is to optimize the switching 

and the fixed differential stage for a high gain and a low 

noise contribution. The cross-coupled differential stage is 

optimised to improve the linearity. By changing I bias1 and 

I bias2 currents, different values for the conversion gain, the 

noise figure and the linearity can be achieved. 

Figure 3: The continuously adjustable Gilbert cell 

Assuming a perfect square wave for local oscillator (LO) 

voltage, the voltage gain of the adjustable Gilbert topology 

can be approximated as: 

⎛ 2 

⎞ 

G = 20log ⎜ R( gm1−gm2) ⎟ 

⎝π⎠ (3) 

where g m1 is the transconductance of M 1 and M 2 and g m2 is 

the tranconductance of M 11 and M 22. 

Taking noise folding from the frequency fRF +flo into 

account the NF of the adjustable mixer can be 

approximated by: 

⎛ 2 

4γ 

( gm1 + gm2) 

π ⎞ (4) 

NF = 10log ⎜2+ + 

⎟ 

2 

2 

⎜ ( g − g ) R 2RR 

( g − g ) ⎟ 

⎝ m1 m2 s s m1 m2 

⎠ 

In order to analytically estimate the inter-modulation the 

drain current is modeled by, [3]: 

( gs T ) 

I = f V − V = K 

1 

2 

( Vgs −VT) 

+ θ ( Vgs −VT) 

(Vgs-Vt) is the overdrive voltage of a transistor, coefficient 

θ models the source series resistance, mobility degradation 

because of the vertical field, and short-channel effects 

such as velocity saturation. For a 0.25-um CMOS 

technology θ =2.5 V -1 , approximately [3]. K is expanded 

as K = µ Cox 

W / L . The output current from the 

transconductance stage can be described as a Taylor series 

polynomial expression of the input voltage vgs: 2 

3 

( a − b ) v + ( a − b ) v + ( a − b ) v + ... 

(5) 

i = i1 

− i2 

= 1 1 gs 2 2 gs 3 3 gs (6) 

where a 1=dI bias1/dV gs1,a 2=d 2 I bias1/dV gs1 2 ,a3=d 3 I bias1/dV gs1 3 , 

b 1=dI bias2/dV gs2, b 2=d 2 I bias2/dV gs2 2 , b3=d 3 I bias2/dV gs2 3 , (Vgs1- 

V t) is the overdrive voltage of the transistor M 1 and M 2, 

and (V gs2-V t) is the overdrive voltage of the transistor M 11 

and M 22. In order to cancel the third order distortion

products, each stage should be designed such that a 3 = b3 

, 

[2]. For a 3 = b3 

the following relation is estimated: 

1 ⎛ W ⎞ d2 Wd2 

Vgs2 −Vt ≈ ⎜ 4 1 4 ( Vgs1 Vt) 

θ ⎜ 

− ⎟ 

W ⎟ 

+ − (7) 

⎝ d1 ⎠ Wd1 

where Wd1 is the width of M1 and M2, and Wd2 is the width 

of M11 and M22. For this specific design the target is a 

maximum adjustability over a certain range and not 

design for the point of “ideal” inter-modulation 

cancellation. 

G,NF[dB] 

15 

13 

11 

9 

7 


G[dB] G[dB] 

NF[dB] NF[dB] 

IIP3[dBm] IIP3[dBm] 

0 0.2 0.4 0.6 0.8 

Ibias2[mA] 

Figure 4: Measured and simulated results 

6 

4 

2 

0 

IIP3[dBm] 

The input signal is set to 2.5GHz, while the output signal 

is measured at an IF of 2MHz. A SSB NF is measured at a 

50Ω source resistance. The differential LO voltage swing 

is V lo=500mVp, the supply voltage is 2.5V, I bias1=3.3mA, 

R=500Ω, L d1=L d2=L s=0.25um (L d1 is length of M 1 and M 2; 

L d2 is length of M 11 and M 22) W d1=100um, W d2=40um, 

W s=80um (W s and L s are width and length of M 3, M 4, M 5 

and M 6). 

Figure 5: Die micrograph of the adjustable 

Gilbert cell 

The measured (solid line) and simulated (dashed line) 

results are presented in fig. 4. By increasing I bias2 the 

voltage gain will decrease, the NF will increase and the 

linearity first will increase due to cancellation of third 

order distortion products. In the case of further increase of 

I bias2 the linearity will decrease. There are two reasons for 

this. The first reason is that in the case of further increase 

of I bias2 cancellation of the third derivatives (a 3- b 3) of the 

I-V curve becomes constant, [3] and the first derivatives 

32 

(a1- b1) cancel each other further (IIP3~(a1- b1)/ (a3- b3)). The second reason is that an increase of the total bias 

current will increase the voltage drop at the drain of the 

transistors in the switching stage. This will bring the 

switching transistors into the triode region. 

The die photo of the realized adjustable Gilbert cell is 

shown in fig. 5. The active chip area is 180um х 210um. 

The fixed Gilbert cell (fig. 1) was also realized. For the 

same design parameters (as the continuously adjustable 

Gilbert cell) and Ibias1=3.3mA a voltage gain of 13dB, a 

NF of 12dB and an IIP3of 1dBm are obtained. 

4. COMBINED METHOD TO VARY 

TOPOLOGY PERFORMANCE 

Based on the achieved results some general 

recommendations, which are important for choosing 

methods to vary a topology performance, can be proposed. 

Values of design parameters can be tuned continuously 

(analog tuning). Alternatively, a value of each design 

parameter can be tuned discretely by switching between 

different values (digital tuning). The trends from the 

achieved results show, that by increasing the number of 

switches in discrete tuning topology performance is 

degraded. There are some limitations in achieving a wider 

continuous tuning range because topology performance is 

also degraded by increasing the tuning range. Combination 

of both, continuous tuning and discrete tuning are a 

promising solution to cover all points of interest of the 

overall specification space of a certain topology. 

5. CONCLUSION 

Gilbert cell mixers with a discretely and a continuously 

adjustable performance space are presented and analyzed. 

A particular test circuit of a discretely adjustable Gilbert 

cell is designed in CMOS 0.25um technology and a 

particular test circuit of a continuously adjustable Gilbert 

cell is implemented in the same technology. Combination 

of both, continuous tuning and discrete tuning is expected 

to be a good solution to cover the desired specification 

space of a certain topology with the small performance 

degradation. 

6. REFERENCES 

[1] V.Vidojkovic, et.al., “Mixer Topology Selection for a Multi 

– Standard High Image – Reject Front – End”, IEEE, May 

2003. 

[2] T.P.Weldon, “New Method for Amplifier Linearization”, 

University of North Carolina at Charlotte, 2002. 

[3] M.T.Terrovitis and R.G.Meyer, “ Intermodulation 

Distortion in Current – Commutating CMOS Mixers”, IEEE 

Journal of Solid-State Circuits, vol. 35, no. 10, October 

2000.


A 1.5V 8-BIT LOW-POWER SELF- 

CALIBRATING HIGH-SPEED FOLDING ADC 

ABSTRACT 

An 8-bit High-speed folding/interpolating ADC is 

presented. Designed in 0.18μm CMOS technology, the 

ADC dissipates only 50mW from a single 1.5V supply. A 

novel technique based on using both N and P folding cells 

is used to widen the input range and a self-calibration 

technique based on using Trimmable MOSFETs is 

employed to improve the static and dynamic performance. 


Among different ADC structures, flash and folding are 

among the first choices for high speed applications. 

Although the flash architecture has been used in the 

highest speed ADCs, its severe disadvantage of requiring 

2 N -1 comparators for N bits of resolution has limited 

practical flash ADC resolutions to less than 8 bit. Folding 

structure effectively reduces the number of comparators 

by adding an analog-pre-processing stage before the 

comparators. However, folding structure is sensitive to 

mismatch between elements (i.e. voltage and current 

offsets). Although the mismatch performance can be 

improved by using techniques such as averaging and 

interpolating, still large MOSFET device sizes are 

required to maintain reasonable offsets which in turn 

degrade the maximum sampling frequency. As a result, 

considerable power must be consumed to satisfy both the 

static and dynamic performance in classic folding ADCs. 

Another challenge in designing folding ADC in scaled 

CMOS processes is the reduction of the power supply 

voltage which reduces input range and voltage efficiency 

(i.e. the ratio of the input voltage range to the supply 

voltage). As voltage efficiency affects many of the design 

parameters (matching considerations, input capacitance, 

power dissipation, etc) [1], narrowing the input range 

would result in more complex design process. The 

restriction is more severe when the supply voltage is less 

than the nominal value of the technology (as is the case in 

our design). 

Nevertheless, the number of reported low-voltage folding 

ADC’s is increasing [2,3,4]. The mismatch induced errors 

are usually reduced by using averaging and interpolating 

Hamid Movahedian,Mehrdad Sharif Bakhtiar 

Electrical Engineering Department 

Sharif University of Technology 

Tehran, IRAN 

Email: movahedian@sharif.ir 

33 

and/or self-calibration. The effects of reduced power 

supply on static and dynamic behaviour are generally 

compensated at the cost of increasing power dissipation. 

Considering the energy per conversion step as a figure of 

merit [2]: 

F=E/convstep=Power/(2 ENOB x F s) (1) 

For all the referred cases, F is more than 2.8pJ. As power 

consumption is an important parameter especially from 

industrial point of view, it would be very attractive to 

convey methods for using the advantages of folding 

architecture without sacrificing power and/or chip area. 

The folding ADC proposed in this paper utilizes two novel 

techniques, one for increasing voltage efficiency, and the 

other for self-calibration and compensation for static 

mismatch. By using these techniques, both the dynamic 

and static performance will be improved without any need 

to increase the power. Simulation results show energy per 

conversion step of less than 1.4pJ. 

2. IMPROVEMENT TECHNIQUES 

2.1 Widening Usable Input Voltage Range 

The main building block of every folding amplifier is a 

folding cell which consists of one or two differential 

pair(s). The technique used to increase the usable input 

range is based on the use of both N and P differential pairs 

as preamplifiers and folding amplifiers[5]. In other words, 

the lower part of the input range is covered by P 

differential pairs while the upper part is covered by N 

differential pairs. In this way, the input range can be 

virtually extended from both ends to supply limits (0 and 

Vdd ). The usable input range, however, would be lower if 

extra folders are used to allow interpolation at the ends of 

the input range and also for dc balance. For example, to 

have a Folding Factor of 8, using 11 folding amplifiers is 

a practical choice [6]. For such an architecture, the input 

signal range would be 8/ 11 × 1. 5 ≈ 1. 1V 

for a 1.5V 

supply voltage.

Vi 

P-Folding Cell 1 P- Folding Cell 5 

Vref 

Vref 

Iss 1 

Iss 

5 

Iss 

Vref 

6 

Iss 

N-Folding Cell 1 N-Folding Cell 6 


Vref 

11 

Vb1 

Vb2 

+Vout- 

Figure 1. Wide Input Range Folding Block 

The output currents of P-folders and N-folders are 

summed up before being converted to voltages in active 

loads. Fig. 1 shows the proposed structure. 

As the summing node of the output currents is divided to 

two nodes in this structure, the total capacitance hanging 

from each node is reduced to about one half of the former 

case. In this way, the summing nodes have potentially 

higher bandwidths. 

As it can be seen in Fig.1, there are two folding cells for 

which one of the neighboring folders is N-type while the 

other is P-type. As the characteristic curves of N and P 

folding amplifiers are not matched, the overall 

characteristic curve will be distorted at the interface 

between two subfolders. In order to compensate for the 

mismatch between characteristic curves of N- and Pfolding 

cells, the gain of N-preamplifiers are adjusted such 

that the two types of folding blocks have the same 

characteristic curve. This is done in an additional circuitry 

consisting of replicas of an N- and a P-folding cell and an 

op-amp to adjust the bias of tail current source of the Nfolding 

preamplifier (Fig.2). The input values of the 

replica folding cells are selected from the reference 

voltages in such a way that the gains are equalized at the 

region between N and P sub-ranges. The same bias 

voltage is applied to the tail current sources of all the Npreamplifiers. 

Vref M+1 

Vref M-1 

Vref M 

Vref M 

Figure 2. Equalizing gain of N- and P-folding 

cells 

34 

2.2 Self-Calibration 

Considering the major sources of mismatch as 

independent random variables, their effect in term of 

mean-squared values can be mathematically expressed as 

parts of an input referred offset. The effect of such an 

input offset can be cancelled out by introducing a 

“programmable input offset”. In Continuous time offsetcancellation 

techniques, the input offset is sampled on a 

capacitor before signal sampling and is subtracted from 

signal during normal sampling phase[7]. This technique, 

however, limits the sampling frequency as the calibration 

process must be repeated before each sampling. Static or 

start-up calibration, on the other hand, can improve the 

dynamic behavior. In [4], current DAC’s are used to 

subtract the measured offset from the signal at the output 

of the preamplifiers. This has led to a considerable 

improvement in both the static and dynamic behavior, but 

at the cost of increasing power and chip area. 

As a classic differential amplifier with resistive loads 

(R D), the input referred offset of the preamplifier is: 

( V −V ) ΔR Δ( 

W / L) 

GS th D 

V = ( + ) − Δ V (2) 

off th 

2 R W / L 

D 

Δ ( W / L) 

in Eq. (5) can be adjusted using “Trimmable 

MOSFET” as a part of one of the input transistors of the 

folding cells. The trimmable MOSFET consists of a 

number of switchable paralleled transistors with different 

(W/L)’s and acts as a programmable W/L transistor. It’s 

usually used for trimming binary weighted current sources 

in DACs [8]. 

With proper weighting of (W/L) M1…(W/L) Mn, the 

preamplifier containing trimmable MOSFET('s) acts as a 

D/A which converts an n-bit digital word to a 

programmable input offset which can cancel out the 

mismatch induced offset. An n-bit latch is used to store 

the proper digital word. 

Fig.3 shows a 4-bit digital-to-offset converter used as 

preamplifier in N-folding cells (similar structure with Ptransistors 

is used for P-folding cells). To maintain 

dynamic matching, another trimmable MOSFET (with 

fixed code) is used for the other input transistor. 

Vref M0 

4-bit 

Latch 

M 1 M 2 M 4 

Figure 3. 4-bit Digital-to-Offset Converter 

Vin

The next step is devising a procedure for offset 

cancellation. Noting that the ultimate goal of offset 

cancellation procedure is reaching the situation: 

VIN= Vref ⇒ VOUT 

= 0 

(3) 


i 

This procedure will be quite straightforward: 

1-The two inputs of the each folding cell (V IN and V refi) are 

connected to maintain the condition VIN=Vrefi . 

2-The programmable offset is set to its most negative 

value. This value must be selected to be higher in 

magnitude than the highest expected value of the 

mismatch induced offset. 

3-The programmable offset is incremented in 

(1/2 n ).V FullScale steps as long as the output reaches zero (i.e. 

the output of the comparator toggles) 

4- The last value of the n-bit digital word is stored in the 

latch and the inputs are disconnected. It must be noted that 

the number of bits is chosen to achieve the maximum 

allowable INL. 

The same procedure will be repeated for every folding cell 

of each folding block. As this technique compensates the 

static offsets, it will be sufficient to perform it once if the 

latches are non-volatile memories or once per power up if 

the latches are volatile. For the latter case, it takes less 

than a millisecond after each power up to perform selfcalibration 

for the whole ADC. 

Fig.4 shows the block diagram of the offset cancellation 

system . 

Using the self-calibration technique has an obvious effect 

on the reduction of the overall chip area because the added 

logic circuitry occupies negligible area compared to the 

large transistors needed to satisfy the same static 

performance without calibration. In this case, the overall 

chip area was reduced to about 0.6mm 2 

V IN 

Folding 

Cell n 

N-bit 

Latch 

Vref n 

N-bit Bus 

CLK 

+V OUT 

Enable 

Figure4. Offset Cancellation circuit 

Output 

35 

Vout (V) 

0.6 

0.4 

0.2 

V IN 

0 

-0.2 

-0.4 

FOLDING 

BLOCK 1 

FOLDING 

BLOCK 2 

FOLDING 

BLOCK 3 

FOLDING 

BLOCK 4 

8x INTERPOLATOR 

32 

32 COMPARATORS 

COARSE 

ADC 

32 8 

SYNCH AND ENCODER 

Figure 5. Block Diagram of the 8-Bit 

Folding/Interpolating ADC 

USABLE RANGE 

DATA OUT 

8 

-0.6 

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5 

Vin (V) 

Figure6. Folding waveforms 

3. ADC ARCHITECTURE 

The block diagram of designed ADC is shown in Fig.5. It 

consists of 4 self-calibrated complimentary folding blocks, 

resistive interpolating networks, 32 fine comparators, a 

digital encoder and a coarse ADC block. The entire input 

range of (0 – 1.5V) was folded 11 times, among them 8 

(0.15 V

VON 

VIP 

M1 

CLK M7 M5 

M6 M8 CLK 


M10 

Vdd 

CLK 

M2 

Vb 

M3 M4 M 9 

Figure 7. Improved Comparator 

VIN 

VOP 

- Instead of tying output nodes to ground, they were 

shorted in the preamplification phase. In this way, these 

transistors can start the regeneration process shortly after 

the falling edge of the clock, resulting in lower dynamic 

offset. 

4. SIMULATION RESULTS 

Fig.8 shows the simulated INL based on the Monte Carlo 

simulation of the ADC with and without self-calibration. 

Dynamic simulation of the designed ADC shows that the 

sampling frequency can be increased to 300Msample/sec. 

In this sampling rate, however, ENOB drops to 7 bits at 

nyquist rate. The total power consumption is about 

50mW, including reference ladder power and static and 

dynamic power consumption of the ADC (excluding T&H 

circuit). Table.1 shows the summary of the simulation 

results in comparison with state of the art folding ADC’s . 

INL 

1.5 

1 

0.5 

0.2 

0 

-0.2 

-0.5 

-1 

INL 

Calibrated 

-1.5 

0 32 64 96 128 160 192 224 256 

Code 

Uncalibrated 

Figure 8. Simulated INL with and without selfcalibration 

36 

Table. 1. Comparison with the state of the art. 

This Work [1] [2] [3] 

Technology 0.18um 0.12um 0.18um 0.18um 

Vdd 1.5V 1.2V 1.8V 1.8V 

Fs, Nyquist 300 MHz 

100 MHz 

400 MHz 

800 MHz 

ENOB 7bit 8.83b 7.5 7.26 

INL 0.4 LSB 

Power 50 mW 

? 0.8 LSB 

140 mW 


A 4GSa/s 7-BIT TWO-WAY TIME-INTERLEAVED 

BIPOLAR TRACK-AND-HOLD AMPLIFIER 

BASED ON A NOVEL ANALOG SWITCH 

Burak Çatlı 1,2 , Fidel Bayam 1,2 , Bilal Tarık Çavuş 1 , Asım Kepkep, Ali Zeki 1 

1 Istanbul Technical University, Faculty of Electrical and Electronics Eng., 

Electronics and Communications Eng. Dept., 34469 Maslak, Istanbul, Turkey 

2 ETA-IC Design Center, KOSGEB Binasi, A Blok, 34469 Maslak, Istanbul, Turkey 

E-mail: catli@ehb.itu.edu.tr 

ABSTRACT 

Based on a novel analog switch, a two-way timeinterleaved 

bipolar track-and hold amplifier is proposed, 

achieving 7-bit resolution at 4GSa/s sampling rate. 


Ever increasing demand for broadband applications, such 

as optical communications, wideband radar and highspeed 

instrumentation, has made high-speed ADCs a 

crucial element. The performance, particularly the speed 

of such ADCs is mainly limited by the track and hold 

(TH) amplifier, thus it is a critical component. 

When, the sampling rate of an ADC is limited by the 

speed of the TH amplifier, the high-speed conversion 

demand can be relaxed by applying time-interleaving to 

multiple copies of the ADC. Main disadvantages of a 

time-interleaved ADC are high power dissipation and 

large area occupation due to repetition of sub-ADCs with 

all blocks (TH amplifier, comparator array, decoder, etc.). 

To overcome the TH bottleneck with a simpler 

architecture “time-interleaved TH amplifier” technique is 

proposed. This technique limits parallelization in TH 

block. Then, only a single copy of the remaining blocks 

(comparator array, decoder, etc.) is required, thus the 

excess power and area consumption drawbacks are 

apparently eliminated. Few examples of this approach 

have been reported [1-3]. Among these, only one can 

achieve the high-speed requirements of a broad-band 

system, but with a 16-way structure, mandating a 

complicated analog multiplexing circuitry and a 16-phase 

clock generation [3]. In this paper, based on a novel 

analog switch (ASW), a 4GSa/s two-way time-interleaved 

TH amplifier is proposed, employing two 2GSa/s TH 

amplifiers. 

2. TRACK-AND-HOLD SYSTEM 

2.1 Proposed circuit 

The block diagram of the proposed circuit is shown in 

Fig.1. The two TH amplifiers (TH-1 and TH-2) at the 

input are clocked to sample the input signal, similar to TH 

amplifiers in a two-way time interleaved ADC. The analog 

37 

switches (ASW-1 and ASW-2), controlled by opposite 

clock signals (clk-t and clk-h), perform “analog 

multiplexing” to combine the sampled signals at the 

output, to obtain an effective sampling rate of 4GSa/s. The 

proposed circuit, whose timing diagram is shown in Fig.2, 

operates as follows: During the first time interval, t1-t2, 

TH-1 is in hold mode and the held differential signal at its 

outputs (out+, out-) is transferred to the output nodes of 

the circuit (out-p, out-n) via the analog switches ASW-1 

and ASW-2 (for both, sel1=“1” and sel2=“0”). During the 

same interval, TH-2 is in track mode but its output is 

isolated from the output nodes of the circuit. At time t2, 

the hold period of TH-1 is over and the ASWs disconnect 

the output of TH-1 from the output nodes of the circuit. 

The interval t2-t3 is the hold period for TH-2, during 

which sel2=“1” and sel1=“0” for both switches, such that 

the held differential output signal of TH-2 is connected to 

the output nodes of the circuit. Thus, the ASWs combine 

two 2GSa/s sampled signals at the output to yield a 

4GSa/s sampled signal. 

Figure 1. The complete track-and-hold system. 

2.2 Analog switch 

An ASW can be thought as two emitter followers (EFs), 

activated alternately by clock signals to drive their 

common output node. An EF can be deactivated by 

pulling down its DC base voltage to a low level; in this 

case the other EF is activated. A problem is the transient 

base current observed at the beginning of activation of an 

EF, which reduces the usable hold period of the output 

signal of the preceding TH amplifier.

Figure 2. Timing diagram of complete TH system. 

The complete schematic of the proposed analog switch, 

shown in Fig.3, has some differences with respect to the 

simple ASW explained above. To limit the transient base 

currents during activation, a simple darlington pair is used. 

This reduces the emitter currents of Q1 and Q2 (when ON) 

considerably, degrading operation. Therefore, resistive 

paths (R1 and R2) are added from the emitters of Q1 and 

Q2 to the current source I1. QS1 and QS2 (driven by 

opposite clock signals) are used to activate/ deactivate the 

darlington stages. When sel1=“1”, QS1 directs I2 to the 

base of Q1, to pull down this node with help of output 

buffer resistor of TH-1. Thus, Q1 is driven OFF, cutting 

off the path of Q3 and R1. Consequently, the other 

darlington stage (Q2-Q4-R2-I1) is activated. Similarly, 

when sel2=“1”, QS2 is ON to activate the stage Q1-Q3- 

R1-I1, while the other is OFF. 

Figure 3. The complete schematic of analog switch. 

Although pulling down/releasing the bases of Q1 and Q2 

for deactivation/activation is similar to the method in a 

switched emitter follower (SEF) of a TH amplifier, the 

proposed ASW is functionally different in two ways: i) 

When ASW is to pass a signal (say “in1”) to its output, 

this signal is an almost constant voltage, already held by 

the preceding TH during this period (hold period of TH-1). 

Conversely, SEF of a TH is ON during the track mode and 

has to keep up with a slewing signal to perform proper 


38 

tracking. ii) When ASW is to block a signal (say “in1”), it 

isolates its output node from this signal (output of TH-1, 

which is in track mode), but unlike the SEF, does not 

perform sampling. Actually, unlike a SEF, when one half 

of ASW is OFF, its output signal is not a voltage held on 

a floating capacitor, but a voltage dictated by the other 

half of the ASW. Therefore, signal feedthrough across the 

deactivated part is apparently lower. 

2.3 Simulation results and discussion 

The circuit was implemented in a 0.35µm BiCMOS 

technology with f T=30 GHz and simulated with Spectre. 

Design of TH-1 and TH-2 were based on the TH amplifier 

in [4]. The supply voltage is 3.3V and complete system 

consumes 120mW. The differential full-scale analog input 

voltage is 400mV p-p. The hold capaticance of TH 

amplifiers is 200fF. Fig.4 shows the ENOB curves versus 

input signal frequency for a single TH (sampled at 

4GSa/s) and the two-way complete TH (4GSa/s effective 

sampling), revealing the advantage of the time-interleaved 

TH, especially for f>1GHz. Fig.5 shows the differential 

output signals for a 450MHz full-scale sine-wave input. 

Figure 4. ENOB plots for single and two-way TH. 

Figure 5. Outputs of the THs and the system. 

3. CONCLUSION 

The proposed two-way time-interleaved TH is based on a 

novel analog switch. The ASW realizes a simpler function 

and its speed and signal feedthrough problems are

apparently relaxed with respect to that of a SEF, thus the 

optimization space for the ASW is wider. The complete 

system provides an ENOB 2 bits higher than that of a 

single TH operating at the same sampling rate. 


4. REFERENCES 

[1] K. Nagaraj, et al., “A dual-mode 700-Msample/s 6bit 

200-Msamples/s 7-bit A/D converter in a 0.25µm 

digital CMOS process,” IEEE J.Solid-State Circuits, 

vol. 35, pp. 1760-1768, 2000. 

[2] T. Reimann, et.al., “A high-speed BiCMOS 

switched-current track-and-hold circuit,” Proc. of 

Custom Integrated Circuit Conf., pp.377-380, 1998. 

[3] S. M. Louwsma, et al., “A 1.6 GS/s, 16 times 

interleaved track & hold with 7.6 ENOB in CMOS,” 

Proc. of ESSCIRC '04, pp. 343-346, 2004. 

[4] A. N. Karanicolas, “A 2.7-V 300-MS/s track-andhold 

amplifier,” IEEE J.Solid-State Circuits, vol. 32, 

pp. 1961-1967, 1997. 

39


A SIGMA-DELTA ADC DESIGN AUTOMATION 

TOOL 

Selçuk Talay, Günhan Dündar 

Boğaziçi University, Department of Electrical and Electronics Engineering 

Bebek, 34342 Istanbul, Turkey 

E-mail: talays@boun.edu.tr, dundar@boun.edu.tr 

ABSTRACT 

A design automation system for Sigma-Delta analog-todigital 

converters (ADC) which operates at system level 

is presented. New error models and a new approach to 

system level design exploration and/or automation are 

illustrated. Finally, verification of the approach on a chip 

design is presented. 


This work presents a design automation system developed 

for Sigma-Delta (SD) ADC’s. There are various 

applications, especially wireless communication systems, 

which require specific ADC designs. The specifications 

for these circuits may vary in many different dimensions 

such as resolution, conversion rate, power, etc. It is a 

challenging task to identify the most appropriate structure 

for a designer. There are some tools previously developed 

[1] which help the designer in different aspects. Most of 

these tools aim to complete the design for specific ADC 

structure and even with specific transistor level circuits. 

These tools may give adequate solutions for some specific 

implementations since they only utilize fixed ADC 

architectures. Also, designers do not want to use 

“blackbox” design automation systems and rather prefer 

more user interaction. This work satisfies the needs of an 

ADC designer regarding user interaction, flexibility and 

type of interaction that designer may select through the 

design process. Also, equation database that the tool uses 

has improvements over some previously developed 

models. The aim throughout this work has been to develop 

a SD ADC design automation tool which can be merged 

into the analog design automation (ADA) system 

described in [2] at system level. 

2. SIGMA-DELTA ADC DESIGN 

AUTOMATION 

2.1 Modeling approach 

There are two common approaches for SD modulator 

modeling. The first approach utilizes dedicated behavioral 

simulators for parameter optimization [3], while the initial 

architecture selection is performed by limiting the design 

space in a coarse manner by using simple SNR equations 

that do not contain any non-linearities. In order to obtain 

accurate performance information, extensive and time 

consuming simulations should be performed. 

40 

The other approach is to estimate the performance of the 

system by using analytical expressions [4]. Then, 

behavioral simulations on the analytical expressions 

themselves can be performed in order to validate the 

design. This approach is faster than the previous one but 

expressions should be accurate enough to reflect the real 

circuit. Faster simulation times allow a more thorough 

exploration of the design space. Furthermore, analytical 

expressions provide insight into the design, thus helping 

the designer to evaluate the tradeoffs better. 

In our work, the second approach was chosen. Equations 

describing the behavior of the SD ADC under various 

non-idealities were developed and performance estimation 

was performed without behavioral simulations. 

2.2 Equation database 

The database contains many equations, which model the 

effects of non-idealities by calculating their contribution to 

the total noise. Then, the algorithm developed, as shown 

briefly in Figure 1, calculates the dynamic range (DR) 

achievable by the design and other device level parameters 

for the given specifications. The equation database has 

various models for noise sources in SD ADC’s such as 

quantization noise, thermal noise, noise from switches, 

jitter noise, slew-rate effect [5]. The equation database is 

utilized by the algorithm at different stages of operation in 

order to estimate the noise during the design automation 

process. The algorithm uses quantization noise calculation 

at the early stages of design process for a coarse 

estimation. Throughout the design, other noise 

contributions are calculated and candidate solutions are 

generated or killed. 

The equation database has many equations which use 

device level parameters like amplifier gain, comparator 

offset, unit capacitor value, or switch resistances for 

calculating the system level parameters which are DR, 

area, power, conversion speed of the ADC. These 

parameters can clearly characterize an ADC and allow 

designs to be compared with others. 

The DR of the system can be found by calculating 

contributions of all error sources and non-idealities. The 

error sources of the architecture may be collected under 

four different headings. Three of the error sources are 

related to the blocks of the ADC: integrator, quantizer and 

DAC. The remaining one is the clock jitter. All the error 

sources can be modeled either as noise sources or

variations on the transfer functions [4]. As a result of the 

effects on transfer functions, the modified noise shaping 

behavior can be obtained. On the other hand, utilizing the 

extra noise sources, the in-band noise can be obtained. 

Then, DR and other performance parameters can be 

calculated. In order to achieve faster optimization, 

calculations performed for all error sources must be 

carried out without behavioral simulations. Most of the 

available approaches calculate performance of the systems 

through behavioral simulations, at least for some error 

sources. This is simply because some errors such as slew 

rate are much more difficult to model analytically. 

Integrator designs used in Sigma-Delta ADC’s are 

commonly switched capacitor integrators. Most of the 

errors introduced in these integrators can be modeled in 

the transfer function. The transfer function of a non-ideal 

integrator can be expressed as H(z) = Bz -1 /(1-Cz -1 ) where 

B represents the gain error and C represents the leakage at 

the simplest level expressed as: 


⎛ C ⎞ 

f AV 

− Cs 

C = ⎜ ⎟ 

⎜ ⎟ 

⎝ C f AV 

⎠ 

The effect of these errors is the introduction of additional 

terms to the famous quantization noise power expression 

given in [4]. If the expressions, which depend on OSR and 

order, are extended for higher order systems with some 

simplifications, it can be seen that the non-ideality adds 

extra terms to the noise power which is a function of 

modulator order and OSR. 

Although the transfer function of the integrator involves 

non-idealities, there are more error sources, which should 

be added separately. These are among the major 

differences of our work from other works reported. 

Slew-rate of the OPAMP causes an error which is additive 

to the output at the signal band. Some previous researchers 

try to estimate the slew-rate by analytically calculating the 

effects [4] or by performing behavioral simulations [3]. 

For fast design automation systems, slew-rate can be 

calculated in a different way. Our approach is to estimate 

the effect of slew-rate from signal information [5]. In this 

approach, it is observed that large differences between the 

current output and the previous output of the integrator 

cause slewing problems. If this difference is larger than 

the corners defined in linear slew-rate characteristic, 

slewing problems occur. Thus, using information from the 

signal statistics, the number of problematic slew-rate 

conditions can be achieved. In [5], it was shown that this 

value shows the error at the output by a constant. 

There are also errors caused by parasitic capacitances (Cp), which can be added to the capacitor CS in the transfer 

function. If these parasitic capacitances are known or can 

be estimated during the design, these capacitor values can 

be used to calculate CS. Capacitance mismatch is also 

important. The mismatch modifies the gain in the transfer 

function with a factor of (1-σ) where, σ represents the 

mismatch value. The effect of this noise source at the 

output is an additional term in the noise power. However, 

41 

these terms are quite complicated especially for cascaded 

systems and are therefore simplified for speed 

improvement of the system. 

The input referred noise coming from the switches and the 

OPAMP can be taken as an additive noise source at the 

input. This error causes an increase in the noise floor. 

The offset of the OPAMP is also an additive noise source 

in the feedback loop. This noise source can be added to the 

quantizer error. 

The error sources of the quantizer are the offset error, and 

the voltage error caused by settling time or slew rate. It 

can be easily seen that the offset error is additive to the 

quantization error. 

The other errors can be taken as an additional noise to the 

signal band. However, the error given in the above 

expression is shaped by the noise transfer function 

For single bit architectures, the errors of the digital-toanalog 

converter (DAC) do not have significant impact on 

the whole system. However, for multibit systems the 

linearity of the DAC is crucial and is actually the limiting 

factor in the performance since the error at this point is 

directly added to the input. For ADC’s designed by using 

switched capacitor integrators, the only contribution is the 

noise of the switches This error can be modeled as 

additive noise to the input signal, which will raise the 

noise floor of the system. 

One of the drawbacks of SD ADC’s is the oversampling 

process of the ADC. Since the architecture of the SD 

modulator uses oversampling, the error that may come 

from high sampling rates cannot be ignored. SD ADC’s 

generally have high sampling ratios, which may require 

jitter smaller than few picoseconds for wideband 

applications. The jitter error was modeled as an additive 

input. The most meaningful way of defining this error is to 

consider the first derivative of the signal and the possible 

shift in the sample time. The result will add an error to the 

signal. In our model, the signal at the input of the first 

integrator with clock jitter error is defined as: 

Xnew[nT]= X[nT+δ]= X[nT]+X’[nT].p(t) 

where X[nT] is the input signal, X’[nT] is the first 

derivative of the signal and p(t) is the Gaussian probability 

function representing the deviance from the sample time. 

The linear approach is feasible since the SD ADC employs 

high sampling values where the difference between two 

samples does not change much. The jitter error was 

modeled as an additive input noise where the X’[nT].p(t) 

term is an addition to the signal. The derivative can be 

expressed as X[nT]-X[nT-T] which can be calculated 

easily since the input signal characteristics are available. 

The developed algorithm can be used to find a solution 

with different oversampling ratios, orders and cascade 

configurations. The users even can interact with the tool 

and select if the solution should be a cascaded architecture 

or single-loop architecture. Also, there are some other 

configurations, which use feed-forward and feedback 

connections, and their models are still under development

and will be incorporated into the tool. The equation 

database is used for calculating the performance 

parameters of these architectures. 

Get design 

parameters 

Evaluate design 

Output 

feasibility 


Start 

Get desired 

SNR 

Get stability 

Get OSR 

1 Operation 3 

mode 

False 

Get ranges 

for missing 

data 

2 

Get library 

blocks 

Library 

complete 

True 

Evaluate 

Output feasibility 

and block parameters 

Figure 1. The algorithm. 

2.3 Modes of operation 

Search design 

space 

Find candidate 

solutions 

Output parameters 

of candidate 

solutions 

The developed algorithm has three different modes of 

operation for helping the designer during the system level 

design of the ADC. The user should select a mode for 

operation at the beginning of the design process. The first 

mode (verification mode) is for checking if the design is 

implementable. In this mode, the user provides all the 

design parameters for each block in the design and the tool 

checks the feasibility of the whole circuit. In this mode, all 

design parameters provided by the user are evaluated in 

the equation database and their noise contribution is 

calculated. Then, the tool calculates the performance 

parameters DR, area, power and conversion speed 

achievable with the given block parameters. 

The second mode (semi-custom mode) is where the user 

can attach a library to the tool. The libraries attached to the 

tool may contain block characterizations such as OPAMP 

and comparator information. Then, the tool tries to find a 

solution with the parameters of the blocks available in the 

library. This mode is useful when there are previously 

designed blocks. The designer may use these blocks or 

some of them and generate the specifications for the 

remaining blocks. 

In the last mode (the full automatic mode), the user only 

specifies the system level inputs. Then, the tool searches a 

42 

huge design space and finds candidate solutions based on 

an incorporated cost function for selecting a solution in the 

design space. In this mode, not only the block parameters 

are calculated, but also the order and cascade 

configuration are also explored. The design space 

exploration can be limited by user interaction. 

To be able to utilize this tool to its full power in the semicustom 

and full automatic modes, an accurate cost 

function should be defined. In this cost function, the 

power consumption and area of each block should also be 

provided. However, this information is available only if 

the blocks are pre-designed. In order to get around this 

problem, a performance estimator has been developed as 

explained in [2]. This performance estimator estimates the 

cost of any block given the required performance 

specifications such as gain, SR, etc [6]. Since the 

performance estimator is discussed elsewhere, it will not 

be detailed here. However, it is possible to guarantee the 

lowest cost solution with this approach. The accuracy of 

performance estimation lies in the approach used in the 

system. The performance estimator utilized in this work, 

has been developed using EKV models and provides 

accurate results in reasonable cpu time. 

Having more than one operation mode increases the 

flexibility of the design process. Also, by utilizing a 

library, the design time for an ADC may decrease 

considerably. It is certain that in such a case the solution 

will not be the optimum one, maybe not even close to it. 

The verification mode and semi-custom mode are geared 

towards typical design cycles in the industry where preverified 

cells exist and the engineer may wish to use them. 

2.4 Examples 

In order to show the accuracy of the models, an example is 

presented. Real circuit data from [4] is used since all 

design parameters are clearly stated. The design is a 

second order system which has 100.2 dB DR. In order to 

compare the models, the first mode of operation was used. 

The design parameters used in the reference design were 

given as input to the tool and it calculated the DR value as 

100dB. Although the results are very similar, the effect of 

capacitor mismatch was not included in the example run 

of the system. 

Another example is presented in order to show other 

modes of operation. The semi-custom mode of the SD 

ADC design tool was chosen in this example because it 

contains both library oriented design and automated 

design. The amplifiers were designed by automatically 

utilizing the performance estimator and the comparators 

were chosen from the library. The amplifier types utilized 

by the performance estimator throughout this example are 

cascode OPAMPs. 

In the design example, the desired specifications are a DR 

of 86 dB, a supply voltage of 5V, and an OSR of 64. The 

order of the modulator was not set. The desired DR value 

corresponds to nearly 14 bits of resolution.

The algorithm searches for candidate architectures with 

the given specifications. Since behavioral simulation was 

not performed for checking the stability of the design, the 

tool advised the user to use cascaded architectures, which 

utilize at most second order modulators. As a result the 

candidate architectures were 2-1, 2-2 and 2-2-1. However, 

lower order architectures can be achieved by assigning the 

OSR as a free variable. In this case, the algorithm searches 

for OSR values which provide adequate performance. This 

search is performed on ideal SD ADC equations and the 

real performance is calculated later by adding noise 

contributions. 

The candidate architectures which satisfy the desired DR 

performance for OSR of 64 were sent to the performance 

estimator and area and power values were estimated. 

The algorithm uses a structure called ‘worm’ which is a 

solution for the ADC. The worm contains all information 

such as OSR, supply voltage, configuration, noise values, 

DR, capacitor values and the block parameters such as 

amplifier gain, comparator offset. These worms are passed 

to functions in order to modify their relevant values, such 

as quantization noise or DR. For the semi-custom 

operation mode that is used in this example, worms were 

created for 2-1, 2-2 and 2-2-1 configurations. The initial 

number of worms depends on the number of elements in 

the library. The amplifier library was not used in this 

example, thus the comparator library defines the number 

of initial worms. Then, the user may select the range of 

parameters for the amplifier and other blocks. For our run, 

ranges for the gain of the amplifier and capacitor values in 

the integrator were set. 

The worms were sent to noise estimation functions which 

calculate the DR of the worm. As a result, the user has 

many solutions satisfying the specified DR performance. 

The algorithm generates 846 candidate solutions. 

Performance estimator could find a solution for 567 of 

them. This means that the OPAMP specifications for the 

rest were not achievable. These solutions were listed 

according to their DR values by the software. Several 

solutions may exist for the same DR with different 

structures in which case the optimum solution (in terms of 

area, power, or a combination of these two) should be 

selected by the user. 

2.5 Chip Design 

In order to test the developed system, a chip was 

fabricated in 0.6µm AMS technology, which contains two 

modules. The first module is for testing the first-order 

system. The second one is a 2-1 cascaded system, whose 

second and third order outputs are accessible. Correct 

operation of the modules was observed in initial testing. 

Figure 2 shows the I/O characteristics of 10 IC samples 

where the reference voltages are ±0.75V. The 

characterization results are in good agreement with the 

behavior predicted by the tool. The 60 mV offset is due to 

process variations. 


43 

Digital output mapped to analog 

1 

0.8 

0.6 

0.4 

0.2 

0 

-0.2 

-0.4 

-0.6 

-0.8 

y = - 0.000652*x + 0.0658 

M easured 

Data fit 

Target 

-1 

-1500 -1000 -500 0 

D ifferential Input 

500 1000 1500 

Figure 2. Chip characterization. 

3. CONCLUSION 

In this work a system level design automation system for 

SD ADC’s was presented. The developed system has 

some improvements on models of SD ADC’s, especially 

on jitter and slew-rate. Also, the algorithm of the system 

was developed such that it allows user interaction at every 

instance of design process. Another novelty of the 

approach is that it allows the modeling and synthesis of 

different architectures. It also is developed for seamless 

integration into previously developed ADA systems. A 

chip was designed to verify the validity of the approach. 

4. ACKNOWLEDGEMENT 

This work was supported by TÜBİTAK by project number 

101E039. 

5. REFERENCES 

[1] L. Williams, III and B. Wooley, "MIDAS—A 

functional simulator for mixed digital and analog 

sampled data systems." in Proc. Int. Symp. Circuits 

Syst. (ISCAS 92 ), pp: 2148-2151. 1992, 

[2] S. Balkır, G. Dündar, and A.S. Öğrenci, Analog VLSI 

Design Automation, CRC Press, 2003. 

[3] K. Francken, G.E. Gielen, "A High-level Simulation 

and Synthesis Environment for Delta Sigma 

Modulators", IEEE TCAD, Vol. 22, pp. 1049-1061, 

Aug. 2003 

[4] F. Medeiro, B. Perez-Verdu and A. Rodriguez- 

Vazquez, Top-Down Design of High-Performance 

Sigma-Delta Modulators, Kluwer Academic 

Publishers, Holland, 1999. 

[5] S. Talay and G. Dündar “Slew-Rate Effect in First 

Order Sigma-Delta ADC’s”, Melecon 2004, 

Dubrovnik, Crotia, May 2004. 

[6] E. Deniz and G. Dündar, “Performance Estimator for 

an Analog Design Automation System using EKVmodeled 

Analog Circuits”, to appear in ECCTD 

2005.


A REGULAR MODULAR ARCHITECTURE 

FOR PIPELINED BINARY TREE 

MULTIPLIERS BASED ON A SOG 

STRUCTURE 

Nicola Testoni, Marco Cisterni, Eleonora Franchi 

Advanced Research Center on Electronic Systems (ARCES), University of Bologna 

v.le Risorgimento 2, 40136 Bologna, Italy 

e-mail: ntestoni@arces.unibo.it 

ABSTRACT 

This paper presents an highly regular modular architecture 

for the design of pipelined binary tree multipliers which is 

suited to be mapped onto a gate array device. The “tree of 

Wallace trees” architecture is employed in order to 

achieve a regular layout, while symmetrical sea-of-gate 

(SOG) enables for a reduced design time and an high predictability 

of line delay. Post-layout simulations for a 

16×16bit pipelined multiplier designed using a 5 metal 

layers, 0.35μm CMOS technology show operative frequencies 

up to 1GHz. 


A great number of today's mid-volume integrated circuit 

production runs are not well-served by the two leading 

technologies in this field: FPGAs and ASICs. Author in 

[1] suggests that a new class of devices, namely structured 

ASICs, could fill the gap between these technologies, 

since they are both closer to FPGAs in terms of design 

costs and turnaround time and to ASICs in terms of gate 

capacity, performances and power consumptions. Modern 

high-end gate array devices can be viewed as extremely 

fine-grain structured ASICs, being both highly regular and 

fast to design: by this standpoint we describe a modular 

architecture for pipelined binary tree multipliers which can 

be easily used to quickly design arbitrary large multipliers 

with good throughput performances exploiting the high 

line delay predictability due to the use of a symmetrical 

gate array support. Taking steps from the Wallace Tree 

(WT) [2], the tree of Wallace Tree (TWT) [3] architecture 

is discussed in Section 2. In Section 3 we highlight the 

advantages of a symmetrical sea of gates (SOG) structure 

for the design stage of a TWT pipelined multiplier and we 

describe implementation choices at circuit and layout 

level. Section 4 shows the simulation results for a 

prototypical implementation on a 5 metal layers, 0.35μm 

CMOS technology. Section 5 concludes this paper. 

2. TWT ARCHITECTURE 

A TWT multiplier unit is divided into three stages: the 

first one generates the partial products, the second sums 

up the partial products adding them in parallel using 

multiple full adders (FA). The TWT architecture uses a 

pair of FA at each node in order to generate two outputs 

from four inputs (CSA 4:2), which results in a balanced 

binary tree with an high degree of regularity and a 

simplified wiring structure. The third stage generates the 

44 

Figure.1. TWT layout for a 16×16bit multiplier: 

partial product generators are shaded. The longest 

SOG row is enclosed by a dashed line while 

arrows indicate the adding direction; 

final multiplication result: in this stage, any kind of fast 

adder architecture can be used as a carry propagate adder 

(CPA). The layout of the TWT can be conducted in stages, 

from leaf nodes towards the root, in the form of an L-tree 

[4] as shown in Fig.1, so that any node is placed between 

its two children. Although the root always ends up in the 

middle of the layout, the resulting routing density is the 

smallest achievable for a linear placement structure, 

improving the pipeline performances. Finally, due to the 

symmetry of the layout at each leaf, the design of 

multipliers with an higher number of bits comes at almost 

no cost, while maintaining all the benefits of constant and 

predictable line delay. 

3. SOG IMPLEMENTATION OF TWT 

Since each CSA stage of the TWT multiplier is identical to 

its children, an optimized implementation for the CSA 

should be adopted. In this paper we exploit the 

performance that can be achieved by using the high 

regular structure of a SOG: even if this choice does not 

aim to single transistor optimization, it grants a certain 

degree of optimization on the whole layout. Each SOG 

basic cell is left-right symmetrical and contains one 

NMOS transistor and one PMOS transistor. The block 

diagram of the TWT latch-based pipeline is shown in 

Fig.2.

3.1 CSA design choices 

Due to the SOG structure, a CSA layout with a balanced 

number of NMOS and PMOS is required. In order to both 

ease the design phase and achieve an high throughput, we 

chose a static pass transistor logic for each FA. Delay 

between each FA is reduced removing the output inverter 

stages, thus using negative logic FA (FAn) instead of 

common FA: since the number of FA in each CSA is even, 

this choice does not alter the global logic function. 

Moreover, a tree of pass-transistor logic FA implements a 

number of pass-transistor gate chains: each chain can be 

optimized in order to achieve the minimum propagation 

time. The schematic of the basic CSA unit is shown in 

Fig.3. 

3.2 Layout level design choices 

The CSA stages are arranged in order to have partial 

products of the same weight on the same SOG row. Only 

one row of maximum length exists (Fig.1) and it can be 

shown that it coincides with the critical path (Fig.2). 

Interestingly, this same row is replicated to implement 

both active circuitry and local interconnections between 

TWT leaves in each row, thus leading to the highly regular 

layout shown in Fig.5. This layout structure is made 

possible due to the flexibility of the FA: in fact, since they 

are based on pass-transistor logic, whenever some of their 

inputs are fixed, they can work both as half adders or 

buffers with almost the same performance of dedicated 

hardware. This improves both the modularity of the design 

and the global predictability of the line delay since each 

interconnection is realized using the same structure. 

Additionally, since the TWT is a balanced binary tree and 

the SOG used is itself symmetrical, each path is equivalent 

to the critical one in terms of performances: this means 

that the optimization effort can be concentrated on the 

basic CSA and the pipeline buffers since the length of 

each line is quantized. Finally, thanks to the symmetry of 

the SOG, each cell in the TWT is designed only once and 

then mirrored left-right in order to realize the L-Tree 

structure. This gives way to interconnections that have the 

same length and capacitance not only between each row 

but even between each leaf of the L-Tree. 

3.3 Pipeline latches design and optimization 

In order to improve pipeline throughput, pass-transistor 

based dynamic latches are used in place of static registers: 

the two clock phases are generated within each latch from 

a single phase clock. This additional circuitry, consisting 

of a cascade of 2 logic inverters is not shown in Fig.4. 

Since both FA and latches are based upon pass-transistor 

logic, an almost complete analysis of the critical path load 

capacitance can be issued in order to optimize the latches' 

output buffer. Given the characteristics of the minimum 

sized inverter available on the SOG and a good RC model 

for the propagation delay of the pass-transistor gate, the 

optimization effort [5] along the critical path gives the 

following results: optimal number of pass-transistor gates 

in each stage equal to 2.7 and stage buffer multiplying 

factor equal to 2.2. Given the constraints of the SOG 

support, the implemented solution is the closest to these 


45 

Figure.2. Block diagram of the pipeline: critical 

path is drawn solid while dashed block represents 

other TWT leaves. 

Figure.3. Basic CSA block schematic: two 

negative logic FA are used in order to reduce the 

propagation delay. 

Figure.4. Pass-transistor logic latch with Set- 

Reset; output transistors are double-sized in order 

to reduce delay.

values: in fact, along the critical path we have at most 3 

subsequent pass-transistor gates, taking into account the 

one within the latch too, while each latch output buffer is 

double-sized. I/O propagation time for rising edges is as 

low as 65ps while is close to 83ps for falling edges; 

propagation time from clock rising edges are 166ps for a 

falling output transition and 186ps for a rising one. As for 

a 16×16bit multiplier, the difference in interconnections' 

length between CSA stages results in a negligible 

difference of capacitance loads so that equal sized pipeline 

buffers are used. 

3.4 Line drivers design and optimization 

Even if the TWT structure has a very regular layout, as 

shown in Fig.5, multiplicand's and multiplier's input bits 

does not follow the same path within the unit: the length 

of the longest distribution line for each input signal must 

be correctly estimated in order to optimize the 

performance of line drivers. Fig.6 displays two sample 

input signal lines: in general, it can be shown that, while 

the length of the multiplicand's distribution lines A0:A15 is 

almost constant throughout the whole unit, the length of 

multiplier's distribution lines grows constantly from B0 to 

B15 but upper bounded by the length of the multiplicand's 

lines. The longest line measures 914μm and its 

capacitance load is 166fF. In addition to this, multiplier's 

and multiplicand's lines have the same fan-out: for a 

16×16bit unit based on a 0.35μm CMOS technology this 

capacitance load is 214fF, almost 150% of the capacitance 

load of the longest line, thus reducing the difference 

between input signal buffers' total capacitance load. Input 

signals line drivers are implemented using a passtransistor 

latch followed by a cascade of buffer with 

growing form-factor: the optimization process [5] gives a 

form-factor multiplying factor of 4, while the optimal 

number of stages needed to drive a capacitance of 380fF is 

2.4. We implemented a 3 stages line driver since it 

produces sharper signal edges, while keeping the 

propagation delay as low as possible. 

3.5 TWT as multiplier building block 

Larger multipliers can be easily built using the basic TWT 

unit: it's symmetry and modularity can be exploited by a 

structure compiler to design an arbitrary large multiplier 

simply mirroring and tiling appropriate sized TWT unit. 

As shown in Fig.7, a 16×16bit TWT multiplier is made up 

of four 8×8bit TWT multipliers enclosing the final stage 

CSA for that level. In general, the easiest way to 

implement a larger multiplier given a basic TWT unit is 

the following: 

• Create a copy of the TWT unit 

• Mirror it upside-down 

• Tile it over the original TWT 

• Create a copy of the new compound 

• Mirror it left-right 

• Tile the new compounds around a CSA unit 

• Properly interconnect units' input signals. 


46 

Figure.5. Layout of the 16×16bit TWT multiplier 

on a 0.35μm CMOS technology symmetrical sea 

of gate. 

Figure.6. Comparison between signal distribution 

lines for input A2, B2 and B13 within a 16×16bit 

TWT multiplier. 

Figure.7. Hierarchical subdivision for a 16×16bit 

TWT multiplier: 8×8bit TWT are tiled enclosing 

the last stage CSA.

Before interconnecting units, some optimization should be 

taken into consideration: in fact, it can be shown that no 

more than 2(N-1)+log2(N) SOG rows are required for the 

layout of a TWT multiplier with N input bits per channel. 

Using an 8×8bit TWT unit as basic block, up to log2(N)-4 

SOG rows can be eliminated at each stage from the top of 

the stack without compromising the global functionality. 



Simulations of a 16×16-bit unsigned multiplier have been 

done using a 5 metal layers, 0.35μm CMOS technology on 

Spectre. Each cell of the SOG measures 1.5μm×17.4μm 

and contains one NMOS transistor with WN=3.4μm and 

one PMOS with WP=4.7μm: these form factors had been 

chosen in order to maximize the routability of the first 

metal layer and to minimize the propagation delay; the cell 

is left-right symmetrical. A 16×16bit TWT unit measures 

636μm×592μm, as shown in Fig.5; in order to implement 

a working multiplier, distribution network drivers for 

clock, set and reset signals and input signal buffer must be 

added: the former requires 3 additional topmost SOG 

rows, while the last needs 28 columns at each SOG row. 

Dimensions for a 16×16bit TWT multiplier are thus 

678μm×644μm. Performance simulations involved the 

critical path only: worst case commutation for each FA 

pair was considered in order to properly evaluate the 

minimum clock period. The structure regularity allowed 

for a simple but effective simulation setup: each critical 

path carry-out and sum-out is used to generate the 

corresponding carry-in and sum-in. This corresponds to 

the simulation of the multiplier central row, when both 

lower and upper rows are involved in a worst case 

commutation. As shown in Fig.8, several post-layout 

simulation at 3.3V power supply and different 

corner/temperature were conducted in order to evaluate 

the fastest allowed operating frequencies; after that, 

quadratic least square interpolation was used to 

extrapolate continuous functions of the temperature. As 

expected, fast corner allows for 1.1GHz operations all 

over the industrial temperature range, while only 750MHz 

can be guaranteed for the slow corner. Typical corner 

post-layout simulations (Fig.9) show that 1GHz operating 

frequency is easily achievable on this support at 27°C. 


An high-regularity modular architecture for the design of 

pipelined binary tree multipliers has been presented. The 

regularity of the architecture combined with the structure 

of the SOG allows for an high degree of predictability of 

line delay and for a great balancing of line capacitance 

load. System-wise optimization of pipeline buffers led to 

high operating frequencies even if SOG does not allow for 

single transistor optimization. The proposed architecture 

seems an ideal candidate to the design of a multipliers' 

compiler providing both short design time and predictable 

performance. 

47 

Figure.8. Post-layout simulation results for 

minimum clock period vs. temperature sweep at 

different corners; solid curves are obtained 

through quadratic LS interpolation. 

Figure.9. Simulation results for the critical path 

of a 16×16bit TWT multiplier in 0.35μm CMOS 

technology at Vdd=3.3V, T=27°C: all output 

signals' transients end before clock risings. 

6. REFERENCES 

[1] B.Zahiri, “Structured ASICs: Opportunities and 

Challenges”, 21 st IEEE International Conference on 

Computer Design, proceedings, pp.404-409, 2003. 

[2] C.S.Wallace, “A suggestion for fast multiplier”, 

IEEE Transactions on Electronic Computers, vol.13, 

pp.14-17, Feb. 1964. 

[3] K.F.Pang, “Architecture for pipelined Wallace tree 

multiplier-accumulators”, IEEE International 

Conference on Computer Design., proceedings, 

pp.247-250, Sep. 1990. 

[4] Y.Harata, et al., “A high speed multiplier using 

redundant binary adder tree”, IEEE J. Solid St. Circ., 

vol.22, pp.28-34, Feb. 1987. 

[5] I.Sutherland, et al., “Logial Effort: Designing Fast 

CMOS Circuits”, Morgan Kaufmann Publisher, 

1999.

Abstract 


Developing a Strategic Error Source Based 

Design Evaluation For ADC’s 

Jason Hannon, Carsten Wegener and Michael Peter Kennedy 

In this work, we develop the foundation of an error source 

based Design Evaluation and apply it to the exmple of 

a Succesive-Approximation-Register (SAR) Analog-to-Digital 

converter (ADC). The proposed approach identifies the error 

sources in the design and relates them to the performance characteristics 

measured for prototype samples. Based on this 

identification, we extract the sources of dominant performance 

degradation and suggest a redesign to counter act the latter. 

1 Introduction 

The objective of this article is to develop a strategic approach to 

Design Evaluation of an ADC. The aims of Design Evaluation 

consist of: 

establishing confidence that the design meets specifications 

with high yield in volume manufacturing [1], and 

determining the sources of errors degrading device performance. 

If a design marginally meets its design specifications, an important 

piece of information to learn from Design Evaluation is 

which are the contributors that affect the design performance. 

This information proves invaluable for two reasons: (1) guiding 

a redesign effort which can lead to devices that perform 

towards improved specifications, and (2) providing information 

on potential design hazards for future designs when migrating 

to smaller geometies. Also, with tighter profit margins for IC’s, 

e.g. in consumer products, achieving a yield in manufacturing 

that is higher by even a small percentage translates into significant 

additional revenue. 

Traditional Design Evaluation approaches are ad-hoc in nature; 

when a design does not satisfactorily meet specifications, the 

design evaluation engineer attempts to identify the design errors, 

i.e. the main source of performance degradation. With 

increasing complexity of designs, the portion of time for evaluating 

and troubleshooting design errors is increasing [2]. 

The here proposed approach is strategic in that all known error 

sources inherent to the design are identified and subsequently 

modeled. This provides insight into device behavior, which is 

ready for exploitation by fitting contributions associated with 

independent errors sources to the measured device response. 

The advantage of the model based approach is that one can establish 

the model’s completeness with respect to covering the 

Department of Microelectronic Engineering, 

University College Cork, Ireland 

E-mail: jason.hannon@ue.ucc.ie 

48 

on chip error sources; if the model is incomplete this will show 

as lack of fit of the model. Like this one can ensure that all relevant 

error sources are covered, or at least, determine the degree 

of coverage, i.e. the quality of fit, obtained. 

2 Design evaluation 

2.1 ADC transfer characteristic 

The transfer characteristic, i.e. the input to output relationship, 

of an ADC depends on the device parameters. This relationship 

is generally non-linear, however, if the parameters vary by 

only a small amount, as is typical for a stable manufacuring 

process, this dependence can be approximated by a linear relationship 

[3]. 

The Integral Nonlinearity (INL) describes, how far away from 

the ideal transfer function is the converter under test. The 

IEEE [4] defines the maximum and minimum INL of an ADC 

as the most positive and negative difference between the ideal 

and measured code transition levels. 

Fig. 1 shows a plot of the nominal INL characteristic versus 

code for the ADC used in this work. This INL curve is obtained 

by averaging the INL curves of the 77 devices which are taken 

as a representation sample for the manufacturing process. Note 

that this averaging removes the influence of manufacturing process 

variations, thus, the characteristic shown can be considered 

the INL curve built-in by design, which ideally should be zero 

at all-codes. 

2.2 Standard approach 

The standard approach to Design Evaluation starts with measuring 

the design specifications for a sample set of devices from 

the manufacturing process. For a sample set of 77 measured devices, 

the probability density distribution of maximum and minimum 

INL values is shown in Fig. 2. If, as in the case shown, 

there is sufficient margin between the performance spread and 

the design specifications of |INL| < 1.5 LSB, the design can be 

submitted to high volume production. Otherwise, Design Evaluation 

continues with the aim of identifying and counteracting 

the dominant on-chip error sources that contribute to performance 

degradations. 

At the point of identifying the dominant source of error, the 

relationship between design-specific error sources and the per-

Integral Nonlinearity in LSB 

0.5 

0.4 

0.3 

0.2 

0.1 

0 

−0.1 

−0.2 

−0.3 

0 500 1000 1500 2000 2500 3000 code 4000 

Figure 1: Nominal INL characteristic with maximum of 

+0.39 LSB and minimum of −0.28 LSB. 

Probability density 

3.5 

3 

2.5 

2 

1.5 

1 

0.5 

0 

−1.5 −1 −0.5 0 0.5 1 1.5 


Integral Nonlinearity in LSB 

Figure 2: Distribution of maximum and minimum INL 

for ADC sample. 

C2 

C1 

K circuit elements 

R n 

x 

n device parameters 

Model 

Figure 3: Model mapping. 

R m 

b 

m measurements 

49 

VIN 

CMP 

DAC 

Code Word 

Figure 4: SAR ADC block diagram. 

SAR 

Logic 

formance measurements becomes an important input to the Design 

Evaluation process. However, in the standard approach, 

the design engineer can only inspect the measurement results 

in detail and try to replicate the observed performance degradation 

in simulation. This trial-and-error approach is costly as it 

delays Time-to-Market and, moreover, does not guarantee completeness 

with respect to all known sources of error. 

2.3 Design evaluation based on error 

source model 

The approach taken in this work is to build a model which can 

replicate the measured results. This model is first built using the 

circuits schematics, with the component values setting the models 

device parameters. Once the model is fitted to the measured 

INL transfer function, the values for the device parameters used 

to fit the model can be used in the circuit schematic to give the 

actual values for the components. The previous approach was 

ad hoc, unless an on-chip error source dominated the INL performance 

degradation it proved difficult to locate the reason for 

performance degradation. 

The test vehicle used for this research is a 12-bit SAR ADC 

design similiar to [5]. This ADC uses a charge-redistribution 

DAC in a feedback loop and which is illustrated in Fig. 4. The 

output code for the ADC is the DAC’s input “code word” at 

the end of the SAR logic controlled conversion cycle. Nonlinearities 

in the transfer characteristic of the ADC are due to 

nonlinearities in the DAC and the settling time for the decision 

by the comparator (CMP). In this work, we focus on the DAC 

nonlinearities as it can be shown to be the dominant contributor 

to the nonlinearity of the ADC. 

The model based approach focuses on the linear model concept 

which exploits the relationship between on-chip error sources 

and the Integral Non Linearity (INL) measurements [1]. The 

modeling approach uses the fact that mismatches, vary by only 

a small amount, such as DAC component mismatches, thus the 

model can be linear in the component parameters. Known error 

sources that impact the INL characteristic are simulated. 

Since the modeling is linear, the superposition principle holds 

therefore it is possible to simulate each individual error source. 

These simulation results combine to form the overall INL transfer 

characteristic.These simulation results are used in a matrix 

A for a 12-bit converter the size would be (4096 × n) with n 

denoting the number of error sources. The measured device 

characteristic b ∈ R 4096 is decomposed as 

b = Ax + ∆b (1) 

Where x is a vector of parameters associated with each error and 

the residual ∆b is the lack of fit. Solving for x gives the values

Cc 

Cb4 

1 

32 

Cb5 

Cb3 

Cb6 

Cseg1 


1 

16 

Cb2 

2 

8 

Cb1 

4 

4 

Cseg2 

Cb0 

4 

2 

Cseg31 

Ct 

1 

4 

Cgnd 

Sgnd 

4 

Cpar 

Figure 5: 12-bit Charge Redistribution DAC. 

X 

Sin 

− 

+ 

Sfb 

Vin Vref 

for the models parameters. These parameters are then related 

back to the component values in the schematic giving the actual 

values for the manufactured device. This is used to identify the 

dominant error source or combination of error sources causing 

the degradation in the INL transfer characteristic. 

3 Succssive approximation register 

ADC 

3.1 ADC implementation 

The charge redistribution DAC in the SAR ADC is shown in 

Fig. 5 the top five bits are segmented, with the remaining seven 

bits being binary weighted. 

The operation of the ADC is as follows. All the switches are 

initially as shown, this tracks the input voltage Vin charging all 

the capacitors to the input voltage. At the end of this sampling 

phase the switches S fb and Sgnd are opened, preserving 

the charge on the capacitors. Next all the switches at the bottom 

end of the capacitors are switched to ground, causing the 

comparator input voltage to go to −Vin. The input switch Sin 

is than connected to reference voltage Vre f .The SAR logic then 

starts a binary search for a setting of the switches at the bottom 

end of the capacitors for which the comparator input node 

returns to ground. 

3.2 Development of the model 

In the circuit diagram in Fig. 5, forty-one capacitors are shown; 

each capacitor is labeled with the number of unit capacitors 

they are made up of. If all capacitors are at there ideal value 

and the comparator has sufficient settling time then the simulated 

INL characteristic is that of an ideal ADC, i.e. zero at 

all-codes. However, the manufacturing process causes these capacitor 

values to deviate randomly from ideal which causes the 

INL chartacteristic to display nonlinearities. During the manufacturing 

process typically the capacitors will be mismatched 

by 0.1% [6] of their designed value. 

In Fig. 6 the segment capacitors Cseg1,...,Cseg31 simulated INL 

characteristics for each individual capacitor increased by 0.1% 

is shown. 

50 

0.1 

0.05 

0 

−0.05 

−0.1 

INL in LSB 


0.15 

0.1 

0.05 

0 

0 500 1000 1500 2000 2500 3000 3500 4000 

Cseg1 

Cseg2 

Cseg3 

−0.05 

0 100 200 300 400 500 

Figure 6: Simulated INL characteristic for segment capacitors 

being increased by 0.1%. 

4 Application of the model 

4.1 Solution with identified error sources 

As discussed in section 2.3, a model is built using simulation 

results obtained from all the known error sources. These results 

are than used in equation 1 to decompose the measured device 

response into a set of weighted values for each error source. 

Since this model replicates the measured results, applying these 

weights to the simulated results should result in the INL characteristic 

obtained from the measured results. 

The results of this are shown in Fig. 7. The top graph is the 

average device characteristic for 77 device measurements. The 

bottom graph in Fig. 7 is the residual ∆b, i.e. the lack of fit for 

the model. 

The spikes in the residual lack-of-fit represent the settling time 

of the comparator decision. By inspection of the residual: the 

largest peaks are located at codes 1023 and 3071 corresponding 

to the second most significant bit in the code word. Note that the 

ADC design allows more settling time for the most significat 

bit (MSB) decision so there is no peak observed at mid-scale 

code 2047. 

4.2 Improved model 

From the initial model built using the known error sources the 

lack of fit was to high, making it apparent an major error source 

had been missed. The next step is to identify this missing error 

source, which had caused the model’s lack of fit. The answer to 

the missing error source came from inspecting a zoomed plot 

of the fitted INL characteristic and nominal INL characteristic. 

This is shown in Fig. 8, the difference between the two 

waveforms is a repeating range of 32 codes this points to the 

sub-DAC being the location of the missing error source. 

The waveform seen in the zoomed plot exhibits the shape seen 

from simulations for mismatches of Ct and Cc. The explanation 

for the mismatch is a parasitic capacitance to ground on 

the sub-DAC. This capacitance can be lumped into a capacitor 

Cpar which is shown in Fig. 5. The lack of fit is improved by 

including the INL characteristic for the termination capacitor. 

The result for fitting the improved model is shown in a plot in

Nominal INL in LSB 


0.4 

0.2 

0 

−0.2 

0.2 

0.1 

0 

−0.1 

0 500 1000 1500 2000 2500 3000 3500 4000 

−0.2 

0 500 1000 1500 2000 2500 3000 3500 4000 

Figure 7: Simulated INL characteristic for segment capacitors 

being increased by 0.1%. 


0.2 

0.15 

0.1 

0.05 

0 

−0.05 

−0.1 

−0.15 

−0.2 

−0.25 


Fitted INL Characteristic 

Measured INL Characteristic 

50 100 150 200 250 300 

Figure 8: Simulated model characteristics fitted to nominal 

INL. 


0.25 

0.2 

0.15 

0.1 

0.05 

0 

−0.05 

−0.1 

−0.15 

−0.2 

−0.25 

0 50 100 150 200 250 

Figure 9: Improved model characteristics fitted to nominal 

INL. 

51 

Fig. 9. From the results it is apparent that the improved model 

is now able to capture the INL characteristic of the measured 

characteristic much closer. 

Now that we have a more accurate model we will use it to suggest 

a redesign that can perform to a higher specification. As 

was seen a major reason for the lack of fit originally was the 

parasitic capacitance in the sub-DAC. The parasitic capacitance 

is a major contributor to the performance degradation. The size 

of the parasitic capacitance can be estimated by the mismatch 

of Ct in the nominal INL characteristic. The mismatch from 

Ct suggested that the parasitic capacitance Cpar value is equal 

to 58% of a unit capacitor. The suggested redesign is to make 

capacitor Ct value 42% of a unit capacitor. 

5 Conclusions 

In this paper we have presented an error source based approach 

to Design Evaluation. The advantage of this model-based approach 

is that one can quantify the approach’s completeness in 

terms of the on-chip error sources and that the masking effect 

of multiple error sources can be removed in the decomposition 

process. 

In the example used in this paper, a previously un-quntifiable 

error source, i.e. the parasitic capacitance Cpar is determined. 

This was seen from a large lack of fit for the first model. The 

model was improved accommodating Cpar. Using the improved 

model Cpar was estimated from the decomposition process and 

a redesign suggested to compensate for this error source. 

References 

[1] C. Wegener and M. P. Kennedy, Linear model-based error 

identification and calibration for data converters, in 

Proc. DATE, ser. Conf. on Design, Automation and Test 

in Europe, Munich, Germany, March 2003, pp. 630–635. 

[2] International technology roadmap for semiconductors. 

[Online]. Available: http://public.itrs.net 

[3] C. Wegener, Applications of linear modeling to testin and 

characterizing d/a and a/d converters, Ph.D. dissertation, 

University College Cork, Nov 2003. 

[4] IEEE-Std-1241 Draft, The Institute of Electrical and Electronics 

Engineers, Inc., New York, March 2000, IEEE standard 

for terminology and test methods for analog-to-digital 

converters. 

[5] A. Rivetti, G. Anelli, F. Anghinolfi, G. Mazza, and F. Rotondo, 

A low-power 10-bit ADC in a 0.25-µm CMOS:design 

considerations and test results, IEEE Trans. Nuclear 

Science, vol. 48, no. 4, pp. 1225–1228, Aug. 2000. 

[6] M. McNutt, S. LeMarquis, and J. Dunkley, Systematic 

capacitance matching errors and corrective layout procedures, 

IEEE Journal of Solid-State Circuits,, vol. 29, no. 4, 

May 1994.


SIGNAL-PATH LEVEL ASSIGNMENT FOR DUAL- 

Vt TECHNIQUE 

Yu Wang, Huazhong Yang, Hui Wang 

Circuits and Systems Laboratory, Department of Electronic Engineering, 

Tsinghua University, 100084, Beijing, People’s Republic of China 

E-mail: wangyuu99@mails.tsinghua.edu.cn 

ABSTRACT 

Along with the fast development of dual threshold voltage 

(dual-V t) technology, it is possible to use it to reduce static 

power in low-voltage high-performance circuits. In this 

paper we present a new signal-path level circuit model and 

an algorithm based on the new circuit model which 

introduces the concept of extracting sub-circuits. 

Experimental results show that, for the ISCAS85 

benchmark circuits, our algorithm produces a significant 

leakage-power reduction similar to the transistor level 

dual-V t assignment, but the computational cost is 

comparative to gate level dual-V t assignment. 


With the development of the fabrication technology, 

leakage power dissipation has become comparable to 

switching power dissipation [1]. At the 90nm technology 

node, leakage power may make up 42% of total power [2]. 

Inevitably, techniques are necessary for reducing the 

increasing leakage power. These leakage control methods 

can be broadly categorized into two main categories: 

process level and circuit level techniques. At the process 

level, leakage reduction can be achieved by controlling the 

dimensions (length, oxide thickness, junction depth, etc.) 

and doping profile in transistors. There are also four major 

circuit design techniques, namely, transistor stacking, 

supply voltage scaling, dynamic V t and multiple V t for 

leakage reduction in digital circuits. The two main 

methods in multiple V t technique are sleep transistor 

insertion and dual V t CMOS assignment. The extra area 

and delay due to the insertion of sleep transistors have 

considerable influence on the circuit performance. 

Furthermore, with the supply voltage scaling, it is 

becoming harder to turn on under a very low supply 

voltage. A higher V t can be assigned to some of the 

transistors in the non-critical paths and a lower V t is 

assigned to other transistors in the dual V t CMOS 

assignment for a logic circuit in order to achieve both high 

performance and low power simultaneously. Recently, a 

dual-V t MOSFET process was developed [3], which 

makes the implementation of dual-V t logic circuits more 

feasible. Dual-V t method results in a significant reduction 

in total power dissipation and energy. Therefore, 

determining which gate should be the high V t has already 

become a major emphasis in the research field. 

Traditionally, gate level dual-V t assignment [4][5][6][7] 

52 

suppresses less leakage power than transistor level dual-Vt assignment [8] while saving much more computation time. 

In this paper, we assume that all the gates are using the 

low threshold voltage in order to get the best performance 

(timing characteristic). The new signal-path level circuit 

model we used is different from the circuit models which 

consider a gate as a vertex or an edge in a graph. This is to 

make our algorithms useful for transistor level leakage 

control. We use look up table method in static timing 

analysis to get the critical paths and non-critical paths of 

the circuit much faster and with more accuracy. The gates 

in the critical paths will remain unchanged to maintain the 

performance; and the gates in the non-critical paths are 

extracted into several sub-circuits. Without reiterating the 

whole circuit, we can focus solely on dealing with the subcircuits 

in which we use a new developed hierarchy based 

algorithm to get an optimal result faster. Our new signalpath 

level dual Vt assignment aims to have more leakage 

power saving and a similar or even less computation 

complexity than gate level dual-Vt assignment. 

2. DUAL Vt ASSIGNMENT 

2.1 Gate level circuit model 

A combinational circuit is represented by a directed 

acyclic graph (DAG) G = (V, E). Traditionally a vertex v 

∈V represents a CMOS transistor network which realizes 

a single output logic function (a logic gate), while an edge 

(i,j)∈E, i,j∈V represents a connection from vertex i to 

vertex j. In this way, the transistors within a vertex that are 

driven by the same logic signal will be assigned to the 

same threshold. 

The assignment of threshold voltages to the transistors in 

the circuit can be represented as one of assigning a 

threshold voltage to a vertex v∈V [3][4][5], or one of 

assigning a threshold voltage to an edge (i,j)∈E [6]. Thus 

this allows us to treat the dual-Vt optimization problem as 

a kind of graph problem. It greatly simplifies delay 

analysis and standby power estimation during Vt assignment. The effects on delay when a Vt change is 

made can be easily modeled by static timing analysis 

(STA) methods. In Figure 1, a combinational circuit is 

presented at the left side; the traditional circuit model is at 

the right side.

Figure 1. Original circuit C17 in ISCAS85 and 

traditional gate level circuit model. 

2.2 Signal-path level circuit model 

In our signal-path level circuit model, a vertex v ∈ V 

represents a pin of logic gates or a primary input/output; 

an edge (i,j)∈E represents a connection from vertex i to 

vertex j. In our model, an edge is the abstraction of a wire 

connecting two pins of two different gates or a signal-path 

in a logic gate from one of its input pin to an output pin. 

Furthermore, we have added a virtual input vertex and a 

virtual output vertex to our model. The virtual input vertex 

is connected to all the primary inputs and the virtual 

output vertex is connected to all the primary outputs. The 

fan-in of a logic gate’s input pin refers to the number of 

pins which connect with this input pin. The fan-out of a 

logic gate’s output pin refers to the number of pins which 

is connected with this output pin. Furthermore, vertexes 

which have a fan-in of zero constitute primary inputs; 

similarly vertexes which have a fan-out of zero constitute 

primary outputs. Figure 2 shows our signal-path circuit 

model of circuit C17 from ISCAS85 bench mark. If vertex 

i∈V represents one of gate A’s input pins and vertex j∈V 

represents gate A’s output pin, we define edge (i,j)∈E as 

a “signal-path” and this signal-path belongs to gate A. 

And actually each signal-path consists of one of the 

parallel transistors and the transistors in series in a simple 

classical CMOS gate. 

Figure 2. Signal-path level circuit model (C17). 

There are several reasons for using this new circuit model. 

Firstly, the signal arrival time may be different for every 

input pin of a gate. More detailed delay information for 

every gate is presented since the delay information for 


53 

every pin of the gate is computed by STA. Secondly, 

through the definition of signal-path, it is possible to have 

transistors with different Vt in a single gate at the same 

time, which means transistors in one gate may have 

different Vt. If we neglect the possibility of assigning 

different threshold voltage to signal-paths which belong to 

the same gate, it will get the same solution as previous 

methods [4][5]. Finally it leads to a much less 

computation complexity than transistor level assignment 

[8], yet achieving a similar accuracy. 

The edge E in the graph represents two kinds of 

connections. One is “signal-path”, the other is the 

connection of two pins belonging to different gates 

respectively which represents a wire between two pins in 

most cases. Hence it is possible to consider the 

interconnect delay during STA in order to get more 

accurate model of the circuit. 

2.3 Delay model 

We create our signal-path delay model and get arrival 

time, require time and slack time information for each 

vertex and signal-path in the signal-path level circuit 

model. 

In order to get the delay attributes, we levelize the 

vertexes in the graph, making sure every two vertexes 

belongs to the same level have no edges between them. 

Each pin’s fan-ins are not at the same level as itself, its 

fan-outs are not either; thus an edge (i,j) ∈ E’s two 

vertexes i,j∈V are not at the same level. The delay of an 

edge (i,j)∈E, i,j∈V is denoted by di,j. We define three attributes for every vertex v∈V, they are 

namely, the arrival time ta(v), the required time treq(v), and 

the slack time tslk(v). The arrival time ta(v) is the worst 

case of delay from the primary inputs to pin v. treq(v) is the 

latest time the signal needs to arrive at pin v. We define 

them as: 

⎧⎪ 

given _ time _ of _ arrival, if v is the vitual input 

t ( v) 

≡ a ⎨ max { t ( i) + d , } , otherwise 

a i v 

⎪⎩ i∈fan_ in( v) 

⎧ta( 

v), if v is the virtual output 

⎪ 

treq () v ≡ ⎨ min { treq ( i) − d 

⎪⎩ 

v, i} 

i∈ fan _ out( v) 

By comparison to traditional circuit model, the arrival 

time of a gate is the maximum of its input pins’ arrival 

time, and the required time of a gate is its output pin’s 

required time (if the gate is a CMOS transistor network 

which realizes a single output logic function). The slack 

time of a gate is also defined as the difference of its arrival 

time and required time. The critical path of the circuits is 

constituted by the set of gates that has the minimum slack 

time value. 

We define every edge (i,j)∈E, i,j∈V in the graph G also 

has the attribute s i,j which represents the slack time of the 

edge: 

s ≡ t ( j) −t ( i) −d 

i, j req a i, j

Finally, the slack time of a vertex v∈V is defined as the 

minimum slack time of its fan-in edges: 

t () v = mins 

s iv , 

i∈fan_ in( v) 

In our delay model we define the critical path of the 

circuits as the set of the edges that has the minimum slack 

time value. If there is no negative slack in the circuit, then 

timing constraints are satisfied [9]. 

Notice that every signal-path in the same gate can have 

different delay difference when its Vt changes; and when 

several signal-paths can be simultaneously changed in one 

gate, the delay difference is even more complicated 

because of the infections between the changed signalpaths. 

Here we select the largest delay difference of all the 

signal-paths’ change schemes as the reference delay 

difference of the signal-path in this kind of gate. The 

signal-path delay data are then derived from the look up 

table of standard cells and HSPICE simulation. 

2.4 Leakage power model 

We find out that the leakage power change due to only one 

signal path’s change is always the same and furthermore, 

if there are k signal-paths which can change their threshold 

voltage in a gate with w signal paths (k< w), no matter 

how to choose the k signal paths, the power change due to 

k signal paths’ threshold voltage change is always the 

same. The leakage power saving due to k signal paths’ 

threshold voltage change is nearly the same as k times the 

leakage power saving due to only one signal path’s change. 

However, if all the w signal paths in the gate is changed, 

the leakage power saving is larger than w times the 

leakage power saving due to only one signal path’s 

change. Finally we use two values to represent each signal 

path’s leakage power attributes: the larger one is for all the 

signal paths in that gate can change into high threshold 

voltage, and it equals to the leakage power saving due to 

the gate’s threshold voltage change divided by the number 

of signal-paths in the gate; and the smaller one is for other 

conditions which equals the leakage power saving due to 

only one signal path’s change. Using HSPICE and a 

typical library for each circuit scheme of the signal-path, 

we can create a table of leakage power for the signalpath’s 

threshold voltage change. 

We do not consider the signal probability at each pin of 

the gates, and we may use logic simulation or local 

probability propagation in our future work to make it 

possible to combine transistor stacking effects with the 

circuit analysis to get a more accurate leakage power 

estimation table. 

2.5 Algorithm 

The dual-Vt optimization is defined as a problem to assign 

one of two threshold voltages to each signal-path to get 

most leakage power reduction with no performance 

reduction. 

In our algorithm, we assumed the DAG representation 

G(V,E) of a signal-path level combinational circuit. The 


54 

graph is firstly levelized to indicate the depth of the 

vertexes and signal-paths in the graph. We initialize the 

circuit by assigning a low threshold voltage (VTHlow) to all 

the signal-paths of the circuit, i.e. it essentially configures 

the circuit to have the minimum delay. In the initialization 

procedure, we decide the delay attributes of every vertex 

and edge in the graph: the arrival time ta(v), the required 

time treq(v)and the slack time tslk(v), the edge slack time si,j, the edge propagation delay di,j. All these attributes can be 

calculated using static timing analysis and the formula we 

have denoted before. The fan-ins of a vertex are the 

former level vertexes which are connected with this 

vertex; the fan-outs of a vertex are the next level vertexes 

which are connected with this vertex. Since every edge has 

a slack time, we extract all the non-zero slack time edges 

to construct a set of sub-graphs Gsub1, Gsub2, …, Gsubn. The 

critical paths’ delay attributes are not affected when the Vt of some signal-paths on non-critical paths are changed. 

Therefore the assignment of dual Vt in the whole circuit is 

decomposed into several small problems, which have 

much smaller solution space and thus are more easier to 

get the optimal assignment of Vt. Without reiterating the 

whole circuit, we can focus solely on dealing with the subcircuits 

in which we use a new developed hierarchy 

priority based algorithm to get an optimal result faster. 

If we do not consider the condition that signal-paths in the 

same gate can have different threshold voltages, we can 

get the solution for gate-level dual-Vt optimization. 

Therefore, during the sub-graph extraction, we will only 

consider the gates in which all the signal-paths’ slack 

times are positive. It could be easily realized by mapping a 

whole gate to a single vertex in the graph. The arrival time 

of the gate is the maximum of the arrival times of the 

gate’s input pins. The required time of the gate is the 

output pin’s required time. The slack time of the gate is 

the difference between the arrival time and the required 

time of the gate. Through a little change in the algorithm, 

we can get the gate level optimization of the circuits. 

3. IMPLEMENTATION AND 

RESULTS 

The assignment algorithm has been implemented in C++ 

under signal-path level static timing analysis environment. 

The value of various transistor parameters have been taken 

from the TSMC library, the effect channel length is 

0.13µm and the gate oxide thickness is 2.4nm. The circuit 

temperature is assumed to be 110℃. The leakage power 

table and delay look up table is created by HSPICE 

simulation. In our analysis, the low threshold voltage and 

the supply voltage of the original circuits are assumed to 

be 0.2V and 1.2V, and high threshold voltage during the 

dual V t optimization is assumed to be 0.3V. 

In Figure 3, the signal-paths which are labeled out can be 

changed into high threshold voltage; meanwhile only 

NAND_A can be changed by gate level assignment. The 

leakage power saving of C17 is respectively 16.3% and 

28.7% for gate level and signal-path level optimization.

Figure 3. Changeable signal-paths in C17. 

Table. 1. shows that the gate level and signal-path level 

optimization leads to different results for leakage power 

saving of ISCAS85 circuits, and obviously more leakage 

reduction can be achieved through signal-path level 

optimization since there are actually more transistors in 

the implementation of the circuit which can be assigned to 

high threshold voltage. 

Table 1. Comparison of leakage power reduction. 

ISCAS85 

Benchmark 

Circuits 


Gate level 

Reduction 

(%) 

Signal-path 

level Reduction 

(%) 

C432 34.5 43.3 

C499 29.2 53.1 

C880 71.8 77.4 

C1355 45.2 68.1 

C1908 55.4 66.8 

C2670 77.3 85.5 

C3540 81.9 89.7 

C5315 69.6 78.5 

C6288 40.3 56.5 

C7522 69.2 75.4 

Average 57.44 69.43 

4. CONCLUSION 

In this paper we have proposed a new circuit model for 

combinational circuit during dual-V t assignment. The 

assignment algorithm is sped up by the proper extraction 

of sub graphs. By using a delay look-up table and a 

leakage power table generated by HSPICE simulation, we 

find that approximately 12% more leakage power savings 

can be achieved under the signal-path level optimization 

than the gate-level optimization. 

55 

5. REFERENCES 

[1] G. Moore, “No exponential is forever: But forever 

can be delayed,” IEEE ISSCC Dig. Tech. Papers, 

2003, pp. 20 - 23. 

[2] Kao J., Narendra S., Chandrakasan A., “Subthreshold 

Leakage modeling and reduction techniques”, 

ICCAD, 2002, pp 141 - 149 

[3] Z. Chen et. al., “0.18 um dual Vt MOSFET process 

and energy-delay measurement,” in IEDM Dig., 

1996, p. 851. 

[4] L. Wei, Z. Chen, and K. Roy, “Design and 

Optimization of Dual Threshold Circuits for Low 

Voltage, Low Power Applications”, IEEE 

Transaction on VLSI Systems, Vol.2. 17, NO. 1, 

1999, pp. 16-24. 

[5] Vijay Sundararajan, and Keshab K. Parhi, “LOW 

Power Synthesis of Dual Threshold Voltage CMOS 

VLSI Circuits”, Proc. ISLPED, 1999, pp. 363-368. 

[6] Nikhil Tripathi, Amit Bhosle, Debasis Samanta, and 

Ajit Pal; “Optimal Assignment of High Threshold 

Voltage for Synthesizing Dual Threshold CMOS 

Circuits”, VLSI Design, 2001. Fourteenth 

International Conference on ,3-7 Jan. 2001 pp. 227 - 

232. 

[7] Qi Wang; Vrudhula, S.B.K.; “Algorithms for 

minimizing standby power in deep submicrometer, 

dual-Vt CMOS circuits”, Computer-Aided Design of 

Integrated Circuits and Systems, IEEE Transactions 

on ,Volume: 21 ,Issue: 3 ,March 2002 pp. 306 - 318 . 

[8] Liqiong Wei; Zhanping Chen; Roy, K.; Yibin Ye; 

De, V.; “Mixed-Vth (MVT) CMOS circuit design 

methodology for low power applications”, Design 

Automation Conference, 1999. Proceedings. 36th ,21- 

25 June 1999 pp. 430 - 435 . 

[9] S. Devadas, A. Ghosh, and K. Keutzer, Logic 

Synthesis. New York: McGraw-Hill, 1994.

Abstract - The augmentation of transistor technologies 

with Resonant Tunnelling Diodes (RTDs) has demonstrated 

improved circuit performance and it has been claimed 

that it could be the way to extend lifetime of current technologies. 

Thus the research on circuit topologies using 

RTDs and transistors is of critical importance for these 

emergent technologies. In particular, threshold logic gates 

(TGs) and multi threshold gates (MTTGs) have been efficiently 

implemented. In this paper we propose a novel circuit 

topology to implement MTTGs which exhibits advantages 

in terms of speed and power consumption with respect 

to the previously reported circuit. A comparison 

between both topologies is carried out for an useful logic 

block: a gate which simultaneously implements the EXOR 

and the NAND functions. 

Index Terms - Resonant Tunneling Diodes, MOBILE, 

negative differential resistance, logic gates. 


Novel Improved RTD-Based Implementation of 

Multi-Threshold Logic Gates 

Héctor Pettenghi, María J. Avedillo, and José M. Quintana 

Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, 

Edificio CICA, Avda. Reina Mercedes s/n, 41012-Sevilla, SPAIN 

FAX: +34-955056686, E-mail: {hector, avedillo, josem, }@imse.cnm.es 

I. INTRODUCTION 

Resonant tunnelling diodes (RTDs) are very fast non linear 

circuit elements which have been integrated with transistors 

to create novel quantum devices and circuits. The 

incorporation of tunnel diodes into transistor technologies 

has demonstrated improved circuit performance: higher 

circuit speed, reduced component count, and lowered 

power consumption [1]. 

RTDs exhibit a negative differential resistance 

(NDR) region in their current-voltage characteristics 

(Fig. 1a) which can be exploited to significantly 

increase the functionality implemented by a single gate 

in comparison to conventional MOS and bipolar technologies, 

thus reducing circuit complexity. Circuit 

applications of RTDs are mainly based on the MOnostable-BIstable 

Logic Element (MOBILE) [2]. The 

MOBILE, shown in Fig. 1a, is a rising edge triggered 

current controlled gate which consists of two RTDs 

connected in series and driven by a switching bias voltage 

Vbias . When Vbias is low both RTDs are in the onstate 

(or low resistance state) and the circuit is monosta- 

56 

x 1 

load 

driver 

V bias 

w1 

A 21 

V bias 

RTD 1 

RTD 2 

A 1 

A 2 

IRTD (mA) 

peak 2 

current 

valley 

current 

1 

VRTD (V) 

-1 -0.5 0.5 

peak 

-1 

voltage 

1 

V out 

NDR 1 

V out 

NDR 2 

Figure 1. MOBILE circuits, a) basic MOBILE, 

b) MOBILE inverter. 

ble. Increasing Vbias to an appropriate maximum 

value ensures that only the device with the lowest peak 

current switches (quenches) from the on-state to the offstate 

(the high resistance state). Output is high if the 

driver RTD is the one which switches and it is low if it 

is the load. Peak currents are proportional to RTDs 

-2 

(a) 

(b)

areas. Assuming equal current densities, the smallest 

RTD is the one which switches. Logic functionality is 

achieved by embedding an input stage which modifies 

the peak current of one of the RTDs. An input stage 

composed of the series connection of an RTD and a 

FET transistor has been proposed [3]. This is the idea of 

the inverter MOBILE shown in Fig. 1b. Only when a 

logic one is applied to the gate of a transistor its associated 

RTD contributes to the NDR2 current. RTDs areas 

are selected such that the relation of the peak currents of 

NDR1 and NDR0 depends on whether the external input 

signal Vin is “1” or “0”. For Vbias high the output 

node maintains its value even if the input changes. That 

is, this circuit structure is self-latching allowing to 

implement pipeline at the gate level without any area 

overhead associated to the addition of the latches which 

allows very high throughtoutput. 


A 

0.4 

0.2 

B 

0.4 

0.2 

V bias 

By using as many input stages as input variables, 

Threshold Gates (TGs) [4] can be realized with the 

same operating principle [3]. TG design style is a well 

recognized powerful alternative to the standard logic 

design because of the intrinsic complexity of the functions 

performed by TGs allowing realizations that 

require less threshold gates than standard threshold 

logic. Recently, a circuit structure for Multi-Threshold 

Gates (MTTGs) [5], a generalization of TGs able to 

implement even more complex functions than TGs, has 

been proposed using three or more series connected 

RTDs [6]. 

II. CIRCUIT TOPOLOGIES 

Fig. 2a shows the circuit diagram of a previously 

reported two-input logic block implementing simultaneously 

the NAND and the EXOR operations [7] which 

RTD NDR 

RTD 

0 

0 

0 

A+0.4 

A 

A+0.1 

y 2 

NDR 

1 

NDR 

2 

0.2 0.2 0.2 0.2 

w1 w1 RTD 

1 

w2 w2 w1 w1 

y1 w 2 

w 2 

RTD 

2 

(a) 

c d a b 

A 

B 

V bias 

A+0.4 

A 

RTD 

1 

y 2 

y 1 

A+0.1 

RTD 

2 

Figure 2. Two input NAND-EXOR gate, a) implemented with previously reported topology, b) implemented with 

new proposed topology. RTD areas are expressed as area factors; an area factor of 1 is equal to an area of 10µm 2 

Figure 3. Simulation results for the proposed design showed in Fig. 2b. 

57 

(b) 

V bias 

A 

B 

y 2 

y 1

employees the topology of MTTGs reported in [6]. Fig. 

2b depicts the new proposed realization. In both circuits 

the parameter A, determining the area of some of the 

RTDs, is selected according to the technology and to the 

required speed-power trade-offs. Circuit in Fig. 2a operates 

on the basis of current comparison: the NDR with 

the lowest peak current switches off. Inputs (A and B) 

modulate the peak currents of both the down (NDR2 ) 

and the middle (NDR1 ) NDRs, although by a different 

amount since the areas of the RTDs of the input stages 

are 2 µm and 4 respectively (see caption to Figure 

2). Thus, concerning and , the same 

result of the current comparison could be obtained if 

only is modulated with input stages of 2 

RTDs. That is what has been done in Fig. 2b (input 

stages a and b). However, area relationships of 

and with must be kept for circuit in Fig 

2b to implement the same functionality that circuit in 

Fig. 2a. To achieve this, 2 input stages common to 

both and have been added to the proposed 

circuit (input stages c and d). Note that the area of 

some RTDs is reduced with respect to the solution in 

Fig 2a, thus allowing to reduce the width of their associated 

transistors since they are sized such that RTDs are 

the current limiting devices in the series connection of 

the RTD and the transistor. This idea is the rationale for 

a new topology for MTTGs. Fig. 3 shows simulation 

results for the proposed new design. Correct operation 

(y2 implements NAND and y1 implements EXOR) is 

obtained. 

2 

µm 2 

NDR1 NDR2 NDR1 µm 2 

NDR1 NDR2 NDR0 µm 2 

NDR1 NDR2 Maximum frequency (MHz) 


III. COMPARISON OF ARCHITECTURES 

In order to compare both circuit architectures we have 

carried out simulations of three stage chains of these 

NAND-EXOR gates. The study has been done with 

w1 = 10µm , w2 = 2µm for circuit in Fig 2a and 

w1 = 5µm , w2 = 2µm for circuit in Fig 2b. 

L = 0,6µm 

for all transistors. These sizes have been 

selected to maximize the operating frequency. In all the 

simulations LOCOM models for RTDs and transistors 

have been used [8]. 

Fig. 4 shows the maximum operating frequency for 

different values of the bias voltage taking the RTD area 

A as a parameter. The results in Fig. 4 indicate that with 

the new idea faster designs can be obtained. Also, for 

operation frequencies which can be achieved with both 

architectures, the new one requires smaller A values. 

Fig. 5 shows the power consumption versus operating 

frequency for different A values. Due to the form for the 

maximun operating frequency versus Vbias (see Fig. 4), 

with two values of V bias resulting in the same operation 

frequency, two branches are observed in these representations. 

For both circuits power increases with the area factor 

A but the circuit incorporating the new idea exhibits 

less power consumption than the respective original one 

with the same A value. 

Finally, Fig. 6 depicts power consumption versus the 

operating frequency. Designs with the smallest A value 

(and so smallest power consumption) achieving the 

required operating frequency have been selected. The 

Vbias (V) 

Figure 4. Maximum frequency versus bias voltage for different A values. 

Original designs: marks over dashed line 

New designs: marks over solid line 

58

Power (mW) 

Figure 6. Power consumption versus maximum 

operating frequency. 

bias voltage is fixed at 0.7 volts. It is clear that the new 

idea design has less power consumption than the original 

one. 


IV. CONCLUSIONS 

Maximum frequency (MHz) 

A new RTD-based circuit topology for MTTGs has 

been proposed. The comparison to a previously reported 

one by means of an NAND-EXOR gate shows significant 

improvements. The new design can operate at higher frequency 

and consumes less power. 

ACKNOELEDGEMENT 

This effort was partially supported by the Spanish Government 

under project TEC2004-02948/MIC. 

REFERENCES 

[1] P. Mazumder, S. Kulkarni, M. Bhattacharya, J.P. Sun 

and G.I. Haddad, “Digital Circuit Applications of Resonant 

Tunneling Devices”, Proceedings of the IEEE, 

Vol. 86, no. 4, pp. 664-686, April 1998. 

[2] K.J. Chen, K. Maezawa and M. Yamamoto, “InP- 

Power (mW) 

59 

Figure 5. Power consumption versus 

maximum operating frequency for different 

A values. 

Original designs: marks over dashed line 

New designs: marks over solid line 

Maximum frequency (MHz) 

Based High Performance Monostable-Bistable Transition 

Logic Elements (MOBILEs) Using Integrated 

Multiple-Input Resonant-Tunneling Devices,” IEEE 

Electron Device Letters, Vol. 17, no. 3, pp. 127-129, 

March 1996. 

[3] C. Pacha et al., “Threshold Logic Circuit Design of 

Parallel Adders Using Resonant Tunnelling Devices,” 

IEEE Trans. on VLSI Systems, Vol. 8, no. 5, pp. 558- 

572, Oct. 2000. 

[4] S. Muroga, Threshold Logic and Its Applications, New 

York: Wiley, 1971. 

[5] D. R. Haring, “Multi-Threshold Threshold Elements”, 

IEEE Trans. on Electronic Computers, Vol. EC-15, 

No. 1, pp. 45-65, February 1966. 

[6] M.J. Avedillo, J.M. Quintana, H. Pettenghi, P.M. 

Kelly, and C.J. Thompson, “Multi-threshold Threshold 

Logic Circuit Design Using Resonant Tunneling 

Devices,” Electronics Letters, Vol. 39, pp. 1502-1504, 

2003. 

[7] H. Pettenghi, M.J. Avedillo, J.M. Quintana, “Useful 

Logic Blocks Based on Clocked Series-Connected 

RTDs” Proceedings. IEEE Conference on Nanotechnology, 

pp. 593-595, 2004. 

[8] W. Prost et al., EU IST Report LOCOM no. 28 844 

Dec. 2000.


VARIATION OF FLASH MEMORY THRESHOLD 

VOLTAGE CORRELATED WITH APPLIED VOLTAGE 

SLOPE IN FOWLER NORDHEIM ERASE MODE 

Valéry Bouquet 1,2 , Pierre Canet 1 , Frédéric Lalande 1 , Jean Devin 2 , Bruno Leconte 2 , Nicolas Mariéma 1 

(1) L2MP-UMR CNRS 6137, IMT Technopole de Château Gombert, 13451 Marseille Cedex 13 

(2) ST-Microelectronics, ZI de Rousset BP 2, 13106 Rousset Cedex, FRANCE 

E-mail: valery.bouquet@l2mp.fr 

ABSTRACT 

In order to pre-evaluate the necessary time needed to 

write a flash cell memory, we use a simplified expression 

for the Fowler Nordheim injecting current during the 

erase mode, which allows us to find a relationship 

between the applied voltages and the resulting threshold 

voltage. We show in this study that the absolute value of 

the derivative of the threshold voltage is equal to the 

positive signal slope applied on the control gate. We 

validate this assumption by measurements on samples 

provided by STmicroelectronics 


The flash memory is a non-volatile memory made of one 

stacked transistor with an isolated poly silicon gate called 

floating gate which lead to a small cell’s area and a high 

integration density. In order to pre-evaluate the necessary 

time needed to erase a Flash cell memory, we try to 

evaluate the threshold voltage variation depending on the 

applied voltages. 

2. FLASH MEMORY 

The flash memory is a none volatile memory which stores 

and keeps the binary information without any external 

electrical supply. The flash memory is made of one 

stacked transistor with an isolated poly silicon gate called 

floating gate (Fig. 1a) [1]. We define the different 

capacitances : C PP is the inter poly silicon capacitance 

between the floating gate and the control gate, C ox is the 

capacitance between the floating gate and the channel, 

IFN is the injected current generator . 

(a) (b) 

Figure 1. (a) Structure of the stacked transistor 

with an isolated polysilicon floating gate (b) 

Electrical equivalent schema of the flash memory. 

The floating gate charge, Q FG, impacts the threshold 

voltage of the transistor to determine two binary states. 

60 

Q 

V − 

FG 

(1) 

T = VT 

0 

CPP 

Where VT is the threshold voltage after injection of 

charge ; VTo is the initial threshold voltage without 

injected charge in the floating gate ; QFG is the charge 

injected in the floating gate. 

Two mechanisms are used to inject charges through the 

thin tunnel oxide in the floating gate : the positive charge 

injection is led by a Fowler Nordheim mechanism (FN) 

[2] and the negative charge injection is led by channel hot 

electron mechanism (CHE) [3, 4]. The positive charge 

injection is called the erase mode and the negative charge 

injection is called the programming mode. 

To reach an erased threshold voltage, we apply a negative 

signal between the control gate and the well to establish a 

high electrical field across the thin tunnel oxide. By this 

way, a positive charge is injected in the floating gate by 

Fowler Nordheim mechanism [2]. 

3. MODELING OF ERASING 

The equivalent electrical schema is given in figure1b 

where CPP is inter poly silicon capacitance between the 

floating gate and the control gate, Cox is the capacitance 

between the floating gate and the channel. The charge 

injection is controlled by a Fowler Nordheim injecting 

current given by the following equation [2]. 

2 B 

(2) 

IFN 

= A × STUN 

× ETUN 

× exp( ) 

ETUN 

Where A (AV -2 ) and B (Vm -1 ) are the Fowler Nordheim 

parameters ; STUN is the tunnel array ; ETUN is the electrical 

field across the thin tunnel oxide. 

Using the electrical scheme (Fig. 1b) and the Kirchoff law, 

we obtain the expression (3) where VFG is the floating gate 

potential and VCG is the control gate potential. 

dV dV 

( C 

(3) 

PP 

dt dt 

FG CG 

I FN = COX 

+ CPP 

) × − × 

Without injection (I FN=0A), we introduce the coupling 

ratio, α G (4a). This parameter permits to establish an 

expression of the variation of the floating gate potential in 

function of the variation of the control gate potential (4b).

PP 

α G = 

COX 

+ CPP 

(4a) 

dVFG dVCG 

= αG 

× 

(4b) 


C 

dt dt 

When injection occurs the injected charges moved the 

floating gate potential and the expression (4b) will be not 

valid. 

In order to reach the given erase floating gate voltage, a 

high coupling ration permit to decrease the erase applied 

voltage. When the coupling ratio increases, the tunnel 

oxide field increases, and in the same time the tunnel 

oxide voltage. Moreover the injected current is more 

important, and the charges are injected faster. So it’s 

possible to decrease the erase time. But this increase of the 

coupling ratio implies a worse reliability[]. 

In order to exhibit an analytical solution, we solve 

equation (3), by using a linear simplified expression of the 

Fowler Nordheim current (5) as shown in figure 2. 

Injected current (A) 

0 

2 .10 13 

2 .10 13 

4 .10 13 

IFN() x 4 .10 13 

IFN() x 

6 .10 13 

IFNl( x) 

6 .10 13 

IFNl( x) 

8 .10 13 

8 .10 13 

0 

VS 

g = dIFN 

g = 

dV 

dIFN 

g = 

dV 

dIFN 

g = 

dV 

dIFN 

dV 

IFN theoretical 

IFN simplified 

1 .10 

14 12 10 8 6 4 2 0 

12 

− 1 10 12 − 

× 

1 .10 

14 12 10 8 6 4 2 0 

− 14 

x 

Tunnel oxide voltage (V) 

0 

12 

− 1 10 12 − 

× 

− 14 

x 

Tunnel oxide voltage (V) 

0 

Figure 2. Simplification of the Fowler Nordheim 

current by introducing VS as threshold potential 

and g as the current variation for V >V S 

IFN S FG 

= g × ( V − V ) 

(5) 

By this way we express the expression of the floating gate 

potential where t s is the time when the injection occurs : 

V 

FG 

1 dV ⎧ 

⎫ 

CG 

− g × ( t − ts) 

(6) 

= VS 

+ ( × CPP 

) × ⎨1 

− exp 

⎬ 

g dt ⎩ COX 

+ CPP 

⎭ 

So we can express the maximal floating gate potential 

when permanent regime is established as experimental 

conditions permit it : 

1 dVCG 

V FGMAX 

= VS 

+ ( × C 

g dt 

PP 

) 

We can now express the variation of threshold voltage 

during an erase permanent regime (8). 

PP 

PP 

(7) 

dVT 

1 

1 

(8a) 

= − × I FN = − × g × ( VS 

−V 

FGMAX ) 

dt C 

C 

dt 

dV 

= − 

(8b) 

dt 

dVT GC 

61 

We show that the absolute value of the derivative of the 

threshold voltage during erase permanent regime is clearly 

equal to variation of the control gate potential. We can 

notice that this equality is independent of the technological 

parameters of the cell as the coupling ratio, α G. But the 

time to reach permanent regime will depend of 

technological parameters. 

4. MEASUREMENTS 

We designed three cells to reach different coupling ratios, 

by adjusting the inter poly capacitive areas of the cell. 

These cells were realised by Stmicroelectronics. The 

technology used imposes all the oxide thickness : tunnel 

oxide thickness, t ox

eaches his maximum and constant value, the injection 

current is maximal and constant. The permanent regime is 

established and the absolute value of the variation of the 

threshold voltage, is clearly the same and equal to positive 

signal slope as (8) . 

Figure 4. Threshold voltage evolution in erase 

mode for three memory cells with different 

coupling ratios (▲ cell A, α G=0.61 ; ■ cell B, 

α G=0.71 ; ● cell C, α G=0.78 ) by three positive 

signal slopes (0.625V/ms ; 1.25V/ms ; 2.5V/ms). 

Moreover, we observe that for the final threshold voltage 

value depends on coupling ratio and depends on the 

applied signal slope, table 1. The technological limitation 

(maximum allowed voltage) and the expected threshold 

voltage will conduct to the choice of the erase signal slope 

and of the coupling ratio giving the shorter erasing time. 

Table 1. Final threshold voltage for three cells with 

different coupling ratio (cell A, αG=0.61 ; cell B, αG=0.71 ; cell C, αG=0.78 ), in erase mode by three positive signal 

slopes (0.625V/ms ; 1.25V/ms ; 2.5V/ms) at the same final 

bulk-control gate potential. 


Cell A Cell B Cell C 

0.625V/ms 3.4V 2.8V 2.1V 

1.25V/ms 3.7V 3.1V 2.5V 

2.5V/ms 4V 3.4V 2.75V 

5. CONCLUSION 

In this study, we show with a very simple modelling of the 

Fowler Nordheim current, that the derivative of the 

threshold voltage is opposite to the applied signal slope 

when the permanent regime is established with a constant 

floating gate potential and constant injected current. 

Neglecting the transitional domain, it is very easy to 

evaluate the erasing time necessary to reach a given 

threshold voltage depending on applied signal slope. 

A better evaluation of this erasing time needs to simulate 

the transitional behaviour of the cell. 

62 

6. REFERENCES 

[1] W.D. Brown, J.E. Brewer, Non Volatile Semiconductor 

Memory Technology, IEEE Press (1998). 

[2] R. H Fowler and L. Nordheim, Proc. Soc. London 

Ser., A119 (1928) 173. 

[3] B. Eitan, D. Froham-Bentchkowsky, Hot-Electron 

Injection into the Oxyde in N-Channel MOS devices, 

IEEE Trans. Electron Devices, ED-28 n°3 (1981) 

328-340. 

[4] C. Hu, Lucky Electron Model for Channel Hot- 

Electron Emission, IEDM Tech. Dig., (1979) 22. 

[5] P. Canet, R. Bouchakour, F. Lalande, J.M. Mirabel, 

EEPROM Cell Design : Paradoxical Choice of the 

Coupling Ratio, J. Non-Cryst. Solids, vol. 322 (2003) 

p.246-249. 

[6] V. Bouquet, P. Canet, F. Lalande, R. Bouchakour, 

J.M. Mirabel, Non Volatile Memory Cell Design : 

Coupling Ratio Impact On tunnel Oxide Reliability, 

J. Non-Cryst. Solids (2005) to be published. 

[7] P. Canet, F. Lalande, J. Razafindramora, V. Bouquet, 

J. Postel, R. Bouchakour, J.M. Mirabel, Integrated 

Reliability in Non Volatile Memory Cell Design, 

NVMTS’2004 5th Annual Non-Volatile Memory 

Technology Symposium, Orlando, Florida, 

November 15-17 (2004) proceeding CD.


TOWARDS A UNIFIED TOP-DOWN DESIGN 

FLOW FOR FULLY DIFFERENTIAL LOGIC 

BLOCKS WITH IMPROVED SPEED AND NOISE 

IMMUNITY 

Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici 

Microelectronic Systems Laboratory (LSM) 

Ecole Polytechnique Fédérale de Lausanne (EPFL) 

Batiment ELD Station 11, CH-1015 Lausanne, Switzerland 

E-mail: {ilhan.hatirnaz, stephane.badel, yusuf.leblebici}@epfl.ch 

ABSTRACT 

A new top-down design flow (RTL-to-GDSII) is 

proposed for achieving high-performance and noiseimmune 

designs consisting of differential logic blocks. 

The differential building blocks are based on the currentmode 

logic (CML), which offers true differentiality with 

low-swing signalling, switching-independent constant 

power dissipation and very high-speed operation. The 

goal of this flow is to allow effective cancellation of 

inductive and capacitive noise in high-speed on-chip 

interconnect lines using a simple generic interconnect 

architecture. 


Currently, the implementation of chip design is an 

iterative process guided by the design automation tools 

and the conventional linear design flow. In the ideal case, 

the limiting factor in achieving the design goals would 

come only from the physical limitations of the process 

technology used. However, especially starting with the use 

of deep sub-micron technologies, the design flow and the 

electronic design automation (EDA) tools started 

becoming the limiting factors of what final performance 

can be achieved. 

There is a number of reasons behind this fact. One reason 

is the increasing complexity of the designs, which, can not 

be handled by currently available tools. Furthermore, 

traditional VLSI design flows may mask some problems, 

which only show up during or after the final steps of the 

flow (for example, after the detailed routing is finished), 

where, in some cases, a dramatic change at the high-level 

description of the circuit might be necessary. 

In addition to the increasing design complexity, the 

fabrication costs of ASICs are rising rapidly as the latest 

technologies with much smaller feature sizes are offered. 

This leads to a tendency from standard-cell based design 

to more soft-programmable design solutions, like FPGAs 

and/or processor-based solutions, where the mask-cost is 

reduced to minimum. Although these solutions help 

reducing the total cost and time-to-market, they are not 

able to offer comparable performance as ASIC-based 

solutions. Recently, to address this problem, structured- 

63 

ASICs (SA) were introduced [1]. Structured ASICs are 

expected to fill the gap between FPGAs and standard-cell 

based design approaches. Structured ASICs are based on 

a predefined and pre-built logic fabric, which is fabricated 

including the interconnect structure consisting of a number 

of the bottom metal layers (for example up to Metal3 or 

Metal4), where the rest of the metal layers are to be laid 

out later for having the design mapped to the wafer. These 

wafers are stored as base wafers until ordered by 

customers. 

This project aims to find a generic solution to signal 

integrity problems and a differential-design flow that 

employs a fully differential (differential inputs-differential 

outputs) standard cell family based on current-mode logic 

(CML). This paper introduces the first step into the search 

for a complete solution. Proposed is a flow for the 

implementation of a design using differential gates or 

structures, where the signal integrity issues are to be 

addressed early at the design flow, even in the library 

modelling phase. The target device of this flow can be 

either a standard-cell library or a structured-ASIC based 

solution; in this paper only implementation targeting a cell 

library is discussed. The benefits of such a scheme is the 

regularity and hence the increased predictability of the 

final design, and additionally, shifting the limitations from 

the limits of the tools or flows to the process technology 

limits. These goals, if achieved, would prevent the underutilization 

of the very deep sub-micron (VDSM) 

technologies, which means that the designers would be 

able to achieve higher clock speed using the same 

technology at either an acceptable or no additional cost, 

resulting in a faster time-to-market. 

The remainder of this paper is organized as follows: The 

proposed differential design flow is introduced in Section 

2, including the individual steps and the CML-based cell 

library. In Section 3 the test chip including the blocks 

designed using this and regular design flows is presented., 

followed by the conclusions. 

2. DIFFERENTIAL DESIGN FLOW 

There are a number of well-known advantages of using 

differential signalling in high-performance systems in 

terms of signal integrity and noise immunity. The primary

disadvantage of differential signalling is the increased 

number of traces per bit of information, which 

proportionally increases the cost of the associated routing 

and the total silicon area, which, in fact, constitutes the 

main reason for making use of differential signalling and 

differential gates only in some very high performance 

designs ( for example, microprocessors [2] ) and only in 

specific cases, like routing bit lines of RAM-structures. 

Therefore, there is not as much interest and support from 

the EDA world for differential designs as there is for 

conventional single-ended cell libraries. There are no 

commercial tools that provide differential logic synthesis, 

moreover, conventional hardware description languages 

do not support differential design entry. 

Figure 1 The proposed RTL-to-GDSII differential 

design flow. It should be noted that ‘S’ stands for 

single-ended and ‘D’ stands for differential in the 

descriptions of the different netlists. 

2.1 Logic Synthesis 

The proposed design flow is given in Figure 1. The main 

pieces of this flow are commercially available EDA tools 

and a number of netlist conversion scripts. The main input 

to the flow is a synthesizable RTL description of the 

design. The RTL code does not need to include any 

knowledge of differentiality, it only describes the design 

in a single-ended manner. 


64 

Even a fully characterized differential cell library 

(differential inputs-differential outputs) is available, 

current synthesis tools are not able to provide mapping of 

nets to differential inputs pairs of gates from this 

differential library. To overcome this issue and also make 

use of the complementary nature of the differential cell 

outputs, a new synthesis library is extracted from the fully 

differential library, where this new library consists of 

single-ended input/differential output (SD) gates. The 

logic synthesis tool (Synopsys Design Compiler [3]) is 

able to benefit from the differential outputs of the logic 

gates offered by the SD cell library, i.e., the tools uses 

either both signals (inverted and non-inverted) or one of 

them without needing to invert the complementary net of 

the pair. 

After the mapping process is finished, the synthesized 

circuit is written out as a Verilog netlist. This netlist, 

consisting of SD gates, are then converted first to a singleended 

input/single-ended output netlist and then to a fully 

differential Verilog netlist using the netlist conversion 

scripts. The observe if the same functionality is kept for all 

the different netlist of the design, these scripts also provide 

a run file to be fed to the equivalency checker tool 

(Synopsys Formality [3]) with the Verilog netlists under 

comparison. 

During logic synthesis, it can happen that only one of the 

complementary outputs (either Y or Y´) drives an input of 

any other gate, whereas the other signal stays floating, 

because the inputs are only single-ended. This means that 

the loading of the complementary nets in one differential 

pair might not be the same. During the SD-to-DD Verilog 

netlist conversion all the SD gates are replaced with their 

DD counterparts. Hence, both signals of any output pair 

will have the same fan-out. If routed together as a pair, the 

differential nets will be exposed to the same wire load, and 

therefore, exhibit similar timing behaviour. 

2.2 Placement and Routing 

As in the logic synthesis case, tools for routing differential 

signals as a differential wire pair do not exist. Some of the 

currently available routers can route signals together at a 

specific distance from each other, as desired for 

differential pair routing, but, this feature can be applied 

only to few user-defined nets. 

There is not much previous work available on differential 

routing; the existing solutions are based on a routing the 

differential pairs as one wider net, where the width of this 

“fat” wire is equal to the sum of the individual widths of 

each net and the spacing between them. This method was 

introduced in [4] to be used in multi-chip modules 

(MCM), and it was adapted to be part of a design flow in 

[5], in order to obtain secure hardware implementations of 

crypto algorithms against the differential power analysis 

(DPA) attacks. 

The inputs to the placement-and-routing (P&R) step are 

the Verilog netlist consisting of SS-gates and a LEF file 

(Library Exchange Format by Cadence [6]) representing 

the “fat-wire” technology and the cell library, in which,

each gate has single-ended IO pins. These pins are defined 

as “virtual pins” located on a higher level of metal. The 

regular P&R flow is followed until a DRC clean and 

logically verified layout is obtained. The output of this 

step is a DEF file (Design Exchange Format by Cadence 

[6]) describing the final circuit of SS-gates and wide-wire 

interconnections. The next step is to run the script, which 

replaces each SS-cell with its counterpart from the fully 

differential DD library, and splits the “fat wires” into the 

two nets of regular wire width dictated by the original 

technology. Then, to complete the connections between 

the differential IO pins and the differential nets, the fully 

differential DD Verilog netlist is read and a corresponding 

connection mask is applied to between every pin pair and 

the so-called virtual pins. The final step is to verify the 

interconnection network by either running LVS or using 

an equivalency checker tool. 

The proposed method involves a more detailed work with 

less constraints on the cell design compared to other 

methods in previous works, serving the goal of achieving 

a noise-immune design solution. During placement the 

tool is allowed to use any symmetry for the cells, which 

might save a lot of area. The method allows the designer 

to run clock tree synthesis, in fact, it does not prevent the 

tool to apply any ECO changes that might be necessary. 

Moreover, it can be applied to existing differential cell 

libraries with little additional work. 

2.3 The Differential Cell Library 

A fully differential cell library has been designed and 

characterized to be used in logic synthesis and P&R. The 

cells are based on current mode logic (CML), where, the 

operation is based on the principle of re-directing (or 

switching) the current of a constant current source through 

a fully differential network of input transistors, and 

utilizing the reduced-swing voltage drop on a pair of 

complementary load devices as the output. CML circuits 

have been introduced as very high speed design 

alternatives that offer robust operation, reduced power 

supply/common mode noise, and improved immunity 

against process variations [7]. The switching delays can be 

significantly reduced due to limited output voltage swing, 

while fully differential inputs and outputs contribute to 

improved noise immunity and robustness. In addition, the 

power dissipation of the MCML gate remains virtually 

independent of the switching frequency, which means that 

the power dissipation at higher operating frequencies is 

actually lower than that of an equivalent CMOS gate 

under the same output load conditions. 

Figure 2 shows a generic 3-input CML gate. The transistor 

M1, driven by a fixed voltage (“nbias”), provides the 

current for the circuit, and the transistors M2 and M3, 

driven by another fixed voltage (“pbias”) act as resistors. 

The generic function of this structure is Y = AB + A'C 

( Y’= [A + B’] [A + C’] ), it corresponds to a multiplexeroperation. 

All the 2-input logic functions, including XOR 

operation and some of 3-input logic functions can be 

realized using only one generic CML gate, by assigning 

the input pairs to appropriate logic levels. 


65 

Figure 2 Transistor-level view of the generic 

CML gate. 

The CML cell library consists of a limited number of basic 

logic gates, including buffers, latches and resettable flipflops. 

Each cell is designed with six different drive 

strengths. Typical CML two-input gate delays are found to 

be between 90ps, where a full-adder delay is 

approximately 50ps. 

Figure 3 The layout-view of the generic CML 

gate, including two neighboring cells of the same 

type, which do not have all the physical layers 

visible. 

The layout view of the generic CML gate is given in 

Figure 3, with two neighboring instances of the same cell 

together. The total size of the given layout is 22.0 um x 

24.5 um, where one cell has a height of 22.0 um and a 

width of 8.5 um. The cells use up only the lowest two 

metal layers, hence, the rest of the upper levels are free for 

routing purposes. . 

The main contribution of CML gates with respect to 

predictability of the proposed flow is based on the fact that 

there is virtually no change in current drawn by the gate,

even after switching of inputs. This eases overcoming 

some signal integrity problems like IR-drop and electromigration 

(EM), just by making them easier to calculate or 

to be known at the very first steps of the design flow. 

3. HARDWARE IMPLEMENTATION 

To test and to evaluate the proposed design flow, a test 

chip is produced which consists of three different 

realizations of the same RC4 block [9] as listed below: 

1. RC4_ART_SER: Implemented using a 

commercially available single-ended CMOS 

standard-cell library. 

2. RC4_CML_FDF: Implement using the fulldifferential 

cells, placed-and-routed according to 

the proposed flow. 

3. RC4_CML_SDF: Implemented using the CML 

based fully differential library, same cell 

placement as in RC4_CML_FDF, without fulldifferential 

routing. 

The layout of the test chip is shown in Figure 4. One key 

observation is the difference in size between the singleended 

implementation ‘RC4_ART_SER’ (located at the 

top-left corner) and the differential implementations. 

RC4_ART_SER occupies an area of 400um x 400um, 

whereas the differential circuits have the dimensions of 

approximately 1mm x 1mm. This difference is caused 

mainly by the area difference of the cells from both 

libraries and of course the need for routing two nets 

instead of one. In return, it is expected that the fully 

differential version of the circuit exhibits significantly 

improved signal integrity characteristics, and hence, 

higher operating speed. Complete experimental 

characterization of the circuits will be done following the 

fabrication of the test chip. 

Figure 4 The top-level layout of the test chip 

designed with 0.18um CMOS technology. 


66 

Figure 5 A closer view to the layout of the RC4 

block that is routed fully differential wiring. The 

cell layouts are omitted for better visibility of the 

differential routing. 

4. CONCLUSION 

In this paper a design flow for implementing fully 

differential designs is proposed. It is shown that following 

this flow leads to successful final layouts which are DRC 

and LVS clean. Next step in this work is to show that the 

signal integrity issues encountered with the deep submicron 

technologies can be decreased to an acceptable 

level. 

5. REFERENCES 

[1] B.Zahiri, Structured ASICs: Opportunities and 

Challenges, Proceedings of ICCD’03, 2003. 

[2] P. E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. 

Gowan, R.L. Allmon, High Performance 

Microprocessor Design, IEEE JSSC, vol. 33, Issue 5, 

May, 1998, pp. 676-686. 

[3] Synopsys, Inc., http://www.synopsys.com 

[4] Loy, J.; Garg, A.; Krishnamoorthy, M.; McDonald, 

J., Differential Routing of MCMs-CIF: the ideal 

bifurcation medium, Electrical Performance of 

Electronic Packaging, 2004. IEEE 13th Topical 

Meeting on 25-27 Oct. 2004 Page(s):135 – 138. 

[5] Tiri, K.; Verbauwhede, I., A VLSI design flow for 

secure side-channel attack resistant ICs, DATE 2005 


Page(s):58 - 63 Vol. 3. 

[6] Cadence Design Systems, http://www.cadence.com 

[7] P. Heydari, Design and Analysis of Low-Voltage 

Current-Mode Logic Buffers, 4 th International 

Symposium on Quality Electronic Design, March 

2003. 

[8] I. Hatirnaz, Y.Leblebici, Twisted-Differential On- 

Chip Interconnect Architecture for 

Inductive/Capacitive Crosstalk Noise Cancellation, 

Proceedings of Int. Symposium on System-on-Chip 

(SOC), Finland, 2003. 

[9] P. Hartmann, S. Witt, Vergleichende Analyse und 

VHDL-basierte Implementation von 

Zufallszahlengeneratoren auf Chipkarten, 

Studienarbeit, University of Hamburg, 2001.

A High-Speed Scalable Shift-Register Based On-Chip 

Serial Communication Design for SoC Applications 


I-Chyn Wey, You-Gang Chen, Chia-Tsun Wu, Wei Wang, and An-Yeu Wu 

Graduate Institute of Electronics Engineering and Department of Electric Engineering, National Taiwan University 

No.1, Sec. 4, Roosevelt Road, Taipei 106, Taiwan 

Abstract—In this paper, a high-speed, scalable 

on-chip serial transmission design is proposed to 

provide 2Gb/s transmission bandwidth for SoC 

applications. By using the dynamic control 

technology and the single-phase pulse-triggered 

TSPC shift register design, we can provide 

high-speed on-chip serial transmission. Moreover, 

the shift register design is a scalable design. By 

using the proposed method, we can provide 3 times 

wider bandwidth as compared to the prior art 

design [6]. 


System-on-a-chip (SoC) designs provide possible and 

economical method to integrate complex systems on a single 

chip. However, the exponential growth in speed and 

integration levels of intellectual properties (IPs) has 

increased the interconnection complexity, which dominates 

the performance of SoC design [1-6]. As a result, On-Chip 

Networks (OCN) have been actively studied recently to 

reduce the wire complexity and solve the problems of 

scalability in the bus-based SoC communication [2-4]. On 

the other hand, serial communication is the key technology 

to overcome the wire complexity to make the 

implementation of OCN is possible and practical [5,6]. 

However, the bandwidth of OCN transmission will be 

limited by the serial communication clock frequency. 

High-speed design becomes the critical demand in the 

on-chip serial communication architecture. Therefore, we 

propose a new technology to overcome the speed bottleneck 

in the on-chip serial communication design. 

As illustrated in Fig. 1(a), on-chip parallel-shared bus 

communication requires enormous wire interconnections 

between IPs. In our proposed on-chip high-speed serial 

communication architecture, as illustrated in Fig. 1(b), wire 

complexity can be greatly reduced by 90% and the speed 

bottleneck can be overcome to provide 2Gb/s transmission 

bandwidth. Moreover, the proposed design can be easily 

scalable for higher-bandwidth designs. 

II. PROPOSED ON-CHIP SERIAL 

COMMUNICATION DESIGN 

The proposed high-speed on-chip serial communication 

architecture is constructed by the transmitter with parallel to 

serial converter and the receiver with serial to parallel 

converter, as illustrated in Fig. 2(a). 

Email: archi@access.ee.ntu.edu.tw 

67 

IP0 

Transmit Data Receive Data 


IP3 

IP0 


IP1 



IP2 

(a) On-Chip Parallel-Shared Bus Communication 

High-Speed On-Chip Serial 

Communication Interface 



IP3 


IP1 






IP2 


(b) On-Chip High-Speed Serial Communication 

Arbiter 

Fig. 1: Comparisons of wire complexity between the 

parallel-shared bus and the proposed on-chip high-speed 

serial communication architecture 

A. The Proposed Transmitter Design 

The transmitter, as illustrated in Fig. 2(b), is composed 

of the ring oscillator, the shift register, and the control circuit. 

The ring oscillator is used to generate the high-speed clock 

(int_clk) to synchronize the serial transmission data. In our 

design, the ring oscillator can oscillate above 2 GHz to 

provide high transmission bandwidth. In [6], the speed 

bottleneck in the transmitter is limited by the control circuit 

and the counter because of critical synchronization timing 

constraints. Therefore, we propose the shift register based 

transmitter to overcome the speed bottleneck. 

In the transmitter, the number of serial transmission bits 

is determined by the stage of shift register. In the shift

IP1 


Parallel-to-Serial 

Converter 

Serial-to-Parallel 

Converter 

Int_clock (Transmit) Int_clock (Receive) 

On-Chip Serial 

Communication 

Transmitter 

ext_clk 

Ext_clock 1 

Control 1 


Communication 

Receiver 


D 

CLK 

Q 

control 

Control 2 

Ext_clock 2 

IP2 


Parallel-to-Serial 

Converter 


Communication 

Transmitter 

High-Speed Serial Data Transmission (Critical Wire Line) 

d1 d2 d3 d4 

D 

CLK 

Q D 

CLK 

Serial-to-Parallel 

Converter 

Int_clock (Transmit) Int_clock (Receive) 

Q D 

CLK 

int_clk2 int_clk 

Q D 


Communication 

Receiver 

(a) Proposed High-Speed On-Chip Serial Communication Architecture 

CONTROL CIRCUIT 

d10 

control 

Q 

RING OSCILLATOR 

D 

CLK 

int_clk1 int_clk4 

d9 

Q 

D 

CLK 

d8 

Q 

D 

CLK 

SINGLE-PHASE SHIFT-REGISTER 

int_clk3 

(b) On-Chip Serial Communication Transmitter 

int_clk12 int_clkre 

int_clk11 int_clk14 

Dummy 

Cell 

int_clk13 

(c) On-Chip Serial Communication Receiver 

Fig. 2: The proposed high-speed, reliable on-chip serial 

communication design. 

register, each single bit is constructed by the Pulse-Triggered 

True-single-phase- clocking D Flip-Flop (PTTFF) [7] with 

delay buffer. The PTTFF is adopted as fast register with 

shorter set-up time. In this paper, the shift register is 

designed to be single-phase, which is realized by connecting 

the external-clock (ext_clk) as the shift register input. The 

single-phase design can provide wider synchronization 

timing constraint tolerance to meet the high-speed demand. 

Moreover, the single phase can make the shift register to be 

scalable. 

The control circuit is used to synchronize the int_clk 

between transmitter and receiver. The oscillator starts with 

the positive edge of ext_clk and stops with a fixed number of 

shift register latency. In the proposed dynamic control circuit, 

the control signal can be fast precharged to “high” to trigger 

the int_clk. As the final stage shift register output (d10) 

changes from logic ”0” to logic “1”, the control signal will 

be fast pulled down to stop the int_clk. 

B. The proposed Receiver Design 

The receiver is constructed by the ring oscillator with 

nearly the same frequency as int_clk, as illustrated in Fig. 

2(c). To get the same oscillation frequency in the receiver 

d7 

Q 

CLK 

D 

CLK 

Q 

d5 

d6 

Q 

D 

CLK 

68 

(int_clkre), the dummy cell is inserted to int_clkre with the 

same size as the loading in int_clk. 

III. HIGH-SPEED SCALABLE DESIGN AND TIMING 

ANALYSIS 

To meet the speed constraint and wide-bandwidth 

demand in SoC, we propose the single-phase pulse-triggered 

TSPC shift-register design in the on-chip serial 

communication transmitter to replace the counter-based 

transmitter in [6]. The proposed single-phase shift register 

timing constraint analysis is illustrated in Fig. 3. With 

single-phase advantage, the proposed design can provide 

larger synchronization timing constraint tolerance. Operating 

at about 2.5GHz, the proposed design can provide 0.151ns 

synchronization timing constraint tolerant range. Every 

single-bit shift register can be viewed as the same and we 

only need to consider the case of read logic “1” in the D 

flip-flop. Therefore, it can be easily scalable to any 

transmission bit number meet the future SoC demand. 

Synchronization timing constraint tolerant region 

( Safe_Region ) 

Trasient_time 

Hold_time 

Buffer_delay 

0.082ns 

0.394ns 

0.151ns 

Setup_time 

0.212ns 0.031ns 

Fig. 3: The timing constraint analysis of the proposed 

single-phase shift register 

In the asynchronous counter (ripple counter), as 

illustrated in Fig 4(a), the delay time is proportional to the 

bit number, because each present counter state input is 

triggered by the previous state output. As a result, the speed 

will be slow, especially as the bit number increases. In the 

synchronous counter, as illustrated in Fig. 4(b), every 

counter clock input is parallel triggered at the same time. 

However, the circuit complexity in the counter will be raised 

as the bit number increases. Also the delay time will be 

increased. In the proposed shift register based design, as 

illustrated in Fig. 4(c), the delay time is constant and 

independent from the serial transmission bit number. The 

speed comparison of counter-based design and proposed 

shift register based design is demonstrated in Fig. 5. In the 

10-bit shift register, the speed can be improved about 80% as 

compared to 10-bit counter. Consequently, it is suitable for 

the wide-bandwidth SoC applications. Furthermore, it can be 

easily extended to any transmission number. 

To generate a fast control signal, we propose a new 

dynamic control technology. The operation timing analysis 

of the proposed dynamic control technique is demonstrated 

in Fig. 6. In the precharge period, the int_clk is triggered by 

the positive edge of ext_clk (the negative edge of ext_clkbar). 

In the evaluation period, with the single-phase property, the


D 

D 

CLK 

CLK 

D 

Q 

CLK Q 

D 

CLK 

QB D 

Q D 

CLK 

CLK Q 

Q D 

QB D 

CLK 

(a) Shift register 

CLK Q 

(b) Asynchronous counter 

Q D 

Q D 

QB D 

CLK 

(c) Synchronous counter 

CLK 

QB 

CLK Q 

Q 

Q D 

Fig. 4: Comparisons of the shift-register circuit and the 

counter circuit 

Fig. 5: The speed comparison of counter-based design and 

proposed shift register based design 

ext_clk 

ext_clkbar 

d10 

control 

precharge 

evaluation 

CLK 

Without Charge Loss Without Charge Loss 

Fig. 6: The operation timing analysis of the proposed 

dynamic control technique 

shift register outputs always change from logic ”0” to logic 

“1”. Therefore, there will be no charge loss through the 

pull-down network even though the signal switches in the 

evaluation period of dynamic control circuit. Consequently, 

the final stage shift register output can be directly connected 

to the dynamic pull-down nMOS. Besides, in the output of 

control circuit, we add 4 transistors to construct the feedback 

latch to boost gain and avoid floating situation. The control 

signal can be fast pulled down to stop the int_clk because 

only one nMOS serial connected with the evaluated nMOS 

in the pull-down network and the precharged pMOS has 

Q 

69 

been turned-off. 

IV. PERFORMANCE COMPARISONS AND 

SIMULATION RESULTS 

The detailed performance comparison of various 

on-chip serial communication designs is illustrated in Table 

1 and the speed timing comparison is illustrated in Fig. 7. All 

the comparison results are based on the post-layout 

simulation got from HSPICE. 

In the on-chip serial communication with 

parallel-to-serial ratio of 10, the 90% interconnection wires 

between IPs can be reduced. In the proposed on-chip serial 

communication design, the critical delay time can be reduced 

to 4.25ns with about 65% improvement and can provide 

about 3 times bandwidth. The delay in the proposed 

single-phase shift register based on-chip serial transmitter 

can be reduced to 0.243ns with about 80%improvement in 

speed as compared to the counter based transmitter in [6]. By 

using the proposed dynamic control technique, the speed can 

be accelerated about 20%. Moreover, the proposed on-chip 

serial communication design possesses good scalability, 

wide timing constraint toleranc. In Fig7, we can find that the 

proposed design can operate fastest because of fast serial 

data transmitted by the proposed single-phase shift-register 

based transmitter. 

Table 1: Performance comparisons of various on-chip serial 

communication designs 

This Work Async[6] Sync[6] 

Tr. Count 384 394 562 

Wire Reduction 90% 90% 90% 

P/S Ratio 10 10 10 

Tcritical (ns) 4.25 13.18 12.12 

Improvement 67.75% 64.93% 

Int_Clk Frequency 2.54GHz 0.73GHz 0.80GHz 

Bandwidth 2Gb/s 0.645Gb/s 0.690Gb/s 

Improvement 3.10X 2.90X 

T_transmitter 0.243 1.213 1.134 


T_control 0.166 0.214 0.214 


Energy (uw/MHz) 1.65 1.63 1.81 

Scalability Good Worse Worse 

Timing tolerance Wide Narrow Narrow 

Proposed 

Async 

Sync 

Control 

Serial Data Transmission 

Wire Delay 

Receive Data 

0 2 4 6 8 10 12 14 (ns) 

Fig. 7: The speed timing comparison of various on-chip 

serial communication designs


Transmitter 

Experimental Long Wire 

Receiver 

Fig. 8: The layout of proposed high-speed, scalable on-chip serial communication design 

ext_clk 

int_clk 

int_clkre 

ipre1 

ipre2 

ipre3 

ipre4 

ipre5 

ipre6 

ipre7 

ipre8 

ipre9 

ipre10 

0 1 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 1 

0 

1 

0 

0 

0 

0 

1 

0 

1 

1 

1 

1 

1 

1 

1 

1 

0 

0 

0 

1 

Fig. 9: Waveform of the proposed high-speed, scalable 

on-chip serial communication design 

Table 2: Performance Summary 

Process UMC 0.18um 

Supply Voltage 1.8V 

Transistor count 384 

Transmission Bandwidth 2Gb/s 

Int_clock Frequency 2.54GHz 

Ext_clock Frequency 200MHz 

Implementation Area 180um* 40um 

Experiment Wire Length 6mm 

To verify the function and performance in silicon, we 

layout the proposed design in UMC 0.18um process, as 

illustrated in Fig. 8. A 6mm experimental long wire is drawn 

to simulate the SoC communication environment. The 

function is verified to be correct in 2Gb/s transmission rate 

as demonstrated in Fig. 9. Finally, Table2 shows the 

0 

1 

1 

1 

1 

0 

0 

0 

1 

1 

1 

1 

1 

0 

0 

1 

1 

0 

0 

1 

0 

1 

0 

0 

0 

0 

1 

0 

1 

1 

70 

Input Register 

Output Register 

performance summary of the proposed high-speed, scalable 

on-chip serial communication design. In the proposed design, 

the total transistor number is 384. In the UMC 0.18um 

process, the proposed design can support 2Gb/s transmission 

bandwidth with 2.54GHz int_clk and 200MHz ext_clk. The 

total implementation area is 180um*40um, excluding 

experimental wire area. 

V. CONCLUSIONS 

In this paper, a high-speed, scalable on-chip serial 

communication interface design is proposed in UMC 0.18um 

process. The serial communication clock frequency is 

designed to work correctly at 2.54GHz to provide 2Gb/s 

transmission bandwidth for SoC applications. By using the 

dynamic control technology, we can generate a fast and 

reliable control signal with about 20% improvement in speed. 

By using the single-phase pulse-triggered TSPC shift register 

design, the speed can be accelerated about 65% to provide 

about 3 times serial transmission bandwidth. Moreover, the 

proposed design can be easily scalable. 

REFERENCES 

[1] Ron Ho, Kenneth W. Mai, and Mark A. Horowitz, “The 

Future of Wires,” Proceedings of the IEEE, Volume 89, 

Issue 4, Pages 490-504, 2001. 

[2] L. Benini, and Giovanni De Micheli, “Networks on 

Chips: A New SoC Paradigm,” IEEE Computer, Volume 

35, Issue 1, Pages 70-78, 2002. 

[3] K. Lahiri, et al, “Design of High-Performance 

System-on-Chips using Communication Architecture 

Tuners,” IEEE Transaction on CAD/ICAS, Volume 23, 

Issue 5, Pages 620-636, 2004. 

[4] F. Karim, et al, “On-Chip Communication Architecture 

for OC-768 Network Processors,” Proc. DAC, Pages 

678-683, 2001. 

[5] Se-Joong Lee, et al, “An 800MHz Stat-Connected 

On-Chip Network for Application to Systems on a chip,” 

ISSCC, Pages 468-469, 2003. 

[6] Shinji Kimura, et al, “An On-Chip High Speed Serial 

Communication Method Based on Independent Ring 

Oscillators,” ISSCC, Pages 390-391, 2003. 

[7] J. S. Wang, Po-Hui Yang, and Duo Sheng, “ Design of a 

3-V 300MHz Low-Power 8-b X 8-b Pipelined Multipliers 

Using Pulse-Triggerd TSPC Flip-Flops“ IEEE JSSC, vol 

35, pp. 583-592, April 2000.


FULLY DIGITAL FEEDFORWARD 

DELTA-SIGMA MODULATOR 

Ahmed Gharbiya and D. A. Johns 

Department of Electrical and Computer Engineering, University of Toronto, 

10 King’s College Road, Toronto, Ontario, Canada, M5S 3G4 

E-mail: gharbiya@eecg.utoronto.ca 

ABSTRACT 

A delta-sigma modulator using a fully digital feedforward 

path is proposed. The new modulator retains the 

conventional input feedforward structure advantages and 

adds to them the elimination of the analog adder at the 

quantizer input and improved signal-to-noise ratio. The 

new modulator requires an extra quantizer and digital 

adders. 


Delta-sigma (∆Σ) modulators are widely used for high 

resolution and low to moderate bandwidth 

analog-to-digital converters (ADCs). With the continuing 

advancement of CMOS technology and demand for higher 

bandwidth, the analog components of ∆Σ modulators are 

increasingly more difficult to implement. The input 

feedforward concept is a method of relaxing the 

requirements on the analog blocks [1, 2]. For example, 

Fig. 1 shows a conventional chain of integrators with 

distributed feedback (CIFB) structure (solid line). This 

structure can be modified to include an input feedforward 

(CIFB-IF) path (dashed line) which removes the 

input-signal component from the output node of the 

integrators, relaxing the headroom requirements and 

possibly allowing for more efficient opamp architectures 

to be used. Also, distortion becomes independent of the 

input signal, which relaxes the linearity requirements. 

Both of these advantages can reduce power dissipation. 

z 

1− 

z 

−1 

−1 

z 

1− 

z 

−1 

−1 

Fig. 1: Second-order ∆Σ modulator 

Different input feedforward architectures have been 

proposed [1-3] and most are implemented completely in 

the analog domain. Recently, a partially digital input 

feedforward modulator was proposed [3]. This paper 

presents a modulator with the input feedforward path 

implemented completely in the digital domain. 

The outline of this paper is as follows. Section 2 describes 

the new fully digital feedforward concept using a 

first-order ∆Σ modulator. Section 3 evaluates the 

performance of the proposed technique using a 

71 

second-order ∆Σ modulator. Section 4 presents a 

simplified fully digital feedforward technique. Finally, 

conclusions are presented in section 5. 

2. PROPOSED TOPOLOGY 

The fully digital feedforward (FDFF) structure is 

illustrated for a first-order modulator as shown in Fig. 2. 

The feedforward path (dashed line) consists of an 

additional ADC (ADC 2) with a reference voltage V ref, ADC2 

which can be different than the main ADC (ADC 1) 

reference voltage (V ref, ADC1). In addition, the number of 

bits in ADC 2 can be different than that of ADC 1. An 

additional digital-to-analog converter (DAC) is needed to 

feed the weighted digitized input-signal into the loop. 

Vref, ADC2 

ADC2 

DAC 

x 

a1 

- 

DAC 

−1 

z 

−1 

1− 

z 

ADC1 

y 

b1 

c1 

b2 

Vref, ADC1 

Fig. 2: First-order Fully Digital Feedforward ∆Σ 

modulator 

The modulator can be simplified further as shown in Fig. 

3, where the extra DAC is eliminated by performing the 

addition in the digital domain. As will be shown shortly, 

the coefficient values feeding to the integrator from the 

DAC are equal; therefore, the signal processing doesn’t 

involve any multiplications, only additions are required. 

z 

1− 

z 

−1 

−1 

Fig. 3: Modified first-order FDFF ∆Σ modulator 

c2

The noise transfer function of ADC 1 is not affected and is 

first-order noise shaped. Quantization noise from ADC 2 is 

completely cancelled and doesn’t appear at the output of 

the modulator; however, it appears at the output of the 

integrator. The signal at the output of the integrator 

doesn’t contain any input-signal component, only 

quantization noise. A linear analysis of the system leads to 

the following results: 


−1 

( 1− z ) q1 

y 

out 

−1 

= −z 

q 

−1 

− z q 

(2) 

−1 

= z x + 

(1) 

integrator 

for the following choice of coefficients: 

a α 

−1 

−1 

1 = 1, 

b1 

= 1 − α , b2 

= α, 

c1 

= 1− 

z , c2 

= z 

where q 1 is the quantization noise from ADC 1, q 2 is the 

quantization noise from ADC 2, and α is a constant. 

The first benefit of the FDFF modulator when compared 

to classical input feedforward modulators is eliminating 

the adder that is required before the main quantizer 

(ADC1). This analog adder is implemented using active or 

passive circuits. In either implementation there is an 

increase in design complexity and power consumption. 

The increased power consumption using a passive adder is 

due to the reduction in dynamic range inherent in their 

switched-capacitor implementation, which means that the 

quantizer has to resolve smaller voltages and therefore 

increase its power consumption [2]. Therefore, the 

additional circuitry used to implement the digital 

feedforward modulator does not necessarily increase the 

power consumption and it is simpler to implement. 

The second benefit is increasing the achievable 

signal-to-noise ratio (SNR). To understand how this 

happens, the modulator is redrawn as shown in Fig. 4 with 

α=0. 

z 

1− 

z 

Fig. 4: FDFF ∆Σ modulator with the blocks rearranged 

The modulator can be viewed as a two stage modulator 

with the second stage (inside dashed box) being a 

conventional feedback ∆Σ modulator. The modulator has 

two regions of operation, the first is before ADC 2 saturates 

(the input voltage is less than V ref, ADC2) and the second is 

after ADC 2 saturates (the input voltage is greater than 

V ref, ADC2). In region one, the input voltage to the second 

stage is mostly quantization noise and the modulator has 

all the benefits of the input feedforward technique. In 

region two, the input voltage to the second stage contains 

input-signal component and the modulator operates as a 

conventional feedback structure. The maximum input 

voltage in region two is proportional to V ref, ADC1 and 

depends on the loop order and number of bits in the 

quantizer ADC 1 as in conventional modulators. Therefore, 

−1 

1 

−1 

2 

−1 

z 

72 

the maximum achievable input signal amplitude of the 

overall modulator is: 

Vin , max 

= V + k V 

(3) 

ref, ADC2 

ref, ADC1 

where k is a constant ranging from 50 to 80% [4]. This 

should be compared to conventional structures where: 

Vin = k V 

(4) 

, max 

ref, ADC1 

The larger input-signal means that the FDFF modulator 

can achieve better SNR, or can consume less power for the 

same SNR as conventional structures. 

The third benefit is the possibility of easily modifying an 

existing modulator to incorporate the fully digital 

feedforward idea. The modification can help modulators 

that suffer from opamp nonlinearities if operation is 

restricted to region 1. Another benefit of restricting the 

operation to region 1 is improved stability. As can be seen 

from (3), when the maximum input signal is limited to 

Vref, ADC2, the modulator is kVref, ADC1 away from 

overloading. 


Several simulations using MATLAB ® and Simulink ® were 

used to evaluate the performance of the new modulator 

and to compare it to conventional structures. The 

second-order FDFF modulator is used for the simulations 

as shown in Fig. 5 and for the following choice of 

coefficients: 

a1 

= 1, 

a2 

= 1, 

b1 

= 1, 

b2 

= 1, 

b3 

= 0, 

b4 

= 1, 

−2 

−2 

c = 1, 

c = z , c = z , 

1 

2 

3 

z 

1− 

z 

−1 

−1 

z 

1− 

z 

Fig. 5: Second-order FDFF ∆Σ modulator 

All simulations are carried out with an oversampling ratio 

(OSR) of 32, 3 bits in both quantizers, a quantizer 

reference voltage Vref, ADC1 =±0.5 =Vref, ADC2, and 

uniformly distributed dithering added to each quantizer. 

The modulator is insensitive to non-idealities in the 

additional quantizer ADC2. In fact, variations of σ=50% in 

the reference levels of ADC2 result in no degradation to 

the SNR as long as ADC2 is monotonic. 

Performing the signal processing in the digital domain 

requires finer DACs to feedback the sum of digital signals. 

The number of levels required by the DACs was 

determined by simulations; DAC1 requires 15 levels and 

DAC2 requires 8 levels. In general, the number of levels 

2 1 

1 N + 

− and for DAC2 is N 

2 . 

for DAC1 is ( ) 

−1 

−1

The modulator was simulated taking into account the 

effect of finite gain, bandwidth, and slew rate of the 

opamp in the first integrator. From simulations, the opamp 

requirements are an open-loop DC gain of 55dB, a 

bandwidth f-3dB of 1.25fsampling, and a slew-rate of 

1.2 V/Tsampling; where f-3dB is the closed-loop -3dB 

bandwidth of the opamp, fsampling is the sampling 

frequency, and Tsampling is the sampling period. It should be 

mentioned that these requirements are slightly larger than 

those required by the conventional structures, but less than 

those of cascade (MASH) structures. The higher 

requirements are needed to achieve cancellation of ADC2 quantization noise at the output. It is also possible to 

compensate for these non-idealities in the digital domain 

to relax the opamp requirements which will be discussed 

in section 4. 

The first and second integrator output probability densities 

are shown in Fig. 6 for the FDFF, CIFB, and CIFB-IF. 

occurrences [%] 

occurrences [%] 

15 

10 

5 

0 

-1 -0.5 0 

integrator 1 output 

0.5 1 

10 

8 

6 

4 

2 

0 

-1 -0.5 0 

integrator 2 output 

0.5 1 


FDFF 

CIFB 

CIFB-IF 

FDFF 

CIFB 

CIFB-IF 

Fig. 6: Output probability densities for the first and 

second integrators with sinusoidal input 

The signals for the FDFF are slightly larger than the 

CIFB-IF because it contains q2 in addition to q1; since 

CIFB contains input-signal component, its signals are 

larger. 

The SNR improvement is illustrated in Fig. 7 where the 

SNR is plotted versus the input-signal amplitude in dBFS, 

where dBFS is dB with respect to the full scale (which is 

defined to be Vref, ADC1). The plot shows that the new 

modulator can achieve 8 dB better SNR than conventional 

structures. The SNR can be improved further by 

increasing Vref, ADC2. For example, if Vref, ADC2 is twice as 

large as Vref, ADC1, SNR improves by an extra 3dB. The 

trade off is increasing the signal swings at the integrators 

outputs. Larger reference voltages for ADC2 are possible 

because it is outside the loop and therefore is not limited 

by opamps output swing. 

73 

SNDR [ dB ] 

90 

80 

70 

60 

50 

40 

30 

20 

10 

FDFF 

CIFB 

CIFB-IF 

0 

-80 -70 -60 -50 -40 -30 -20 -10 0 10 

A [ dBFS ] 

Fig. 7: SNR versus input-signal amplitude 

The output spectrum of the modulator is illustrated in Fig. 

8 for both regions of operation. The input-signal frequency 

is at 1/4 the Nyquist bandwidth to clearly show any 

distortion components. The simulations are carried out 

with finite gain, bandwidth, slew rate, and third order 

distortion in the first integrator and with variations of 

σ=5% in the reference levels of ADC 2. 

PSD [ dB ] 

PSD [ dB ] 

0 

-50 

-100 

-150 

0 

-50 

-100 

-150 

10 -3 

10 -3 

10 -2 

Frequency [ f/fs ] 

(a) 

10 -2 

Frequency [ f/fs ] 

(b) 

10 -1 

10 -1 

Fig. 8: Output spectrum for second-order ∆Σ 

modulator (a) region 1 of operation (b) region 2 of 

operation 

In region one, the input signal amplitude is 0 dBFS, and 

the spectrum doesn’t show distortion as expected from 

input feedforward structures. In region two, the input 

signal amplitude is 3 dBFS, and the spectrum shows third 

order distortion component. However, even if the 

input-signal is restricted to region one operation only, 

there is still SNR gain since the input-signal can be as 

large as 0 dBFS. Moreover, V ref, ADC2 can be set larger than 

V ref, ADC1 which allows the input signal to be larger than 0 

dBFS.

4. SIMPLIFIED FDFF MODULATOR 

A simpler FDFF modulator shown in Fig. 9 can be devised 

by generalizing the structure in Fig. 4. The simplified 

FDFF consists of an input stage (ADC 2 and a subtractor), 

a conventional ∆Σ modulator, and a digital filter H. The 

inter-stage gain factor “a” doesn’t map directly from Fig. 

4, but it offers another degree of freedom in designing 

FDFF modulators. 

Fig. 9: Simplified Second-order FDFF ∆Σ modulator 

Linear analysis of the system leads to the following: 


( H − a STF ) q2 

y H x + NTF∆Σ 

q1 

+ 

∆Σ 

= (5) 

where STF ∆Σ and NTF ∆Σ are the conventional ∆Σ 

modulator transfer functions. Therefore, to cancel q 2 at the 

output of the modulator, H must equal (aSTF ∆Σ). 

Compensating for opamp non-idealities in the simplified 

FDFF is an easy task. First, errors in (aSTF ∆Σ) should be 

measured. Then, a correction is applied to H in the digital 

domain to achieve a match between H and (aSTF ∆Σ). Since 

this multiplication is not in the feedback, it doesn’t restrict 

the speed of the FDFF modulator. 

A second-order FDFF ∆Σ modulator is shown in Fig. 10 as 

an example. Note that the two adders on the left-hand side 

of the modulator can be combined in the digital domain. 

Or, they can share the same opamp in the analog domain; 

therefore, there is no extra opamp required for the 

subtractor. 

z 

1− 

z 

−1 

−1 

z 

1− 

z 

Fig. 10: Simplified Second-order FDFF ∆Σ modulator 

The achievable SNR can be increased further by 

exploiting the inter-stage gain factor. There is an optimal 

value for the gain that results in maximum increase of the 

SNR. 

−2 

z 

−1 

−1 

74 

SNR [ dB ] 

90 

85 

80 

75 

70 

65 

60 

55 

50 

1 2 3 4 

inter-stage gain 

5 6 7 

Fig. 11 SNR vs. inter-stage gain 

Fig. 11 shows the maximum achievable SNR versus the 

inter-stage gain for the same specifications stated in 

section 3. There is an extra 6 dB SNR improvement for 

picking the optimal inter-stage gain of 3. The trade off is 

increasing the signal swings at the integrators outputs. 

Since this signal is still quantization noise only, the 

linearity requirements are still relaxed. 

5. CONCLUSION 

A ∆Σ modulator with a fully digital feedforward path has 

been described. The new modulator eliminates the analog 

adder at the quantizer input and improves the SNR. It 

requires one extra quantizer and digital adders. 

6. REFERENCES 

[1] J. Silva, U. Moon, J. Steensgaard, and G.C. Temes, 

“Wideband low-distortion delta-sigma ADC 

topology,” Electron. Lett., vol. 37, pp. 737 – 738, 

2001. 

[2] A.A. Hamoui and K.W. Martin, “High-Order 

Multibit Modulators and Pseudo 

Data-Weighted-Averaging in Low-Oversampling ∆Σ 

ADCs for Broad-Band Applications,” IEEE Trans. 

Circuits Syst. I, vol. 51, pp. 72 – 85, 2004. 

[3] S. Kwon and F. Maloberti, “Op-Amp Swing 

Reduction in Sigma-Delta Modulators,” Proc. IEEE 

ISCAS, pp. I-525 – I-528, 2004. 

[4] S. R. Norsworthy, R. Schreier, and G. C. Temes, 

Delta-Sigma Data Converters: Theory, Design, and 

Simulation. Piscataway, NJ: IEEE Press, pp.157, 

1997.


A HIGH-SPEED TECHNIQUE FOR TIME- 

INTERLEAVING CONTINUOUS-TIME DELTA- 

SIGMA MODULATORS 

Trevor C. Caldwell and David A. Johns 

University of Toronto, Department of Electrical and Computer Engineering 

10 King’s College Rd., M5S 3G4, Toronto, Ontario, Canada 

E-mail: caldwet@eecg.toronto.edu 

ABSTRACT 

A technique for increasing the speed of time-interleaved 

continuous-time ∆Σ modulators is presented. Extra 

feedback paths allow the DAC pulse to enter the adjacent 

clock period without deteriorating the SNR of the ∆Σ 

modulator. With the added feedback paths, an extra 

summer needs to be added to the modulator to attain an 

equivalent impulse response, but the critical path of the 

modulator is able to operate twice as fast. Also, with the 

inclusion of non-idealites such as finite gain and finite 

bandwidth opamps and DAC clock jitter, the modulator is 

able to attain a higher SNR with the new technique. 


A method of time-interleaving continuous-time deltasigma 

(∆Σ) modulators has been accepted for publication 

at the 2005 European Solid-State Circuits Conference 

(ESSCIRC) [1]. The modulator operates at an 

oversampling ratio (OSR) of 5 with a time-interleaving 

factor of 2 at sampling frequencies of 100MHz and 

200MHz. It achieves a signal-to-noise and distortion ratio 

(SNDR) of 57dB and 49dB in signal bandwidths of 

10MHz and 20MHz, respectively. As it was the first 

integrated circuit implementation of a time-interleaved ∆Σ 

modulator, an opportunity for improvement in the design 

has been found. This paper presents a method of 

increasing the speed of the modulator to overcome the 

low-latency requirement of the critical path using 

additional digital-to-analog converter (DAC) feedback 

paths. The method also relaxes the requirements of the 

opamps while also increasing the allowable clock jitter on 

the DAC clock. 

This paper will proceed as follows: Section 2 will discuss 

the new technique, while Section 3 will demonstrate 

simulation results with non-idealities added. Section 4 will 

conclude the paper. 

2. HIGH-SPEED SOLUTION 

2.1 Time-Interleaved Modulator 

A continuous-time time-interleaved (CTTI) ∆Σ modulator 

is shown in Fig. 1, as derived from the appropriate 

discrete-time ∆Σ modulator. The noise transfer function of 

75 

these two modulators is identical, while the signal transfer 

function is negligibly different. 

The critical path in this modulator is between the Bottom 

return-to-zero (RZ) DAC and the Top analog-to-digital 

converter (ADC). Within one clock period (of 2T, as 

compared to the original period of T for the discrete-time 

modulator of Fig. 1), the output of the Bottom RZ DAC 

must be summed to the top branch where it must be 

quantized by the Top ADC and output by the Top RZ 

DAC. For both of the RZ DAC pulses to stay within their 

respective clock periods, the RZ DAC pulses are chosen as 

shown in Fig. 1 where the Bottom RZ DAC pulse is nonzero 

from T/2 to 3T/2, and the Top RZ DAC pulse is nonzero 

from T to 2T. Also, the quantization in the Bottom 

ADC occurs at 0, 2T, 4T, etc., while the quantization in 

the Top ADC occurs at T/2, 5T/2, 9T/2, etc. This scheme 

is successful; however, the output of the Bottom RZ DAC 

must be summed, quantized and output from the Top RZ 

DAC within T/2 seconds. At a sampling frequency of 

200MHz (2T=5ns), this allows only 1.25ns to perform the 

summation, quantization and RZ DAC operation. This 

significantly increases the power consumption of the ADC 

and summer since the latency must be very low. Also, two 

90-degree phase shifted clocks are necessary to produce 

the proper Top and Bottom RZ DAC timing signals, 

requiring a larger clock generator circuit. 

Figure 1. CTTI ∆Σ modulator derived from its 

discrete-time equivalent modulator.

2.2 Additional Feedback Paths 

In order to reduce the latency requirements on the critical 

path of the modulator, the Top RZ DAC pulse could be 

output at a later time. However, the DAC pulse would then 

enter the next clock period. A technique presented in [2] 

demonstrates that in a regular continuous-time ∆Σ 

modulator, an extra feedback path between the DAC and 

the ADC can be added to compensate for a DAC pulse 

that enters the adjacent clock period. Typically, this 

technique is used to combat excess loop delay in 

modulators with non-return-to-zero (NRZ) DAC pulses. 

Due to finite switching time of transistors, these 

modulators are unable to output a DAC pulse 

immediately, causing the NRZ pulse to enter the next 

clock period [3]. 

x(t) 

Sampling Time = 2T 


1 

Ts 

1 

Ts 

1 

Ts 

T 

y 1 

w 1 

w2 y2 0 T 

Top 

DAC 

2T 

Top 

ADC 

Bottom 

ADC 

Bottom 

DAC 

0 T 2T 

Figure 2. CTTI modulator with additional DAC 

feedback paths for the Top DAC. 

Using the technique presented in [2], the CTTI ∆Σ 

modulator can be modified with extra feedback paths that 

will allow the DAC pulse to enter the adjacent clock 

period. Keeping the Bottom RZ DAC pulse the same, the 

Top RZ DAC pulse can be delayed by another T/2 seconds 

so that its non-zero duration is from 3T/2 to 5T/2, where 

the last T/2 seconds of this pulse enters the next clock 

period. Since this is a time-interleaved modulator, the 

extra DAC feedback path does not follow exactly from 

[2], and two feedback paths are required, one from the Top 

RZ DAC to the Top ADC, and another from the Top RZ 

DAC to the Bottom ADC. This requires two additional 

DACs, depending on the design. The resulting modulator 

with the additional feedback terms is shown in Fig. 2. The 

other DAC feedback coefficients β4, β5 and β6 must be 

changed to ensure equivalence between the impulse 

response of the new modulator and the modulator of Fig. 1 

(note that the two impulse responses that must be matched 

to each other are from the output of the Top ADC to the 

input of the Top ADC, and from the output of the Top 

ADC to the input of the Bottom ADC). Since a summation 

node already exists at the input of the Top ADC, an extra 

summation block is necessary only at the input of the 

Bottom ADC. The extra circuit elements are highlighted 

with a dotted line in Fig. 2. 

Since the Top RZ DAC pulse has been delayed by an extra 

T/2 seconds, there are T seconds for all operations in the 

critical path to complete, as opposed to T/2 seconds. The 

ADC clocks can then be adjusted so that while the 

quantization in the Bottom ADC still occurs at 0, 2T, 4T, 

etc., the quantization in the Top ADC now occurs at T, 3T, 

2 

2 

z -1/2 

y[n] 

76 

5T, etc. Therefore, the latency requirements on the circuit 

elements in the critical path have been reduced by a factor 

of 2. This primarily affects the ADC and the summer, 

which have the largest delays. 

2.3 NRZ DAC Pulses 

It is more advantageous in a continuous-time ∆Σ 

modulator to use NRZ DAC pulses since they increase the 

modulator’s resilience to DAC clock jitter [4]. The Top 

DAC of the previous section can be modified by changing 

* * * 

the DAC feedback parameters β4 , β5 , β6 , β8 and β9 to 

accommodate a NRZ DAC pulse that extends further into 

the next clock period (from 3T/2 to 7T/2). The resulting 

modulator is otherwise identical. Note that this 

modification is only possible since the additional feedback 

paths are already in place to allow the DAC pulse to enter 

the next clock period. 

The techniques applied to the Top DAC in the previous 

section can also be applied to the Bottom DAC. The 

Bottom DAC pulse can enter the adjacent clock period as 

an NRZ pulse by adding two additional feedback paths 

and extending the pulse so that it lasts from T/2 to 5T/2. In 

this case, the two impulse responses that must be matched 

to each other are from the output of the Bottom ADC to 

the input of the Bottom ADC, and from the output of the 

Bottom ADC to the input of the Top ADC. The 

coefficients β1, β2 and β3 must be modified to 

accommodate the longer DAC pulse. Since summers 

already exist in both the top and bottom branches, no 

additional summers are required. 

The resulting Modified Continuous-Time Time-Interleaved 

(M-CTTI) ∆Σ modulator is shown in Fig. 3. The Top and 

Bottom DAC pulses are 180-degrees out of phase, and 

they are each of length 2T, meaning that they are NRZ 

pulses. The two additional feedback paths due to this 

modification are highlighted with a dotted line. It should 

be noted that the β10 feedback path cannot be combined to 

the β7 feedback path, even though they may appear to 

represent the same path. This is because the β7 feedback 

path still represents the signal in the critical path that must 

be quantized and added to the Top ADC within T seconds, 

while the β10 feedback path is to be combined with the 

next quantization interval of the Top ADC, 2T seconds 

later. 

x(t) 

1 

Ts 

1 

Ts 

Sampling Time = 2T 

1 

Ts 

y 1 

w 1 

w2 y2 0 T 

Top 

2T 

RZ DAC 

Top 

ADC 

Bottom 

ADC 

Bottom 

RZ DAC 

0 T 2T 

Figure 3. M-CTTI modulator: CTTI modulator 

with additional NRZ DAC feedback paths. 

T 

3T 

2 

2 

z -1/2 

y[n]

2.4 Circuit Considerations 

Despite requiring an additional summation block, the 

latency requirements on both the Top and Bottom paths of 

the new M-CTTI modulator are now equivalent, which 

simplifies the design. Both the Top and Bottom ADCs, 

DACs and summers can be designed identically, while in 

the previous CTTI ∆Σ modulator, the bandwidth 

requirement on the Bottom ADC was much greater than 

that of the Top ADC. Furthermore, one of the major 

sources of power consumption of the original CTTI 

modulator was the ADC, which consumed about 36% of 

the total power. With the new improvement, about half of 

this power (18% of the total power) can theoretically be 

saved since the tolerable latency of the ADCs is now twice 

the previous value. 

While the new modulator requires four additional 

feedback paths, two due to the modification of the Top 

DAC pulses, and two more due to the modification of the 

Bottom DAC pulses, they can be implemented as 

relatively small DACs due to the low linearity required at 

the input of the ADCs. Simulations indicate a linearity of 

6 bits would be sufficient for a 10-bit design, keeping 

them significantly smaller in area than the first stage DAC. 

Another advantage of this technique is that the clocks used 

to generate the RZ DAC pulses are now 180-degrees out 

of phase. The clocks of the original CTTI ∆Σ modulator 

were 90-degrees out of phase, making them much more 

difficult to generate. With the new DAC feedback scheme, 

the clocks are far easier to implement as a simple 

inversion, and only one off-chip clock is required. Also, a 

small power savings in the clock generator circuits is 

obtained, since fewer non-overlapping clock generators 

are needed. 

3.1 Ideal Modulator 


3. SIMULATIONS 

To confirm the equivalence between the M-CTTI 

modulator and the CTTI modulator, MATLAB 

simulations were performed. The impulse responses of the 

two modulators were matched to an accuracy of 0.1% 

using the additional feedback paths. The resulting output 

spectra are shown in Fig. 4 where a 3 rd order, low-pass, 

time-interleaved by 2, continuous-time modulator with an 

OSR of 10 was simulated. The two output spectra are 

almost identical, both achieving a signal-to-noise ratio 

(SNR) of 71.0dB with an input that is 4.4dB below fullscale 

at f S/20. These modulator specifications as well as 

the same input tone were used as the basis for comparison 

in the next section. 

3.2 Addition of Non-Idealities 

Various non-idealities can be added to the MATLAB 

model of the ∆Σ modulators to compare them with respect 

to more practical high-speed issues, such as finite opamp 

bandwidth and gain, and DAC clock jitter. First, the 

77 

effects of the modified feedback paths on finite opamp 

bandwidth and gain were investigated. The integrators 

were modeled as single-poled, finite-gain amplifiers. The 

M-CTTI modulator was slightly more resilient to these 

non-idealities. With a DC gain of 50dB and a first pole of 

f S/50 (e.g., a first pole of 8MHz for an effective sampling 

frequency of 400MHz, where the effective sampling 

frequency is twice the actual sampling frequency due to 

the time-interleaving by 2), the M-CTTI modulator 

achieved an SNR of 68.6dB, while the previous CTTI 

modulator achieved an SNR of 67.1dB. This difference 

can be significant if the modulator’s performance is 

limited by the bandwidth of the opamps. Also, with lower 

DC gains, the difference in performance between the two 

modulators can be much larger, indicating that the two 

modulators are not affected in the same way by the gainbandwidth 

product, and the M-CTTI modulator is more 

capable of operating with lower-gain, higher-bandwidth 

opamps. This is important in high-speed design where the 

gain may need to be traded for increased bandwidth. 

a) 

Amplitude (dB) 

b) 


0 

-50 

-100 

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 

Frequency (fs=1) 

0 

-20 

-40 

-60 

-80 

-100 

-120 

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 


Figure 4. Output spectra. a) M-CTTI modulator of 

Fig. 3. b) CTTI modulator of Fig. 1. 

Since the new modulator uses multibit NRZ pulses, it is 

expected to be more resilient to DAC clock jitter. This is 

because every DAC pulse will contain jitter in only the 

portion of the pulse that is different from the previous 

pulse, resulting in much less total jitter as a fraction of the 

total pulse energy, when compared to RZ pulses (this is 

especially true because of the 4-bit multibit feedback used, 

and becomes less significant as fewer bits are used in the 

quantizer). Furthermore, when compared to the RZ DAC 

pulse, the length of the pulse is twice the energy, and 

therefore the jitter is proportionally only half as 

detrimental for the NRZ pulse. When simulated with an 

RMS jitter of 12ps, the degradation in the M-CTTI 

modulator is far less than that of the CTTI modulator. The 

M-CTTI modulator has an SNR of 66.0dB, while the 

CTTI modulator has an SNR of only 53.8dB. If the jitter 

can be reduced to only 3ps RMS, the M-CTTI modulator 

has an SNR of 69.8dB, while the CTTI modulator has an 

SNR of 64.5dB, and so the performance degradation of the 

CTTI modulator can be reduced, at the cost of a clock with 

much better jitter performance. But with the M-CTTI

modulator, the requirements on the DAC clock jitter are 

relaxed quite significantly. 

The performance results of the new M-CTTI modulator 

compared to the previous CTTI modulator are summarized 

in Table 1 for various opamp gain and bandwidth values, 

as well as for various quantities of jitter. Sample output 

spectra plots are shown in Fig. 5 where the opamp 

bandwidth is fS/80, the DC gain is 50dB, and the jitter is 

6ps RMS (these values were chosen as the approximate 

values of the previously designed CTTI ∆Σ modulator). 

The distorted shape of the noise transfer function is due to 

the finite bandwidth of the opamps, as well as the reduced 

DC gain, while the increase in the noise floor in the signal 

band is primarily due to the DAC clock jitter. The M- 

CTTI modulator has an SNR of 67.7dB, while the CTTI 

modulator has an SNR of 59.2dB. It is clear from this 

comparison that the new techniques improve the CTTI ∆Σ 

modulator, and the resolution of the M-CTTI modulator is 

increased at higher speeds. 

First 

Pole 

Table. 1. Performance comparison of M-CTTI 

and CTTI modulator. 

DC 

Gain 


RMS 

Jitter 

M-CTTI 

Modulator 

SNR 

CTTI 

Modulator 

SNR 

f S/100 56dB 0ps 70.0dB 66.8dB 

f S/50 50dB 0ps 68.6dB 67.1dB 

f S/25 44dB 0ps 68.8dB 66.0dB 

f S/12.5 38dB 0ps 68.2dB 61.1dB 

Inf. Inf. 3ps 69.8dB 64.5dB 



f S/50 50dB 6ps 67.7dB 59.2dB 


A new technique for reducing the latency requirement in 

the critical path of a CTTI ∆Σ modulator has been 

presented. This technique requires one additional summer 

as well as four additional low-linearity feedback paths or 

DACs, but is theoretically able to save about 20% of the 

power consumption of the original CTTI ∆Σ modulator, as 

well as increase the modulator’s resilience to lower gain 

and lower bandwidth opamps and DAC clock jitter. Both 

of these issues were significant in the original CTTI 

modulator which suffered from both high power 

consumption and reduced performance at high-speeds due 

the low-latency requirement on the critical path and the 

finite bandwidth of the opamps. Another advantage of the 

new technique is that the M-CTTI modulator requires 

clocks for the two ADCs and DACs that are 180-degrees 

apart, which is much easier to generate than the original 

90-degree phase shifted clocks required in the CTTI 

78 

modulator. It has been shown that with the additional 

DAC feedback paths, aside from the slight increase in 

circuit area, the new M-CTTI modulator outperforms the 

original CTTI modulator in many important metrics, 

making it much more suitable for high-speed design. 

a) 


b) 


0 

-50 

-100 

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 


0 

-20 

-40 

-60 

-80 

-100 

-120 

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 


Figure 5. Output spectra with non-idealities. a) 

M-CTTI modulator b) CTTI modulator. 

5. REFERENCES 

[1] T. C. Caldwell and D. A. Johns, “A Time-Interleaved 

Continuous-Time ∆Σ Modulator with 20MHz Signal 

Bandwidth,” to be published at ESSCIRC 2005. 

[2] P. Benabes, M. Keramat and R. Kielbasa, “A 

Methodology for designing Continuous-time Sigma- 

Delta Modulators,” in Proc. European Design and 

Test Conf., pp. 46-50, 1997. 

[3] J. A. Cherry and W. M. Snelgrove, “Excess Loop 

Delay in Continuous-Time Delta-Sigma Modulators,” 

IEEE Trans. Circuit and Systems-II: Analog and 

Digital Signal Processing, vol. 46, pp. 376-389, Apr. 

1999. 

[4] J. A. Cherry and W. M. Snelgrove, “Clock Jitter and 

Quantizer Metastability in Continuous-Time Delta- 

Sigma Modulators,” IEEE Trans. Circuit and 

Systems-II: Analog and Digital Signal Processing, 

vol. 46, pp. 661-676, June 1999.


ANALOG SOFT MAX CIRCUIT WITH 

DYNAMIC GAIN CONTROL 

Davide Piombo and Rodolfo Zunino 

Biophysical and Electronic Engineering Department (DIBE), Genoa University, 

Via Opera Pia 11a, 16145 Genova, Italy 

E-mail: {piombo, zunino} @dibe.unige.it 

ABSTRACT 

An analog current-mode circuit performs Soft-Max 

computation with gain-control capability; a theoretical 

analysis supports the design method and gives the 

expected error bound. Experimental results from postlayout 

simulations match theoretical predictions. 


The Soft Max (SM) function [1] of a vector, Y, of n scalar 

inputs:Y={y1,..,yn}, is a vector, S, of n values computed as: 

Si 

n 

( Y ) = exp( − ⋅ y ) / exp( 

− γ ⋅ y ) 

i 

∑ 

j= 

1 

γ ; i=1,.,n (1) 

where γ is a gain parameter. Soft Max often plays a 

relevant role in analog nonlinear processing because it 

generates a set of output-normalized quantities from a set 

of non-normalized inputs, hence it is suitable for dynamic 

control; by adjusting the gain parameter, γ, one can tune 

the SM function from a smooth mapping �(small γ values) 

to a Winner-Takes-All (WTA) selection (γ → ∞). From a 

circuit viewpoint, some issues hinder hardware 

implementations of SM processing: the considerable 

dynamic range possibly required to support the 

exponential function; precision issues in rendering the 

normalizing ratio accurately; finally, and most 

importantly, an effective SM circuit should be able to 

support adjustable gain control. These aspects can 

probably explain why there are very few research on SM 

circuitry, as opposed to the vast literature on WTA 

schemata. This paper describes a general CMOS design 

method for current-mode SM circuits. A theoretical 

characterization derives an analytical upper bound to the 

hardware-induced approximation error, which is used to 

develop the actual circuit design. The schema exhibits two 

major advantages: first, a modular approach facilitates the 

design of SM systems with an arbitrary number of inputs; 

secondly, the circuit enables one to set the SM gain factor. 

2. THEORETICAL ANALYSIS OF 

SOFTMAX PROCESSING 

2.1 Approximation by power series 

A crucial feature of Soft Max computation is that the 

really important quantity is the absolute difference 

j 

79 

between the largest component and other components. In 

this sense, the role of the gain factor, γ, lies in resizing the 

input dynamic range properly. For the sake of simplicity, 

in the following we shall write: γ⋅y i≡x i and x i∈ℜ + . 

The Soft Max computation can be split into two 

operations, namely, the exponential computation and a 

global normalization that rescales output values. The 

approximation method adopted in this paper performs the 

computation of an approximated value of the 

exponentiation, and use a CMOS version of the Gilbert’s 

global normalization circuit [2] for the second task. 

The exponential approximation is obtained by a Taylor 

power series, truncated at the m-th order term: 

m 

i 

i 

( ) 

( x j − x0 

) 

exp x j ≈ ∑ ( −1) 

exp( 

x0 

) (2) 

i= 

0 i! 

Approximated output values are computed in a parallel 

way, for all components of the Soft Max input vector Y. 

The present approach uses the minimum input component 

as the pivot value, x0, of the series; Such a setting ensures 

that all the differential terms in (2) remain positive. 

Defining the quantities x j = x j − x0 

≥ 0 ∀j 

, and 

xupper = sup x j , and denoting with S j 

j 

~ the approximation 

of (1) using (2); after some derivations one obtains an 

upper bound to the approximation absolute error for each 

single output component: 

| | ( ) 

( ) 2 

m+ 

1 

xupper 

2 ⋅ 

~ m+ 

1 ! 

Errj 

= S j − S j ≤ 

; j=1,..,n (3) 

n ⋅ 1− 

xupper 

When representing quantities with a current-mode coding, 

each input value xj is supported by a proportional current 

term Ij=IREF xj. As a result, the current-mode circuit that 

implements (2) should first extract the minimum input 

component, then subtract it from each input term. The 

current-mode representation of this operation will be 

denoted as 

I j = I j − min { Ii} 

= IREF 

⋅ x j ; j=1,..,n (4) 

The resulting current value for the exponential 

approximation will be then: 

m 

~ ( exp) 

m IREF 

⋅ xj 

I j = IREF 

− IREF 

⋅ xj 

+ .. + ( −1) 

; j=1,..,n (5) 

m!

The key idea in the SM circuit is now to make the 

constant current, I0, adaptive to the current input 

configuration, by imposing it to be proportional to the 

largest input value: 

IREF = KREF 

max{ 

Ii} 

(6) 

i 

−1 

By this trick one has: x upper = max{ 

Ii} 

IREF 

= KREF 

, 

i 

which makes the approximation error (3) inputs 

independent, and the designer has one degree of freedom, 

i.e., the order, m, of approximation. 

2.2 Approximation Error Analysis 

The final error characterization gives a bound that 

decrease rapidly with K0 for any input vector dimension n 

and for all approximation order m>1: 

m+ 

1 

⎛ 1 ⎞ 

2 ⋅ ⎜ ⎟ 

~ 

⎜ K ⎟ 

REF 

Errj 

= | S j − S j | ≤ 

⎝ ⎠ 

(7) 

2 

⎛ 1 ⎞ 

n ⋅ ⎜1 

⎟ 

⎜ 

− ⋅ ( m+ 

1)! 

K ⎟ 

⎝ REF ⎠ 

The graph in Fig 1 shows a family of error curves having 

a common approximation order m=2, for several input 

dimensions, n. The graph clearly shows that the adopted 

approximation order m=2 is sufficient to limit the 

approximation error under 0,05 for all K 0>1. 


Figure 1: Approximation error bound 

3. CURRENT MODE CIRCUIT 

DESIGN 

For the sake of clarity, the current-mode Soft Max circuit 

design will be explained by considering a sample set-up 

adopting the above-derived approximation order m=2. The 

following sections will first describe the sub-circuits to 

perform maximum- and minimum-extraction, then the 

schemata to compute each single term of the exponential 

approximation will be illustrated and analyzed. Finally, a 

short description of the global normalization circuit will 

be given. 

80 

3.1 Maximum Minimum Extraction 

The extraction of the maximum and minimum component 

of the input vector is performed by a hierarchical binary- 

tree architecture made of two inputs/two outputs cells. 

One output line from each cell gives the larger input 

value, whereas the other channel returns the smaller. Each 

hierarchy (for max and min selection, respectively) 

includes a number log 2n of layers, but the two hierarchies 

share the first layer. The schema of a binary cell is 

presented in Fig.2, and is a variation of the classical WTA 

Lazzaro cell [3]. The steering cell in Fig.3 compensates 

crossover distortion when the pair of input values are not 

separable, and gives as outputs their arithmetic average. 

Figure 2: Binary Min-/Max extraction cell 

Figure 3: Steering cell for Max-Min selection 

3.2 Exp approx.: the Constant Term 

The bias, IREF, is the first series term (5) that must be 

computed to obtain the exponential approximated value. 

Expression (6) shows that the inputs required to generate 

that bias term are: the difference between the largest and 

smallest inputs, and the gain factor KREF. The schema 

adopted to support (6) accordingly is a current-steering 

D/A converter, whose digital inputs represent the K0 

factor, while the reference current is the difference current 

max { I j} 

. Fig.4 show the constant term circuit schema. 

j 

3.3 Exp approx.: the Linear Term 

The linear term of the approximation is simply the input 

current of the j-th channel, after the subtraction of the 

minimum input current: I j = I j − min{ 

Ii} 

. 

i


Figure 4: Cell schematic for the I REF term 

3.4 Exp approx.: the Quadratic Term 

The circuit schema for the quadratic term in (5) uses a 

weak inversion trans-linear loop, which is highlighted in 

the grey area of Fig.5. It is easy to verify that such a sub 

circuit drives into the mirror M34/M33 a current term that 

2 ( I j ) 

is equal to . The output mirror exhibits a 2:1 aspect 

IREF 

ratio to implement the denominator factor in (5). 

3.5 The Exponential Approximated Value 

Fig. 5 gives the complete schema used for the second 

order exponential approximation. The 2-nd order 

approximation of the exponential will therefore include 

the three terms described above. In the circuit schema of 

Fig. 5, the associated currents sum at node A, hence one 

obtains an output current value: 

( ) 

{ } ⎟ ⎟ 

⎛ 

⎞ 

⎜ 

ˆ 2 

j 

1 1 x j 

I exp = KREF 

⋅ I0 

⋅ max xi 

⋅ 1− 

xˆ 

+ 

⎜ 

j 

(8) 

i K 

2 2 

⎝ REF KREF 

⎠ 

where: 

x j 

xˆ 

j = (9) 

max{ 

xi} 

i 

Figure. 5: Exponential Approximation Cell 

81 

The amplification factor in (8) is common to all 

components, and vanishes in the global normalization 

step. Instead, those expressions show that, in the output 

current value (8), the factor (KREF) -1 can be rewritten as 

the γ factor in the Soft Max definition (1); thus a dynamic 

control of the K REF factor (as shown in Fig.4) allows one 

ultimately to adjust the Soft Max gain dynamically. 

3.6 The Global Normalization Circuit 

The final global normalization is performed by a CMOS 

version of the Gilbert’s global normalization circuit [2], 

whose operation can be written as 

j 

j Iexp 

Iout 

= IT 

⋅ 

(10) 

n 

i 

∑ Iexp 

i= 

1 

In the input/output relationship, the IT bias factor can be 

set in an arbitrary way, and therefore can be adjusted to 

control the dynamic output range. Fig. 6 gives the circuit 

schema. 

Figure. 6: Current Global Normalizer 


4.1 Design Environment 

The example Soft Max computation system has been 

developed using a TSMC 0,35µm p–substrate technology 

by MOSIS service; the Eldo and IC Flow tools by Mentor 

Graphics supported the circuit simulation and the CAD 

design for the layout phase, together with the Calibre tool 

for post-layout analysis. 

4.2 Experimental Tests 

The tests implemented to verify the functionality of the 

proposed schema involved a case study of n=8 input 

quantities. The maximum admissible input current was 

4µΑ, while the minimum value was 0,5µΑ; the bias value 

for the IT term was set to 10µA. Table I gives the sizes of 

the MOS transistors. 

Stress tests aimed at verifying the implementation 

correctness in a variety of worst-case input distributions, 

in which the input configurations stressed the input 

dynamic range (one input very far from all others).


Table I - MOS Sizes for the SM Circuits 

Transistor W/L (µm) Transistor W/L (µm) 

M4 M10 M12 

M18 M21 M35 1/1 M31 12/1 

M14 M16 2/1 M34 6/1 

M15 M22 5/1 M41 15/1 

M17 1/3 M43 2/2 

M13 M20 M33 3/1 M47 50/1 

M32 M42 100/1 M48 1/10 

Table II gives the post-layout results for three SM gain 

settings in each experiment: K0∈{3,7,15}. Lines 1, 2, and 

3 give the ideal SM values (1) and the predicted approx 

error, respectively. Lines 4-7 give the actual circuit 

outputs and the associated overall approximation errors. 

Table II – Results for worst-case experiments 

Experiment 1 Experiment 2 

Inputs → I1 = 4µA, I2-8 = 0.5µA I1 = 0.5µA, I2-8 = 4µA 

Gain → K0= 3 K0= 7 K0= 15 K0= 3 K0= 7 K0= 15 

S1(Y) 0.0929 0.1102 0.1179 0.1662 0.1415 0.1325 

Si(Y) 

i =2,8 

0.1296 0.1271 0.1260 0.1191 0.1226 0.1239 

Erri∀i 

0.0035 0.0002 0.0000 0.0035 0.0002 0.0000 

see (12) 

() 1 

I out / IT 

0.0884 0.1055 0.1148 0.1756 0.1516 0.1420 

() i 

I out / IT 

i =2,8 

0.1316 0.1300 0.1298 0.1190 0.1233 0.1258 

Actual 

Err1 Actual 

0.0045 0.0047 0.0031 0.0094 0.0101 0.0095 

Erri 

i =2,8 

0.0020 0.0029 0.0038 0.0001 0.0007 0.0019 

Experimental results confirm that the HW-induced error 

well matched theoretical predictions; SM operation was 

also effectively supported, as the overall distortion never 

exceeded 5%. The rapidly decreasing predicted error (12) 

when K0 increases may also suggest that, for large K0 

settings, the power series can stop at the first term (m=1). 

Figure 7: Dynamic Error Behavior 

82 

Another campaign of dynamic tests measured the circuit 

bandwidth, which exceeded 100 kHz. Fig. 7 gives the 

measured dynamic distortion, when the input currents 

were sinusoidal waveforms, with 3µA amplitude and 45° 

phase-shift from one another. The graph shows that the 

dynamic error is a zero-mean sinusoidal waveform, as 

well, and never exceeds a 5% overall distortion. Overall 

power consumption was less than 5mW. 

The area occupation for the complete layout of the 

example Soft Max computation system is approximately 

400x480µm 2 . In Fig.8 an image of the complete layout is 

reported. 

Figure 8: Layout of the 8-input Soft Max system 


A current-mode analogue approach involving a 2-nd order 

approximation can support Soft-Max operation 

effectively. The research presented a modular approach 

that allows a designer to develop SM circuits with a 

predictable and consistent performance. The overall SM 

schema also enables one to control the SM gain 

dynamically 

6. REFERENCES 

[1] Gold S, Rangarajan A, “Softmax to softassign: neural 

network algorithms for combinatorial optimization” 

Journal of artificial neural netwoks, 1995, vol. 2, No. 

4, pp. 381-399. 

[2] Gilbert B. “A Monolithic 16-Channel Analog Array 

Normalizer” IEEE Journal of Solid State Circuits, 

SC-19, No 6, pp. 956-963, Dec 1984 

[3] Lazzaro J, Ryckebush S, Mahowald MA, Mead CA 

“Winner-take-all networks of O(n) complexity” in 

Adv.Neur.Info.Proc. Sys. NIPS 1: Morgan Kaufman, 

1989, pp. 703-711


TOWARD ASYNCHRONOUS AND HIGH DATA 

RATES PASSIVE CONTACTLESS SYSTEMS 

Damien Caucheteux (1)(2) , Edith Beigné (1) , Marc Renaudin (2) , Elisabeth Crochon (1) 

(1) 

CEA, LETI-DCIS – 17 rue des Martyrs 

(2) 

TIMA Lab., CIS-Group – 46 av. Félix Viallet 

38054 Grenoble Cedex 9, France 

38031 Grenoble Cedex, France 

E-mail: damien.caucheteux@cea.fr 

ABSTRACT 

This paper is a contribution to the introduction of a new 

class of contactless remotely powered systems. To 

improve remotely powered device performances, like 

transmission data rates, power consumption and dynamic 

adaptation to environment, fully asynchronous systems 

are used. A new and specific event based communication 

is developed and tested with an inductive link coupling 

model. Post-layout simulations of the asynchronous selfadaptive 

to data rate tag test chip show that a downlink 

communication up to 1.2 Mbps is achieved with a global 

power consumption on tag below 120 µW. 


A contactless system is at least composed, as shown in 

figure 1, of a reader and a tag [1]. The first one is a fixed 

element, connected to a specific data base or network, and 

the second one is a mobile element. The tag receives, 

through the magnetic field, the downlink communication 

and emits back to the reader the uplink communication. 

Reader 

Energy 

Clock 

Data 

Tag 

Few centimeters 

Figure 1. Minimum inductively powered system. 

According to required communication distances and data 

rates, contactless systems usually follow one of the 

13.56 MHz ISO standards [1]. Codes, data rates, modulation 

characteristics and protocols are defined in these 

documents. Table 1 gives some of their characteristics. 

Table 1. Some 13.56 MHz downlink standards. 

Standards Downlink characteristics 

Ref Type Modulation Data rate 

14223 

HDX/FDX ASK 90-100% 6 kbps 

SEQ 90° PSK 500 kbps 

10536 X ASK 100% 9.6 kbps 

14443 

A ASK 100% 106 kbps 

B ASK 10% 106 kbps 

15693 

Low ASK 100% or 10% 1.65 kbps 

Fast ASK 100% or 10% 26.5 kbps 

83 

Protocols can be sequential (SEQ) if the carrier sent by the 

reader is discontinuous, half-duplex (HDX) if uplink and 

downlink communications are alternative on a continuous 

carrier or full-duplex (FDX) if communications are simultaneous 

on a continuous carrier. The standard determines 

data frame to be sent to the tag and fixes the demodulator 

specifications. The tag is then designed to be compatible 

with a reader protocol according to the predefined data 

frame and bit rate. Tag demodulator is resynchronized at 

each start of frame symbol to detect the incoming flow. 

New applications, like electronic keys, contactless cryptography 

smart cards, biometry identification or stimulation 

systems, require high performances contactless systems. A 

solution is to improve power transmission or data rates, to 

allow full-duplex protocol or to reduce power consumption 

[2][3]. Actual proposals are based on fixed synchronous 

protocols and data rates, limiting their use into 

specific environments and distances. If conditions are not 

satisfied, no transmission is possible, whereas applications 

could require to adapt performances to environment, like 

reducing data rate to improve power consumption. 

In this paper, we present a new class of 13.56 MHz inductively 

powered contactless systems to reach high data 

rates, asynchronous transmission and to reduce power 

consumption. Moreover, a self-adaptive to data rate tag 

test chip is designed to detect any modulation data rate. 

First, asynchronous systems properties and motivations 

are presented. Secondly, to outline air interface properties 

and to validate the new event based communication 

scheme, an inductive link modelling methodology is 

described. We finally briefly present, in section 4, a selfadaptive 

to data rate tag architecture and features. 

2. ASYNCHRONOUS SYSTEMS 

2.1 Asynchronous circuit properties 

As an answer to the development of high performance 

applications, some works have proved benefits of asynchronous 

circuits on tag. 

operator 

n 

acknowledge 

data + request 

operator 

n+1 

Figure 2. Local handshake synchronization.

Those systems are based on ISO 14443 standard communications 

[4][5]. To replace the global clock synchronization 

signal, those are locally based on a handshake 

protocol. This is illustrated on figure 2. 

First, the handshake synchronization makes those circuits 

active on demand that’s why they are said data driven. So, 

asynchronous circuits are active where and when needed. 

Moreover, block activations over time are distributed, 

limiting consumption current peaks. Those two properties 

reduce static and dynamic power consumption [6]. Spectrum 

and harmonics of digital circuits are also reduced. 

Secondly, the delay insensitive property of asynchronous 

circuits makes them robust to supply voltage variations: 

this improve remotely powered tag performances. It also 

implements an automatic performance regulation on tag, 

depending on available power. The circuit speed, and so 

its consumption, are automatically reduced when the 

energy received is reduced. This also reduces tag front-end 

constraints and consequently its complexity and area. 

2.2 A fully asynchronous contactless tag 

In this paper, we propose to take advantage of high 

performance solutions and asynchronous circuits: a fully 

asynchronous tag, using an asynchronous event based 

transmission from the reader to the tag, is introduced. To 

adapt tag performances to conditions, a high data rate and 

very flexible variable communication scheme is needed. 

A self-adaptive to data rate front-end enables us not to use 

a predefined and fixed data transmission rate. According 

to asynchronous circuit local synchronization, a global 

data clock is no longer needed. An event based communication 

is introduced here to perform asynchronous transmissions. 

Events notify incoming data to the tag, replacing 

a data transmission clock rising edge. These events are 

said asynchronous because they can appear at any time of 

the carrier phase and at any time after the previous one. 

To achieve the demodulation, the device is continuously 

tracking events on carrier to detect a data on coil. Then, a 

signal acquisition sends an image of the received event to 

an asynchronous event demodulator. Finally, a comparison 

between the detected mark and memorized marks 

enables the tag to recover the signature of this event and 

consequently the associated data value. 

We may notice that there is no timing assumption. Any 

data transmission rate can dynamically be chosen up to 

system performances. 

3. INDUCTIVE LINK MODELING 

3.1 Modeling methodology 

To characterize communications and investigate different 

solutions, a simple, but efficient, model is used. Whereas 

the reader antenna is modeled by a R 1L 1C 1 serial resonant 

circuit, tag’s one is modeled by a R 2L 2C 2 parallel one [3]. 

The general case of an inductive link is then described by 

the equation system giving received voltage on tag V 2 and 


84 

current I 1 through inductance L 1, knowing emissions on 

V 1, circuit characteristics (ω i, Q i and L i) and the inductive 

coupling coefficient k. 

2 

⎧ L ⎛ ⎞ 

1ω1 

ω1 

⎪V 

⎜ 

⎟ 

1 = I1 

+ jL1 

ω − I1 

+ jk L1L 

2ωI 

⎪ Q1 

⎝ ω ⎠ 

⎪ 

⎨ V2 

= jL2ωI 

2 + jk L1L 

2ωI 

1 

⎪ 

2 

Q2 

L2ω 

2 

⎪ V2 

= − I 2 

⎪ 

ω 2 + jQ2ω 

⎩ 

Equation 1. Inductive link model equations. 

These equations, given in equation 1, are the basis of a 

powerful tool for fast investigations. It as been 

implemented on Matlab Simulink to perform fast and 

comprehensive simulations. 

3.2 Main inductive link properties 

Communication characteristics are given in two steps: 

first, static analyses and then, dynamic simulations. Static 

analysis results outline coupling family characteristics 

defined by resonant circuit parameter values [7]. On the 

other hand, dynamic analyses give transient simulations of 

V2 and I1. With this new fast simulation model, fullduplex 

protocol simulation and investigation of parameter 

values influence are possible by resolving a three 

differential equation system deduced from equation 1. 

This model has been validated with a Spice level 

simulation of the reader front-end architecture. 

This model gives important features on modulation 

schemes. As an example, the amplitude received by the 

tag is an important selection criteria: power transfer 

function depends on the amplitude level. That’s why we 

propose an analysis of this criteria. As the tag is designed 

to receive a fixed voltage, the transmitted power decreases 

with signal amplitude. As a consequence, optimal power 

transfer is opposed to an easy ASK (Amplitude Shift 

Keying) demodulation which needs high modulation index 

values. FSK (Frequency Shift Keying), which is a 

frequency modulation, also modulates the received voltage 

amplitude because of the inductive link band pass filtering 

function [8]. At the opposite, the inductive model shows 

that PSK (Phase Shift Keying) creates only a transient 

amplitude modulation. This explains why the model 

shows that phase modulation has good EMI radiations 

results for a given transmitted power. 

Moreover, dynamic simulations of an ISO 14443 standard, 

with a 106 kbps data rate transmission, show that the physical 

limit of this inductive link is high enough to improve 

data rates. Some studies have already proved that the 

phase modulation allows high data rate transmissions [8]. 

In fact, the presented model shows that we can improve 

transmission data rates and choose an efficient downlink 

modulation regarding power transfer efficiency. This 

model leads us to choose an adequate communication 

which is presented below. 

2

3.3 The new event based communication 

A new asynchronous event based communication scheme 

is deduced from those studies. No data clock transmission 

or frequency knowledge is needed: each data is carried by 

a particular mark fitting asynchronous circuit protocols. 

This mark, or event, is not only carrying a data value but 

also a local synchronization, requesting a demodulation. 

To dynamically adapt itself to variable data rates, the 

associated demodulator has to detect incoming marks. 

Moreover, if needed, handshake communications toward 

the inductive link are possible using full-duplex protocol. 

Regarding these specifications and modulation properties 

presented above, we have chosen a phase modulation 

based on π/4 shifts on a 13.56 MHz frequency carrier. 

This leads to a code, illustrated in figure 2-a, called a two 

of eight cyclic code. Whereas phase shifts are implementing 

asynchronous synchronization, their signs are encoding 

the data value (logical 0 or 1). Therefore, with such 

phase shift events, the receiver does not need to know the 

absolute value of the phase but only detects phase shifts. 

3π 

4 

π 

2 

π 0 

3π 

− 

4 

'1' 

π 

− 

2 

π 

4 

π 

− 

4 


'0' 

π 

ϕ n+ 

1 −ϕ 

n = 

4 

(a) 

'1' 

'0' 

1 

0 

1 

0 

ϕ n 

V 2 

data value 

data synchronization 

phase position 

modulated carrier 

(b) 

Figure 4. Event based communication. 

An asynchronous downlink communication, up to 1 Mbps, 

i.e. with a maximum time of 1 µs between two data, has 

been simulated using the inductive link model. An 

illustration of an asynchronous downlink transmission 

simulation is proposed in figure 2-b. Data value and local 

synchronization are first presented. The phase position is 

then illustrated, showing that each new data is coded by a 

level transition. Finally, the signal received on coil, V2, is 

simulated using the inductive link model. 

A new high data rate asynchronous reader to tag transmission 

is proposed. Whereas all previous devices are using a 

fixed and predefined data rate, this new asynchronous 

event based communication allows tags to receive any 

data rate up to a maximum value. Moreover, the phase 

modulation is an efficient tool to provide high power 

transmission to tag. Furthermore, the event transmission is 

the key point to the introduction of a new class of selfadaptive 

to data rate contactless devices. The next section 

explains the design of an asynchronous event based 

communication demodulator on a remotely powered tag. 

t 

t 

t 

t 

85 

4. ON TAG DEMODULATION 

A remotely powered device front-end is generally first 

composed of high voltage functions to control supply voltage, 

modulation, etc. Secondly analog functions provide 

stable current references, signal extraction, etc. However, 

a fully asynchronous tag does not need any clock generation 

neither a high performance voltage regulation to 

supply digital blocks. As a consequence, the tag front-end 

is simplified and its area reduced. Finally, an interface 

makes digital circuits compatible with the analog frontend. 

Here, the classical global architecture and main 

functions of a contactless remotely powered device are not 

presented. For more information, we advise to read the 

RFID Handbook 2 nd Edition [1]. 

To detect data events, a charge pump PLL structure, 

illustrated on figure 5, is implemented on tag. A digital 

Phase and Frequency Detector (PFD) is used to analyze 

phases and to activate the Charge Pump (CP). It compares 

the signal received on coil with an internal reference 

generated by the Voltage Controlled Oscillator (VCO). 

Ext-Ref 

Int-Ref 

PFD CP 

VCO 

Up 

Down 

Ultra Low Power PLL 

APJD 

Multi 

Rail 

Asynchronous 

Phase Jump 

Detector 

Figure 5. PLL and demodulation architecture. 

The asynchronous event based communication demodulation 

is achieved by an Asynchronous Phase Jump Detector 

(APJD). It produces on its outputs a data using PFD 

results. First of all, each phase shift received on signal Up 

or Down, is filtered to dissociate data events from phase 

noise. A succession of filter cells gives n different images 

of the same phase shift, with different filtering characteristics 

chosen according to tag position in the field. 

Then, knowing the encoding scheme, the signature detection 

links phase variations with received data: selection of 

a filtering characteristic, detection of the event envelop, 

and conversion in a compatible asynchronous circuit code. 

As no data clock is needed, the data rate can dynamically 

take any value up to link and circuit performances. 

In - 

V CC 

V cont 

Out + Out - 

I pol 

Symmetric Load 

Figure 6. Self-regulated differential delay cell. 

In +

The second key point is the design of an ultra low power 

VCO around 13.56 MHz to create the internal reference. 

The VCO is designed using a ring oscillator composed of 

three differential voltage controlled delay cells [9]. 

Moreover, a self-regulated function is added to perform an 

ultra low supply voltage sensitivity [10]. The VCO power 

consumption is 16 µW and output frequency variations are 

below 1 % with supply voltage variations up to 20 %. 

Normalized frequency 

1,01 

1,005 

1 

0,995 

0,99 

Typical process 

Worst speed process 

0,985 

0,98 

Worst power process 

620 720 820 

Supply voltage (mV) 

920 1020 


Supply sensitivity 

300 K 

Figure 7. VCO supply voltage sensitivity. 

The analog tag front-end is designed to reach high performance 

and low power consumption features. As shown in 

table 2, the front end consumption is below 120 µW 

during a 1 Mbps demodulation. During standby mode, tag 

waiting for events, power consumption is lower by 10 %. 

Moreover, downlink transmissions can take any rate up to 

1.2 Mbps at 10 cm. Compared to similar front-end 

architectures, with a 1 Mbps phase demodulation and a 

13.56 MHz carrier [8], power consumption of our design 

is lower by a factor 6. 

Table 2. Post-layout simulations. 

Reader to Tag distance (cm) 0 6 10 

Supply Voltage VCCA (V) 1.18 1.04 0.94 

I(VCCA) (µA) 98.3 84.8 79.5 

Power consumption (µW) 116 88.2 74.7 

Maximum data rate (Mbps) 1.0 1.2 1.2 

5. CONCLUSION 

A fully asynchronous and self-adaptive to data rate 

contactless system has been developed. An asynchronous 

event based communication protocol using a phase 

modulation and a two of eight cyclic code has been 

adopted because it fulfils the functional requirements we 

target as well as silicon implementation requirements. 

Indeed, the proposed contactless system enables us to 

increase and dynamically adjusts the transmission rate, to 

lower the power consumption and to simplify the 

architecture. 

Post-layout simulations have shown that a downlink 

transmission rate of up to 1.2 Mbps can be achieved. 

Moreover, the proposed architecture is low power and has 

86 

a low sensitivity to the supply voltage. This will extend 

the usage conditions and performances. The chip of this 

architecture, developed using a 130 nm standard CMOS 

process, is currently under test. It has to prove the benefits 

brought by this new approach and validate the uplink 

communication scheme. 

6. ACKNOWLEDGEMENTS 

The authors would like to thank for their help all CEA- 

LETI teams which have been working on this project. 

7. REFERENCES 

[1] K. Finkenzeller, RFID Handbook, Fundamentals and 

Applications in Contactless Smart Cards and 

Identification, Second Edition, John Wiley & Sons 

Ltd, 2003. 

[2] M. Ghovanloo and K. Najafi, A Wideband Frequency 

Shift Keying Wireless Link for Inducti-vely Powered 

Biomedical Implants, IEEE Transac-tions on Circuits 

and Systems, vol. 51, n° 12, 2004. 

[3] D. C. Galbraith, M. Soma and R. L. White, A Wide- 

Band Efficient Inductive Transdermal Power and 

Data Link with Coupling Insensitive Gain, IEEE 

Transaction on Biomedical Engineering, vol. 34, 

n° 4, 1987. 

[4] J. Kessels, T. Kramer, G. d. Besten, A. Peters and 

V. Timm, Applying Asynchronous Circuits in 

Contactless SmartCards, IEEE 6th Int. Symposium on 

Advanced Research in Asynchronous Circuits & 

Systems, ASYNC’00, April, 2000, pp. 36-44. 

[5] A. Abrial, J. Bouvier, M. Renaudin, P. Senn and 

P. Vivet, A New Contactless Smart Card IC Using an 

On-Chip Antenna and an Asynchronous Microcontroller, 

IEEE Solid-State Circuits, vol. 36, n°7, 2001. 

[6] M. Renaudin, Asynchronous circuits and systems : a 

promising design alternative, Microelectronics 

Engineering Journal, Elsevier Science, vol. 54, 

n° 1-2, Dec. 2000, pp. 133-149. 

[7] P. Doguet, Integrated stimulator for visual 

prosthesis, PhD thesis, Université Catholique de 

Louvain, 2000. 

[8] J. F. Gervais, J. Coulombe, F. Mounaim and M. 

Sawan, Bidirectional High Data Rate Transmission 

Interface for Inductively Powered Devices, IEEE 

Canadian Conference on Electrical and Computer 

Engineering, vol. 1, pages : 167-170, 2003. 

[9] J.G. Maneatis, Low-Jitter Process-Independent DLL 

and PLL Based on Self-Biased Techniques, IEEE 

Journal of Solid State Circuits, vol. 31, n° 11, Nov., 

1996, pp. 1723-1732. 

[10] I.C. Hwang, C. Kim and S.M. Kang, A CMOS Self- 

Regulating VCO with Low Supply Sensitivity, IEEE 

Journal of Solid-State Circuits, vol. 39, n° 1, Jan., 

2004, pp. 42-48.


A DIGITAL-PLL-BASED TRUE RANDOM 

NUMBER GENERATOR 

Chengxin Liu, John McNeill 

Worcester Polytechnic Institute, Electrical and Computer Engineering Department, 

100 Institute Road, Worcester, MA 01609, USA 

E-mail: mcneill@ece.wpi.edu 

ABSTRACT 

A true random number generator (RNG) based on a 

digital phase-locked loop (PLL) has been designed and 

implemented in a 1.5um CMOS process. It achieved an 

output data rate of 100 kbps from the sampling of two 

30MHz ring oscillators, and successfully passed the NIST 

test suite SP800-22. 


Several emerging cryptographic applications such as smart 

cards and pervasive computing require a low cost solution 

to the problem of obtaining high quality random numbers 

in system-on-chip designs for secure data communication. 

The most popular approach by far is the method of 

oscillator-sampling [1][2] due to the advantages of less die 

area, power efficiency, and high speed. 

As illustrated in Fig. 1, a low frequency oscillator with 

high jitter samples the output of a high frequency 

oscillator using a D flip-flop to produce the randomnumber 

sequences. In order to achieve high level 

randomness, the rms jitter of the low frequency oscillator 

must be much greater than the period of the fast oscillator 

[2]. Experimental results in [2] have shown that for 

CMOS ring oscillators in a 0.18um digital library, the 

jitter to mean period ratio is less than 10 -4 , which limits 

the maximum output data rate to 100 kbps if a 1GHz fast 

oscillator is used. 

This paper presents a new dual-oscillator sampling 

architecture for random number generation. The main 

advantage over the traditional approach is the capability of 

achieving the same data rate using slower clocks, thus 

cheaper process and lower cost. Section 2 reviews the 

jitter theory of ring oscillators and PLLs. The RNG 

architecture and circuit details are discussed in section 3. 

Section 4 gives the experimental results. 

High Freq. 

Oscillator 

Noisy Low 

Freq. Oscillator 

Figure 1. Traditional oscillator-based RNG 

D 

Q 

Random Bit Stream 

87 

2. JITTER IN PLLS 

2.1 Jitter and phase noise in ring oscillators 

White noise and 1/f noise are the main noise sources in 

MOS transistors which will be upconverted to phase noise. 

Fig. 2 shows the typical phase noise spectrum and time 

domain plot of rms jitter versus measurement time delay 

for open-loop ring oscillators in log-log scale. 

( ( f ) ) 

log SΦ − 30dB/ 

dec 

Nf 1 

f 

c 

3 

fc 

− 20dB 

/ dec 

N1 

2 

f 

log(f ) 

) 

log(σ ∆T 

slope=0.5 

κ ∆T 

tc 

slope=1 

ζ∆T 

log( ∆T) 

(a) Frequency domain (b) Time domain 

Figure 2. Jitter and phase noise in ring oscillators 

The -20dB/dec region in the phase noise spectrum is due 

to the white noise and has the form of 

N1 

SΦ W ( f ) = (1) 

2 

f 

where N1 is the frequency domain white noise figure of 

merit, and f is the offset frequency from the carrier. It is a 

Gaussian random process in the time domain simply 

reflecting the central limit theorem in statistical theory. 

The rms jitter after measurement time delay ∆T is [3] 

σw( ∆ T) = κ ∆ T 

(2) 

where κ is the time domain white noise figure of merit 

which is determined by the delay cell parameters, and is 

independent of the number of stages in the ring [3]. κ is 

related to the frequency domain figure of merit N1 by [3] 

N1 

κ = (3) 

f0 

where f0 is the VCO’s oscillating frequency. 

1/f noise upconverted phase noise dominates at the lower 

offset frequencies and thus longer time delays. It has a 

slope of –30dB/dec in the phase noise spectrum with the 

representation of [4] 

Nf 1 c SΦ 

1/ f = (4) 

3 

f

where fc is the 1/f 3 phase noise corner [4]. In time domain, 

it is a correlated random process. The accumulated rms 

jitter is proportional to the measurement time delay as 

σ1/ f ( ∆ T) = ζ∆ 

T 

(5) 

where ζ is time domain 1/f noise figure of merit. 

2.2 Jitter and phase noise in PLLs 

The noise transfer function of PLL corresponds to the 

high-pass transfer function. If the PLL loop bandwidth is 

wide enough to cover the 1/f 3 phase noise corner fc, the 

upconverted 1/f noise jitter can be filtered out, leaving 

only the filtered white noise as in Fig. 3. This remaining 

noise has a Gaussian distribution and the jitter process is a 

correlated white noise process. 

The closed-loop phase noise spectrum has the form of 

2 

N1/ fL 

SΦ CL ( f ) = (6) 

2 

1 + ( f / fL 

) 

where fL is the PLL loop bandwidth. By the Wiener- 

Khinchine theorem, the autocorrelation function of this 

jitter process can be obtained by taking inverse Fourier 

transform of its power spectrum density (6). Therefore the 

autocorrelation coefficient of this jitter process is 

calculated as 

ρ xx ( ∆t ) =exp( -2πfL∆t) (7) 

And the rms jitter with respect to the PLL reference clock 

is as [3] 

1 

σx= κ 

(8) 

4π 

fL 

So for white noise dominated PLL, only κ and the PLL 

loop bandwidth fL are needed for jitter prediction. 

( ( f ) ) 

log SΦ fc 

fL 

N 

f 


1 

2 

log(f ) 

) 

log(σ ∆T 

κ ∆T 

τ L 

tc 

2σ x 

log( ∆T) 

(a) Frequency domain (b) Time domain 

Figure 3. Jitter and phase noise in PLLs 

DACCtrl 

Ring Oscillator II 

Bias 

DACCtrl 

Ring Oscillator I 

Data 

D Q 

24-bit up/down 

counterp 

Clk 

9 bits 

RandomBits 

Post -processing 

1-bit up/down 

counter z 

Figure 4. The proposed RNG architecture 

8 bits 

1 bit 

88 

3. RNG DESIGN 

3.1 System architecture 

The proposed RNG architecture is illustrated in Fig. 4. 

Two identical noisy ring oscillators are designed with 

white noise dominated jitter. Oscillator І is free-running 

and serving as the clock. The phase error of the two 

oscillators is sampled by a low metastability D flip-flop, 

which also acts as a bang-bang phase detector. Two 

up/down counters form the loop filter. The 24-bit up/down 

counter p integrates the phase error of the two ring 

oscillators to set the average frequency of oscillator II, and 

introduces a pole to the loop transfer function. The 1-bit 

up/down counter z introduces the zero to stabilize the 

loop, and provides instantaneous phase correction without 

affecting the average oscillating frequency. Therefore the 

two oscillators are always synchronized through the 

feedback. The whole system is powered by a voltage 

regulator to reject the noise from the power supply. It 

should be noted that the whole system is nonlinear and 

thus it is difficult to be modeled analytically. 

If the loop bandwidth is wide enough to filter out the 1/f 

noise upconverted jitter, the jitter difference of the two 

oscillators is simply correlated white noise. After sampled 

by the D flip-flop, a correlated data stream with equal 

probability for ‘1’s and ‘0’s is generated. From equation 

(7), by dividing the output data rate down to around or 

below the PLL loop bandwidth, the autocorrelation of the 

output data can be significantly decreased so that the data 

stream can be considered as random. Therefore for the 

proposed RNG, the maximum data rate achievable is 

limited by the loop bandwidth of this system. Since the 

PLL loop bandwidth can be as high as 10% of the clock 

frequency, ideally the maximum RNG data rate can be as 

high as 10% of the ring oscillator frequency. 

However, wider loop bandwidth results in lower PLL 

output jitter according to equation (8). The output jitter 

should be much larger than the LSB of the DAC, or the 

phases of the two ring oscillators will not be synchronized 

but oscillate. Thus the key factors of this design are the 

DAC resolution and the noise figure of merit κ. 

3.2 Time domain analysis 

As illustrated in Fig. 5, in the presence of jitter and 

assuming there is no frequency drift, the transition time for 

the two oscillators can be expressed as 

t1[ n] = t1[ n− 1] + T1+ ε1[ 

n] 

(9) 

t2[ n] = t2[ n− 1] + T2[ n] + ε 2[ 

n] 

(10) 

where T1 is the constant average period of the free-running 

oscillator I, T2[n] is the average period of the oscillator II 

in the n th interval, and εi[n] is zero-mean, discrete 

Gaussian random process which expresses the deviation of 

the period from the average. Since white noise dominates, 

the random process εi[n] is uncorrelated. From equation 

(2), the standard deviation of εi[n] is as 

σ = κ T i = 1, 2 

(11) 

ε i i i

t[1] 

t[2] 

T+ε[1] 0 

0 T+ε[2] 0 T+ε[n] 


t[n] 

Figure 5. Def. of random processes for clock with jitter 

Assuming there is no metastability for the D flip-flop, the 

phase error sequence rb[n], which is also the output 

sequence of this RNG system, is as 

rb[ n] = ( sign( td[ n] 

) + 1 ) /2 

where sign() is the signum function, and td[n] is 

(12) 

td[ n] = t1[ n]- t2[ n] 

= t[ n−1] −t [ n− 1] + T − T [ n] + ε [ n] −ε 

[ n] 

(13) 

( ) ( ) ( ) 

1 2 1 2 1 2 

Since ε1[n] and ε2[n] are independent zero-mean Gaussian 

random processes, their difference is also a zero-mean 

Gaussian random process. The first two difference terms 

in equation (13) indicate the correlation of td[n] with its 

previous bits. Therefore the sequence td[n] is a correlated 

random process. 

The frequency of oscillator II is adjusted in every clock 

cycle and can be modeled as 

f2[ n+ 1] = f2[1] −( kp⋅ ctrp[ n] + kz⋅ctrz[ n] ) ⋅ Kvco 

(14) 

where kp and kz are the gain of the counters p and z, ctrp[n] and ctrz[n] are their counting results, and Kvco is the 

oscillator control constant in the unit of Hz/bit. 

In the implementation of this design, the eight most 

significant bits of the 24-bit counter p are connected to the 

DAC control of the oscillator I, while the output of 1-bit 

counter z is connected to the DAC directly. So equation 

(14) changes to 

16 

f2[ n + 1] = f2[1] − ( fix( ctrp[ n]/2 ) + ctrz[ n] ) ⋅ Kvco 

(15) 

where fix(A) is the Matlab fix function which rounds the 

elements of A toward zero, resulting in an array of 

integers. 

The loop bandwidth of this digital PLL system is 

proportional to the oscillator control constant Kvco, and the 

counters’ gain, kp and kz. Fig. 6 shows the loop acquisition 

process simulated by Matlab for different number of bits 

in counter p. A shorter locking time indicates a wider loop 

bandwidth. 

t d[n]=t 1[n]-t 2[n] 

(ns) 

50 

0 

14-bit 

-50 16-bit 

f 1=30MHz 

f 2[1]=29.9MHz 

-100 18-bit 

t d[1]=20ns 

σ εi =60ps 

-150 

0 50 

t(µs) 

100 

K VCO =40kHz/bit 

150 200 

Figure 6. Loop acquisition simulated by Matlab 

t 

89 

3.3 DAC-controlled ring oscillator 

The DAC-controlled ring oscillator is realized by adding a 

capacitor array to the load of the 3-stage single-ended ring 

oscillator as illustrated in Fig. 7. To provide more jitter, 

the current-starved inverter with six extra 50K resistors at 

the voltage control nodes is used as the delay stage instead 

of the simple CMOS inverter. The two ring oscillators are 

totally symmetric and next to each other in the layout. 

Thus the deterministic jitter due to the power supply and 

substrate is in common-mode and will be rejected. 

Vdd 

Vp 

Vn 

9 control bits 

Z0 F0 F1 F7 

1x 1x 2x 128x 

Figure 7. The DAC-controlled ring oscillator 

out 

Cload 

For the current-starved inverter, the noise figure of merit κ 

can be maximized by minimizing the power dissipated for 

inverter switching [5]. Minimum sizes are used for the 

switching NMOS transistors to achieve higher κ with fast 

available speed. PMOS transistors are sized relative to 

NMOS transistors to provide symmetric rise and fall 

times. The control transistors are twice the size of the 

switching transistors, and are biased with very small 

excess gate-source voltages to limit the switching current. 

3.4 Low metastability D flip-flop 

Since the edges of the oscillators are always aligned to 

each other, a low metastability falling edge triggered D 

flip-flop is designed in this work as in Fig. 8. When the 

CLK is high, both the pre-amplifier [6] and the D latch [6] 

will be reset. The transmission gate is on and the data is 

sampled. When the CLK switches to low, the transmission 

gate is closed to hold the data. The pre-amplifier amplifies 

the difference between the held data and vdd/2, and the D 

latch regenerates it to a valid logic level. To reduce the 

metastability error, two D flip-flops are cascaded. 

Data 

CLK 

CLK 

+ 

Pre-Amp 

− 

CLK Vdd/2 

CLK 

Reset 

+ 

D Latch 

− 

Figure 8. The low metastability D flip-flop 

3.5 Digital post-processing 

In order to lower the autocorrelation, the raw output data 

stream of the digital PLL system is divided down by 10 

first and then fed into a Von Neumann corrector to 

eliminate the bias. Finally another frequency divider is 

used to further reduce the autocorrelation. 

Q


The customized part of this design including the 

oscillators, the D flip-flops, and the voltage regulator are 

implemented in a 5V 1.5um 2-poly 2-metal CMOS 

process and consume an area of 1mm 2 . The chip 

micrograph is shown in Fig. 9. Excluding the output 

buffers, the total power dissipation is 1.92mW. The 

counters and the digital post-processing circuits are 

implemented in an off-chip FPGA for design flexibility. 

DAC1 

DAC2 


Ring1 

Ring2 

Figure 9. The die photo 

2 DFFs 

Resistors 

The two oscillators are running at 30MHz in this RNG 

system. Fig. 10 shows the measured plot of the rms jitter 

over measurement time delay for the open-loop ring 

oscillators. The extracted white noise figure of merit κ is 

1.48E-7. 

RMSJitter (sec) 

10 -9 

10 -10 

10 -11 

κ=1.48E-7 

10 -7 

ζ =2.52E-4 

Meas. Time Delay (sec) 

10 -6 

Figure 10. Jitter performance of the free-running 

ring oscillators at 30MHz 

By analyzing the autocorrelation of the raw output data 

before post-processing, the extracted equivalent loop 

bandwidth of this PLL system is around 500 kHz. Thus 

the rms jitter of this system is about 60ps according to 

equation (8). The DAC has a measured LSB of 44ps with 

the total adjusting range of ±1.6ns. The resolution is not as 

fine as expected due to variation in the fabrication process. 

Thus it was necessary to apply more division than 

expected to lower the autocorrelation sufficiently, and a 

data rate of only 100 kbps is achieved. It is expected that 

this rate will be improved in a future iteration of the 

design. 

The quality of the randomness has been verified by the 

NIST SP800-22 test suite [7] over 2Mbit long sequences. 

This test suite consists of 16 statistical tests, and the 

passing criteria for each test is that the p-value is larger 

than 0.01. Table 1 shows the complete test results for 3 

data sequences. 

90 

Table 1. NIST SP800-22 statistical test results 

Test 

P-value 

Data Set I Data Set II Data Set III 

Frequency 0.403123 0.321518 0.346485 

Block Frequency 0.151636 0.755148 0.055258 

Cusum-Forward 0.323588 0.556027 0.677662 

Cusum-Reverse 0.338798 0.243561 0.506432 

Runs 0.17792 0.194128 0.903376 

Longest Run 0.891002 0.945998 0.124246 

Rank 0.239545 0.24964 0.141371 

FFT 0.270026 0.6652 0.718271 

Universal 0.685955 0.673109 0.841297 

Approx. Entropy 0.399766 0.196523 0.981364 

Serial1 0.866552 0.183901 0.619666 

Serial2 0.793059 0.411532 0.319159 

Lempel Ziv 1.000000 1.000000 1.000000 

Linear Complexity 0.448407 0.187954 0.980834 

Periodic Templates 0.362154 0.65189 0.299952 

Aperiodic Templates all passed all passed all passed 

Random Excursions all passed all passed all passed 

Random Ex. Variant all passed all passed all passed 

5. CONCLUSION 

A new type of true RNG based on digital PLL has been 

proposed. The random bits are generated by the jitter 

sampling of two identical synchronized ring oscillators. 

Comparing to the traditional oscillator sampling approach, 

this method is able to achieve higher data rate when using 

same speed of clocks. This structure has been realized in a 

1.5um process, and has successfully passed the NIST 

SP800-22 statistical test suite. 

6. REFERENCES 

[1] B. Jun and P. Kocher, The Intel random number 

generator, Technical Report, Intel, 1999. 

[2] M. Bucci et al., A high speed oscillator-based truly 

random number source for cryptographic applications 

on a smart card IC, IEEE Trans. on Computers, vol. 

52, No. 4, pp. 403-409, 2003. 

[3] J. McNeill, Jitter in ring oscillators, IEEE J. Solid- 

State Circuits, vol. 32, No. 6, pp. 870-879, 1997. 

[4] C. Liu and J. McNeill, Jitter in oscillators with 1/f 

noise sources, Proc. IEEE ISCAS’04, vol. 1, pp. 773- 

776, 2004. 

[5] C. Liu and J. McNeill, Jitter in deep submicron 

CMOS single-ended ring oscillators, Proc. 5 th 

International Conference on ASIC, pp. 715-718, 

2003. 

[6] C. Portmann and T. Meng, Power-efficient 

metastability error reduction in CMOS flash A/D 

converters, IEEE J. Solid-State Circuits, vol. 31, No. 

8, pp. 1132-1140, 1996. 

[7] A. Rukhin, el. A statistical test suite for random and 

pseudorandom number generators for cryptographic 

applications, NIST Special Publication 800-22, 2001.


A 11-15 GHz CMOS ÷2 FREQUENCY DIVIDER 

FOR BROAD-BAND I/Q GENERATION 

Annamaria Tedesco, Andrea Bonfanti, Luigi Panseri, Andrea Lacaita 

Dipartimento di Elettronica ed Informazione - Politecnico di Milano, 

P.za Leonardo da Vinci 32, I-20133 Milano, Italy 

E-mail: panseri@elet.polimi.it 

ABSTRACT 

This paper presents a 0.13 µm CMOS frequency divider 

for I/Q generation. To achieve a wide locking range, a 

novel topology based on a two stages injection-locking 

ring oscillator is adopted. This architecture can reach a 

larger input frequency range and better phase accuracy 

with respect to injection-locking LC oscillators, because of 

the smoother slope of its phase-frequency plot. Post layout 

simulations show that the circuit is able to divide an input 

signal spanning from 6 to 24 GHz, although the available 

tuning range of the signal source (integrated VCO) limited 

the experimental verification to the interval 11-15 GHz, 

with a consequent measured 31% locking range. A single 

divider dissipates 3 mA from 1.2 V power supply. 


High-speed frequency dividers are among the most critical 

building blocks in modern CMOS wireless tranceivers. 

They are employed both in the feedback path of Phase 

Locked Loops (PLL) and to generate the I/Q quadrature 

signals necessary in zero- or low-IF receivers. The design 

of a fully integrated CMOS divider is critical, above all for 

its power consumption that is comparable to the one of the 

Voltage Controlled Oscillator (VCO). This problem 

becomes even more severe when a wide input frequency 

range is required, since in this case it is not possible to 

adopt resonant loads, that would allow power reduction. 

Moreover, the dissipation of a broad-band buffer, usually 

interposed between the VCO and the divider itself, must 

be also taken in to account in the total power budget. We 

discuss a topology for a ÷2 frequency divider for I/Q 

generation in a WLAN transceiver for IEEE 802.11a/b/g 

standards. In the frequency synthesizer only one VCO will 

be employed, and a first divider provides the I/Q signals 

for the 802.11a channels without using an input buffer. 

Then, a following divider makes the signals for the 2.5 

GHz band available. The key advantage of this 

architecture is that VCO pulling is avoided. Given the 

channellizations of the standards, the input frequency of 

the first divider must vary between 9.6 and 11.6 GHz, 

leading to 18 % input tuning, or locking, range. However, 

a more conservative figure for the locking range is 35%, to 

account for the process spreads in the VCO. In the next 

section we will recall why such high tuning range makes 

not possible to adopt some recently presented low-power 

91 

solutions, as LC injection locking topology. Then we 

discuss the circuit topology and we show why this circuit 

can achieve a wide tuning range. We present the circuit 

implementation, some experimental results and, then, the 

conclusions will follow. 

2. HIGH-SPEED DIVIDERS 

High-speed dividers are typically realized as two latches in 

a negative feedback loop [1]. For multi-GHz input signals, 

these circuits have a differential current-steering structure 

that allows fast current switching, usually called sourcecoupled 

logic (SCL). To reduce the dissipation a dynamic 

logic was employed in [2], but it does not provide I/Q 

outputs. Probably, the best solution in term of power 

consumption is to differentially drive two injection 

locking LC oscillators, as in [3]. With respect to the SCL 

dividers the dissipation reduces by about Q, the quality 

factor of the divider’s resonant tank, at the cost of a large 

area occupation. Unfortunately, this topology is 

intrinsically narrow band: to increase the divider locking 

range the quality factor Q of the LC tanks must be 

lowered with a resulting rise in dissipation. Our locking 

range requirements demand a low Q, close to two, 

practically voiding the effect of the LC resonance. In this 

sense, power is traded not only with speed, but also with 

input locking range. A further example of this trend is the 

40 GHz divider presented in [4], which demonstrates good 

power performance but features 6 % locking range. 

2.1 Proposed injection-lock ring divider 

Our approach was to injection-lock a wide tuning range 

oscillator, namely a two-stages ring oscillator. Self 

oscillating dividers have also the useful property of 

requiring less power from the driving signal, avoiding the 

use of a power consuming buffer. Fig.1 shows the circuit 

scheme and the detail of one stage. Simulations show that 

the transfer function of the single stage can be 

approximated as: 

( ) 

1− jω 

ω 

+ ω ω 

T jω = T0 1 j 

The small signal dc gain is T 0 = g mi R/(1 – g mc R), being g mI 

and g mc the transconductances of transistors M 1 -M 2 and M 3 - 

z 

p 

(1)

+ _ 

0° 

I 

ω in 

2ω in 

+ _ 

180° 

M respectively. The dominant pole frequency is ω =(1– 

4 P 

g R)/C R, where C is the output load capacitance. 

mc O O 

Owing to the gate-drain overlap capacitance of the input 

couple M -M , the transfer function also exhibits a right 

1 2 

half-plane zero at higher frequency, ω = g /C To satisfy 

Z mi gd 

the Barkhausen criterion for loop phase, a lag of – π/2 

radians is required for each stage, providing in this way 

the quadrature outputs. The cross-connection between the 

two stages in Fig.1 gives the remaining phase shift of π. 

The – π/2 delay is reached only thanks to the right zero, 

and it is straightforward from (1) to evaluate that this shift 

is achieved at a frequency corresponding to the geometric 

mean between the pole and the zero. The ring oscillation 

frequency is thus ω0 = (ωp ωz) 1/2 . Using (1) and the 

Barkhausen criterion for loop magnitude, we obtain the 

condition for the dc gain: T0(ωp /ωz) 1/2 = 1. Then, when 

the amplitude rises, the “effective” transconductance of 

the cross-coupled pair M3-M4 reduces with respect to the 

initial small signal value g /2, until the oscillation 

mc 

becomes stable. It’s important to note, from the expression 

of the dominant pole frequency, that also ωP and, 

accordingly, ω0 vary. Both ωP and ω0 increase when the 

transconductance of the pair M3-M4 lowers. In an 

oscillator this effect would lead to very poor performance 

in term of frequency stability and phase noise. In our 

application we do not face this problem, since the circuit is 

driven by an input signal. 

A similar analysis can be found in [5], though the circuit 

in that case is a standard SCL divider, and only simulation 

results are shown. In our case the cross-coupled pair acts 

as a gain-boosting stage at the start-up and then as an 

amplitude limiter to stabilize the oscillation, and not as a 

latch for data holding. An injection-locking ring is also 

discussed in [6]. In that paper however, the circuit only 

generates the I/Q signals without dividing the VCO 

output, that could suffer from pulling effect. 

2.2 Lock Range and Phase Accuracy 

The two differential outputs of the VCO, running at 2ω in , 

drive the divider through the tail transistors of the two 

stages, M 5 in Fig. 1 and the analogous one of the other 

stage. In this way the injected current i in , at 2ω in is 


Q 

+ 

2ω in 


R 

_ 

V bias 

M1 g M2 mi 

M5 V DD 

Figure 1. Ring frequency divider driven by a 

differential VCO. The scheme of one stage is also 

+ R 

M 3 

_ 

g mc 

M 4 

92 

I DC@0 

i in@2ω in 

v2 α 

ϕ 

V1 ω in 

1° Stage 

-1 

superimposed to the dc tail bias current I . In this way the 

DC 

ring is forced to oscillate at ω , which is in general 


different from ω . The mechanism of injection locking has 

0 

been rigorously discussed by many authors, see for 

instance [3], [6], [7] and is intuitively recalled with the 

help of Fig. 2. 

A steady condition is reached when the ring oscillates at 

ω . In this case the input pair M -M in Fig. 1 behaves as a 

in 1 2 

mixer for the signal coming from the tail and thus 

converts I and i to ω . The dominant pole of each stage 

DC in in 

filters out the higher-frequency products. Since ω differs 


from ω , the lag of each stage is not exactly –π/2 but it is – 

0 

π/2–ϕ. The mixer stage must balance this phase shift 

ϕ adding the opposite shift to its output. That is sketched 

in Fig. 2, where all the represented phasors rotate at ω . V in 1 

represents the output signal as a result of the dc current, 

while v is the additional signal caused by the injected 

2 

current. The loop adjusts the phasors, by settling the angle 

α, in order to obtain an additional shift ϕ, with respect to 

the state in which there’s not injection of current. It is easy 

to see that when a differential signal, i and –i , is forced 

in in 

in the two stages, their outputs are still in quadrature. It is 

also possible to evaluate which is the the maximum 

frequency deviation, ∆ω, from ω so that the divider can 

0 

properly operate, [7]. If we call SL the magnitude of the 

slope, evaluated at ω , of the phase vs. frequency 

0 

characteristic of T(jω), it results SL ≅ ϕ/∆ω. If we define 

the injection strength m = v /V = i /I , Fig.2 shows that, 

2 1 in DC 

with a good approximation, is ϕ ≅ m, and consequently 

max 

∆ω ≅ m/SL. Consequently the lock range increases with 

max 

m, and it is also inversely proportional to SL. From 

equation (1) it is possible to simply evaluate the 

magnitude of the slope. Recalling that the expression for 

the free running frequency, ω0, is ω0 = (ωP ωZ) 1/2 , it 

results: 

dϕ 

SL = = 2 ω +ω 

ω 

d ω 

0 

( p z ) 

I DC@0 

-i in@2ω in 

For a given ω 0, this value is much smaller than the 

corresponding one in an LC tank oscillator, namely 2Q/ω 0 . 

In fact, first, the arithmetic mean (ω p + ω z )/2 is always 

larger than the geometric mean, ω 0 . Second, the factor 2Q 


2° Stage 

ϕ α v2 V1 Figure 2. The injection locking mechanism in 

the two stages ring oscillator. 

(2)

210µm 

54µm 

is usually greater than one. Thus, the lock range obtained 

is accordingly larger. Moreover a low value of SL 

provides also benefits to the quadrature accuracy. The 

quadrature error is due to the mismatch between the values 

of ω 0 in the two stages. For a difference dω 0 , a 

corresponding variation dϕ must thus occur. That can be 

achieved only by changing the angle α between the 

vectors V 1 and v 2 . This shift dα, is the quadrature error. 

From the phasors diagram in Fig.2 we obtain that: 


300µm 

36µm 

Figure 3. Die photo. 

2 

1+ m + 2mcosα 

dα= dϕ m m cos 

( + α) 

VCO 

High speed divider 

Since the magnitude of dϕ is approximately |dϕ| ≅ SL 

|dω 0|, also in this case a smoother slope SL is beneficial. 

3. CIRCUIT REALIZATION 

A cascade of two dividers has been integrated in a STM 

0.13µm CMOS technology. A differential VCO as signal 

source and a quadrature mixer are integrated on the same 

die. The two circuits have the same topology, with the 

difference that in the second divider the bias current is 

almost half of the first divider, because of its halved 

operating frequency. Fig. 3 shows a photo of the chip. The 

inductors of a differential LC-tank VCO fill most of the 

area. The only signals available are the ones at the output 

of the VCO and of the second divider. Moreover in order 

to let the first circuit oscillate in free running mode, it is 

possible to switch-off the power supply of the VCO. 

Post-layout simulations show that the first circuit can 

operate with an input frequency varying between 6 and 24 

GHz. Fig. 4 shows the simulated sensitivity curve between 

the minimum amplitude of the input signal of the first 

divider and its operating frequency. At 19 GHz the 

amplitude of the voltage signal at the input of the divider 

is zero. This means that the divider operates in free 

running mode. 

(3) 

93 

Input Voltage [V] 

1.2 

1.0 

0.8 

0.6 

0.4 

0.2 

0.0 

6 8 10 12 14 16 18 20 22 24 

Input Frequency [GHz] 

Figure 4. Simulated sensitivity curve between 

the minimum amplitude of the input signal of 

the first divider and its operating frequency. 


As previously discussed, one characteristic of these 

dividers is the capability to operate both driven by an 

input signal and in free running mode For comparison, 

two measured output spectra are superimposed in Fig. 5. 

The spectrum on the left side was measured when the 

divider chain is driven by the VCO. Its center frequency, 

shifted in the figure for comparison, is 3.66 GHz, 

corresponding to a VCO frequency four times higher, that 

is 14.64 GHz. The spectrum on the right side is the one of 

the first ring operating in free running mode, divided by 

two by the second ring. The measured locking range is 

close to 31 % because it was possible to test the divider 

chain only at the operating frequencies of the VCO, 

between 11 and 15 GHz. The measured free running 

frequency is 8.3 GHz, a value slightly inferior to the one 

obtained by simulations. Actually, the divider current 

needed for free-running oscillation was slightly higher 

than the one used in the simulations. This may be due to 

the underestimation of the parasitic capacitances which 

leads to a lower open-loop gain. 

Fig. 6 shows first the output phase noise when the VCO is 

switched off. It is the phase noise of the first ring, reduced 

of – 6 dB by the frequency division. As expected, this 

noise is very high, but it does not impair the overall noise 

performance. When the two dividers are injection-locked 

to the VCO it is the phase noise of this circuit that appears 

at the output. In Fig.6 in fact, we also compare the 

measured phase noise of the VCO with the one at the 

output of the two locked dividers. The frequency division 

by four reduces the noise by 12-dB and confirms that the 

ring phase noise doesn’t affect the output phase noise. In 

Table I are summarized the two dividers’ performances. 


A novel topology of frequency divider has been presented. 

The key feature of the circuit is the reduced slope of the 

phase-frequency plot of one single stage. That allows

Phase Noise [dBc/Hz] 

Figure 5. Output spectrum (left) of the cascade 

of the two dividers driven by the VCO running at 

14.64 GHz (the spectrum is shifted for sake of 

comparison), compared with the spectrum (right) 

of the first ring in free running, divided by two. 

-10 

-20 

-30 

-40 

-50 

-60 

-70 

-80 

free running ring /2 

-90 

-100 

VCO 

-110 

-120 

-130 

-140 

locked ring 

-150 

10k 100k 1M 10M 

achieving a measured locking range about 31% of the 

center frequency, with a reasonable power budget. This 

value is limited by the operating frequency range of the 

VCO (11-15 GHz) used as injection signal. Simulation 

demonstrate even a larger locking range, 6 – 24 GHz, 

which was not possible to experimentally verify given the 

limited tuning range of the signal source. 


Frequency Offset [Hz] 

Figure 6. Comparison between the phase noise of 

the VCO and the phase noise at the output of the 

two dividers. The difference is 12 dB, indicating 

that the dividers do not impair the noise 

performance. 

6. REFERENCES 

[1] B. Razavi, RF Microelectronics, Prentice Hall, Upper 

Saddle River, NJ, USA, 1998, pp. 290-295. 

[2] S. Pellerano, S. Levantino, C. Samori, and A. 

Lacaita, “A 13.5-mW frequency synthesizer with 

dynamic-logic frequency divider,” IEEE Journal of 

Solid-State Circuits, vol. 39, pp. 378-383, Feb. 2004. 

[3] A. Mazzanti, P. Uggetti, and F. Svelto, “Analysis and 

design of injection-locked LC dividers for quadrature 

94 

Table. 1. Measured Dividers Performance 

Power supply 1.2 V 

Bias current – first divider 3 mA 

Bias current – second divider 1.5 mA 

Free running frequency – first divider. 

Free running frequency – second divider 

8.3 GHz 

5.5 GHz 

Input frequency range 11 – 15 GHz 

generation,” in IEEE Journal of Solid-State Circuits, 

vol. 39, pp. 1425-1433, Sept. 2004. 

[4] J. Lee, and B. Razavi, “A 40-GHz frequency divider 

in 0.18 µm CMOS technology,” in IEEE Journal of 

Solid-State Circuits, vol. 39, pp. 594-601, April 2004. 

[5] R. Dehgahani, and S. M. Atarodi, “A low power 

wideband 2.6 GHz CMOS injection-locked ring 

oscillator prescaler,” in Proc. RFIC Symposium, pp. 

659-662, Philadelphia, PA, 8-10 June 2003. 

[6] P. Kinget, R. Melville, D.Long and V. Gopinathan, 

“An injection-locking scheme for precision 

quadrature generation,” IEEE Journal of Solid-State 

Circuits, vol. 37, pp. 845-851, July 2002. 

[7] R. Adler, “A study of locking phenomena in 

oscillators,” Proc. IEEE, vol. 61, pp. 1380-1385, Oct. 

1973.

A 4.2 GHz CMOS Quadrature VCO using Injection 

Locking for WLAN 802.11a 


Michael Nielsen, Torben Larsen 

RISC Division, Aalborg University, Denmark, email: {mn,tl}@kom.aau.dk 

Abstract— A 4.2 GHz 0.24-µm CMOS VCO for a WLAN 

802.11a image reject transceiver is demonstrated. The VCO 

provides quadrature output through injection locking of two 

LC-oscillators. Because the injection locking has an impact on 

the oscillation frequency and Q-factor, an quasi linear model 

is used to analyze this. Furthermore, as this quadrature VCO 

is prone to imperfections, an analysis of the static phase error 

is presented. The phase error is measured to 2.6 − 3.1 ◦ which 

can be traced back to the coupling from the inductors to the 

DC-supply connection. The phase noise is at most −109 dBc/Hz 

@ 1 MHz over the entire tuning range from 3.95 − 4.55 GHz 

while the power consumption is 21 mW. 


For modern low cost wireless systems such as WLAN 

802.11a a high level of integration and low cost is a 

significant criteria for the transceiver architecture. The most 

obvious candidates are the direct conversion transceiver 

(DCT) and the image reject transceiver (IRT), both requiring 

local oscillator signals in quadrature. 

In an IRT the frequency planning can be done such that 

the second local oscillator signal is derived from the first 

in a divide by four circuit [1]. For WLAN 802.11a this 

means that the first local oscillator should cover a frequency 

range from 4.12 − 4.28 GHz if UNII bands 1 and 2 are 

supported [1]. While the quadrature from the second LO 

can be generated in the divide by four circuit, the first LO 

still needs quadrature form. Traditionally this quadrature 

generation has been done by RC-polyphase filter or divide 

by 2 circuits [2], [3]. However, each method has its own 

advantages and disadvantages. 

An attractive approach to produce LO signals in quadrature 

is to injection lock two oscillators by placing coupling 

transistors in series with the cross-coupled negative-R transistors 

(see Fig. 1) as proposed by [2], where the output 

signals in the ideal case are in perfect quadrature. Other 

configurations do exist [4]. However, in [4] it was found that 

the phase error of this topology is least prone to mismatch. 

Mcpl 

Msw 

Vcc 

Vcc 

I+ I- Q+ Q- 

VBias 

Q+ Q- I- I+ 

Mbias 

VBias 

Fig. 1. Topology with injection locked oscillator [2]. 

95 

In [2] the oscillator has been implemented with an 

oscillation frequency just below 2 GHz, whereas in this 

work the topology is adapted for a 4.2 GHz oscillator. 

Because the dimensions relative to the frequency are larger 

in this case, the perfect quadrature is more prone to layout 

imperfections and consequently a phase error analysis is 

performed to reveal the critical layout aspects. 

The paper is organized as follows. First, a quasi linear 

model is proposed for the analysis of the oscillator. Secondly, 

the impact of the injection locking on the oscillation 

frequency and oscillator Q-factor is investigated. Then, a 

phase error analysis based on the quasi linear model shows 

the critical aspects of the layout. Finally, the results of the 

fabricated oscillator is presented and a conclusion is given. 

II. QUASI LINEAR MODEL 

In Fig. 2 a quasi linear model of the oscillator is depicted. 

In this model it is assumed that the current running in 

the positive branch of the I oscillator is solely depending 

on the voltage of nodes In and Qp and similar for the 

three other branches. Although the current in the series 

coupled transistors also depends on the voltage of the upper 

drain this is incorporated in the model as vIp = −vIn. The 

nonlinearities of the oscillator are modeled in the transconductances 

Gs,x and Gc,x and these adjust themselves to 

ensure that Barkhausens criteria for oscillation is fulfilled. 

Gs,x represents the negative-R trans-conductance, and Gc,x 

represents the coupling between the two oscillators. Several 

things effect Gc,x and Gs,x such as the size, bias-point and 

periods of the transistors being in linear/saturation region. 

Regrettably, Gc,x and Gs,x are not directly related to these 

parameters and have to be simulated. 

HQ = vQ 

Inphase 

vI Quadrature 

Oscillator HI = Oscillator 

vI 

vQ 

vIp 

LI 

CI 

RI 

Gs,IvIn + Gc,IvQp 

vIn 

Gs,IvIp + Gc,IvQn 

vQp 

LQ 

CQ 

RQ 

Gs,QvQn + Gc,QvIn 

vQn 

Gs,QvQp + Gc,QvIp 

Fig. 2. Linear model of the oscillator. R represents the loss in the 

LC-tanks due to the finite Q-factor. A similar model is presented 

in [2] 

A. Quadrature Oscillation 

The transfer functions from vQ to vI and visa versa can 

be found using simple circuit calculations to be:

and 

HI (ω) = 

HQ (ω) = 

vI (ω) 

vQ (ω) = 

vQ (ω) 

vI (ω) = 


−jωL � � Gc 

2 

1 − ω2LC + jωL � 1 

R 

jωL � � Gc 

2 

1 − ω2LC + jωL � 1 

R 

� (1) 

Gs 

− 2 

� (2) 

Gs 

− 2 

where it is assumed that the matching between the components 

is perfect (hence the subscripts are dropped). 

Barkhausens criteria for oscillation states that 

HI (ω) · HQ (ω) = 

ω 2 L 2 G2 c 

4 

� 1 − ω 2 LC + jωL � 1 

R 

�� Gs 2 =1 

− 2 

(3) 

The quadrature nature of the oscillator can be realized 

by analyzing Eqs. (1)–(3). Because the numerator of 

HI (ω) · HQ (ω) has no imaginary part, the denominator 

must also be purely real. Consequently, Gs = 2 

R 

. This 

implies that the denominator of HI (ω) (or HQ (ω)) is 

real, which in turn implies that the phase between vI (ω) 

and vQ (ω) must be ±90 ◦ depending on the sign of the 

denominator. Hence the quadrature is shown. 

B. Oscillation Frequency 

Solving Eq. (3) with respect to the frequency gives 

� 

, (4) 

ωosc = ± 

� � 

∆ω ± ∆ω2 + ω2 0 

where ω0 is the resonance frequency of the LC-tank and 

∆ω = Gc 

, (5) 

4C 

which may be interpreted as an offset frequency between 

the oscillation frequency of the oscillator and the resonance 

frequency of the LC-tank. As ω0 ≫ ∆ω, Eq. (4) can be 

reduced to 

ωOsc = ω0 ± ∆ω, (6) 

where the ± outside the brackets in Eq. (4) represents 

the negative frequency and is consequently left out here. 

Although Eq. (6) has two mathematical solutions, only 

one of them is physically valid. Both measurements and 

simulations show that the oscillation frequency is lower than 

the resonance frequency. Since the parasitic capacitance 

can be difficult to evaluate exact this can not be measured 

directly. However, by assuming that Gc increases with an 

increased bias current (this tendency has been verified in 

simulations) it can be seen that the offset is negative because 

the oscillation frequency drops with increased bias current. 

Note that [2] finds that the offset is positive. Several factors 

can explain this apparent contradiction: (i) The oscillation 

frequency of this oscillator is more than twice of [2]. (ii) 

The L/C-ratio is in this case 4 times that of [2]. (iii) The 

sizes of the transistors Mcpl and Msw are in this case nearly 

the same (refer to Fig. 3), whereas in [2] Mcpl is 5 times 

96 

the size of Msw. (iv) [2] uses a 0.35 µm process, whereas 

this is a 0.24 µm. 

C. Q-factor of Oscillator 

The Q-factor of an oscillator can be found as [5] 

Qosc = ω 

� 

2 

dφ 

+ 

2 dω 

dA 

� 

2� 

� 

� , (7) 

dω 

where dφ 

dω 

and dA 

dω 

� ω=ωosc 

are the derivatives of the phase and 

amplitude of the open loop transfer function of the oscillator. 

In a traditional negative-gm oscillator the Q-factor of 

the oscillator is the same as the Q-factor of the LC-tank. 

A high Q-factor reduces the phase noise and power loss 

(and thereby power consumption). For the injection locked 

oscillator the Q-factor of the oscillator is not the same 

as the LC-tank. Combining Eqs. (3), (6), and (7) allows 

the Q-factor to be calculated. However, the expression gets 

complicated and brings no overview. Assisted by a computer 

algebra system, a few conclusions can be made (note that 

the phase derivative of Eq. (3) is zero because Gs cancels 

out the imaginary part): 

• If it assumed that the parallel resistor in Fig. 2 scales 

linearly with the inductor size, Gs must scale inversely 

with L. If it furthermore is assumed that Gc scales 

linearly with Gs it can be shown that the Q-factor of 

the oscillator is fixed for reasonable choices of the L/Cratio. 

It should be noted here, that the first assumption 

is a logical consequence of the loss being primarily 

dominated by the inductor and that the inductor has 

a fixed Q-factor. Simulations have verified that the 

second assumption is very close to reality. 

• The Q-factor decreases with an increase of Gc. Put 

in other words: the lower coupling between the two 

oscillators, the better. 

The L/C-ratio should like the traditional negative-gm 

oscillator be maximized because the power loss in the LCtank 

increases with a small inductor and the oscillator needs 

to compensate for the increased loss [6]. Consequently, 

the L/C-ratio should be maximized to minimize the power 

consumption. 

D. Phase Error Analysis 

There are three sources to a static phase error: (i) 

Component- or bias mismatch, (ii) parasitic capacitative 

coupling, and (iii) mutual inductance between the inductors. 

In general the matching performance of CMOS is sufficient 

to ensure a low phase error if the critical components 

are placed close to each other. Because the mismatch of 

the active devices (transistors and varactors) is larger, these 

should be given higher priority in this matter. 

The bias matching is primarily the resistive loss in the 

supply voltage to the center-tapped inductors. A resistive 

loss will cause a minor voltage drop across the supply 

connection, if this loss is not matched one of the oscillators 

will have a lower supply voltage and consequently a phase 

error will be introduced. Simulations indicate that a 4 Ω

mismatch of the supply connection causes 1 ◦ phase error. 

However, careful layout can prevent such a mismatch. 

Somewhat intuitive, the parasitic capacitative coupling is 

not a problem if the coupling is the same for all the nodes 

(Ip, In, Qp and Qn). A good match of the parasitic coupling 

can be met by a highly symmetric layout and some hands-on 

area calculations of the interconnections. 

The last contributor to phase error is the mutual inductance 

between the inductors. If the mutual inductance 

between the two inductors is characterized by the coupling 

constant (k) the open loop transfer function H (ω) = 

HI (ω]·HQ (ω) can once again be found by straight forward 

circuit calculations to: 



� Gc,I 

2 

� 

−jωLI ± jk 

HI (ω) = 

1 − ω2LICI + jωLI 

� Gc,Q 

2 

� 

jωLQ ∓ jk 

HQ (ω) = 

1 − ω2LQCQ + jωLQ 

� 

1 

− RI Gs,I 2 

� 

1 

− RQ Gs,Q 2 

� (8) 

� (9) 

where the sign of k depends on the physical layout — 

note that the sign of k in Eqs. (8) and (9) is opposite. It 

is worth noting that because the numerators are no longer 

pure imaginary, the denominators need to have an imaginary 

part for Barkhausens criteria of oscillation to be fulfilled. 

As a consequence, Gs,I and Gs,Q must change, and since it 

is reasonable to assume that Gs and Gc are correlated (the 

origin of the effect is the same transistors) Gc,I and Gc,Q also 

change. It is impossible to predict how these will change 

from the quasi linear model, so simulations are required 

here. Simulations show that the trans-conductances change 

constructively — that is, the phase error is larger than what 

can be calculated from the numerator of Eq. (8) or Eq. (9). 

There are two methods to ensure a low mutual coupling. Either 

the inductors must be placed with sufficiently distance 

in between, or four inductors can be used as proposed in 

[7]. ADS Momentum simulations indicate that placing the 

inductors as shown in Fig. 3 reduces the phase error to a 

value below 0.1 ◦ . 

In conclusion, the static phase error is down to proper 

layout with the following guidelines: 

• Transistors and varactors should be placed close to 

each other to avoid mismatch. 

• The bias supply connection should be resistive 

matched. 

• A highly symmetric layout is preferable to match the 

parasitic capacitance. The interconnections that can not 

be routed symmetric should be given extra attention to 

ensure a matching capacitance. 

• Finally the inductors should be placed with sufficient 

distance between them to avoid mutual inductance. 

III. RESULTS 

The oscillator (depicted in Fig. 3) is fabricated in a 0.24- 

µm CMOS process with 2 µm top layer metal. 

97 

GND 

Vcc 

Vbias 

Vvar 

Vvar 

Ip 

DC-Supply Connection 

In 

Varactor Buffer Varactor 

Oscillator Core 

LI=2.4 nH 

Buffer 

LQ=2.4 nH 

Qn Qp 

Mcp = 0.24x90 µm 

Msw = 0.24x70 µm 

Mbias = 1x70 µm 

Fig. 3. Layout of oscillator. The size of the transistors are chosen 

small to reduce the parasitic capacitance. NMOS inversion mode 

varactors are used to tune the frequency. 

To increase the Q-factor of the inductors, the strip-width 

is made thinner in the inner turn and thicker in the outer 

most turn. The arguments for doing so are as follows. The 

inductance is proportional to the average diameter, whereas 

most of the loss is caused by the series resistance in the 

windings. By decreasing the width of the inner turn and 

increasing the outer turn the average diameter is increased 

with the series loss more or less unchanged. Therefore, 

the Q-factor is increased. The parasitic capacitance of the 

inner turn is reduced in turn of an increased outer turn 

capacitance. However, since the outer turn capacitance is 

in common mode this is not a problem. Momentum simulations 

indicates an increase of the Q-factor of app. 10 % 

by using variable strip-width compared to using fixed stripwidth. 

Measurements show that the Q-factor of the inductor 

is app. 12 at 4 GHz. 

The static phase error is measured on-chip using a 

network analyzer with one of the outputs of the oscillator 

(Ip) connected to the RF-input of the analyzer. Thereby 

the analyzer locks to Ip and the relationship can be found 

between Ip and Qp by connecting Qp to port 2 of the 

network analyzer and reading out S21. The measurement 

setup is illustrated in Figure 4. By swapping the inputs and 

re-measuring, any cable mismatch is calibrated out and the 

phase and amplitude difference between the two signals can 

be found as: 

�� 

S21,b 

θ = angle 

(10) 


�� 

G = abs 

S21,a 

S21,b 

S21,a 

� 

(11) 

where θ typically is of most interest. In these calculations 

it is assumed that the phase between p- and n-branch of 

each oscillator is 180 ◦ (hence perfect symmetry around the 

inductor). The phase error is measured in 4 chips to 2.6 ◦ – 

3.1 ◦ with a maximum spread of 0.3 ◦ pr. chip. Histograms 

of the measurements are shown in Fig. 5. The rather large 

phase error can be traced back to the coupling from the 

inductors to the DC-supply connection to inductor LQ. 

This connection was not included in the initial Momentum 

simulation and therefore not discovered before the layout. 

Post simulations have shown that this coupling has a large 

effect on both the phase error between the oscillators and 

the signal symmetry around the center-tapped inductors.

8510C 

S21a = 

Cable 1 RF Port 2 

Cable 2 

a1 = I+ 

b2 = αQ+ 

b2 αQ+ 

= a1 I+ 

Probe 1 

GND 

I- 

I+ 


Measurement A 

Vcc 

Vbias 

Vvar 

8510C 

S21b = 

Cable 1 RF Port 2 

Cable 2 

a1 = Q+ 

b2 = αI+ 

b2 αI+ = a1 Q+ 

Vvar 

Q- 

Q+ 

Vbias 

Q+ 

Q- 

Measurement B 

Vcc 

I+ 

I- 

GND 

Probe 2 

Probe 1 Probe 2 

Fig. 4. Measurement setup. The usual RF-source of the HP 8510C 

test set is disconnected from the RF-input of the network analyzer 

and one of the outputs of the oscillator (DUT) is connected instead. 

In measurement B the chip and its bias supplies are rotated 180 

deg. 

The coupling can be reduced by wiring the DC-supply 

connection on both sides of the inductors or by using an 

approach to layout with centered DC-supply connections. 

In Fig. 6 the measured phase noise and oscillation frequency 

are shown along with the simulated results. The measured 

frequency is slightly higher than simulated, which can be 

explained by the process variation of CMOS. The higher 

phase noise in the transition from low to high frequency is 

caused by the 1/f noise AM-PM conversion due to the steep 

tuning curve of the varactors (for more information refer 

to [8]). Because this mechanism to a high degree depends 

on the amplitude of the signal, a discrepancy between the 

measured and simulated results can be observed. 

IV. CONCLUSION 

A 4.2 GHz oscillator has been implemented in a 0.24-µm 

CMOS process with a phase noise better than -109 dBc/Hz 

@ 1 MHz over the entire tuning range from 3.95–4.55 

GHz. An analysis of the oscillator with respect to oscillation 

frequency, oscillator Q-factor, and static phase error is given 

based on a quasi linear model. The static phase error is 

measured to be between 2.6 ◦ –3.1 ◦ . This large error can be 

traced back to coupling from the inductors to the DC-supply 

α 

α 

98 

Histogram of θ 

25 

40 

Chip 1 Chip 2 

20 

30 

15 

10 

5 

0 

86.4 

25 

Chip 3 

20 

86.6 86.8 87 87.2 

15 

10 

5 

20 

10 

0 

87 87.2 87.4 87.6 87.8 88 

30 

Chip 4 

25 

0 

87.1 87.2 87.3 87.4 

0 

86.9 87 87.1 87.2 87.3 

Phase Difference, θ [deg] 

Fig. 5. Histograms of the phase error measurement. 

Phase Noise @ 1MHz [dBc/Hz] (RBW/VBW 30 kHz) 

−107.5 

−110 

−112.5 

−115 

−117.5 

POsc=2 dBm 

(differential output) 

PDC=21 mW 

−120 

0 0.5 1 1.5 2 2.5 3 

3.7 

3.5 

Varactor Control Voltage [V] 

Fig. 6. Measured and simulated phase noise and oscillation 

frequency. Solid = measured, Dashed = simulations. The oscillator 

draws 8.3 mA from a 2.5 V voltage supply. 

connection and can be reduced by wiring the connection on 

both sides of the inductors. 

20 

15 

10 

REFERENCES 

[1] M. Zargari, D. K. Su, P. Yue, S. Rabii, D. Weber, B. J. 

Kaczynski, S. S. Mehta, K. Singh, S. Mendis, and B. A. 

Wooley, “A 5-GHz CMOS Transceiver for IEEE 802.11a 

Wireless LAN Systems,” IEEE Journal of Solid-State Circuits, 

pp. 1688–1694, 2002. 

[2] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis 

and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE 

Journals of Solid-State Circuits, pp. 1737–1747, December 

2002. 

[3] B. Razavi, RF Microelectronics. Prentice Hall, 1998. 

[4] X. Wang and P. Andreani, “A 2GHz Low-Phase-Noise CMOS 

Quadrature VCO,” in Proc. IEEE Norchip Conference, 2002, 

pp. 303–308. 

[5] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” 

IEEE Journal of Solid State Circuits, Vol 31., pp. 331–343, 

1996. 

[6] M. Tiebout, “Low-Power Low-Phase-Noise Differentially 

Tuned Quadrature VCO Design in Standard CMOS,” IEEE 

Journal of Solid-State Circuits, pp. 1018–1024, July 2001. 

[7] P. Andreani and X. Wang, “On the Phase-Noise and Phase- 

Error Performances of Multiphase LC CMOS VCOs,” IEEE 

Journal of Solid State Circuits, Vol 39., pp. 1883–1893, 2004. 

[8] S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkink, A. L. 

Lacaita, and V. Boccuzzi, “Frequency Dependence on Bias 

Current in 5 GHz CMOS VCOs: Impact on Tuning Range 

and Flicker Noise Upconversion,” IEEE Journal of Solid State 

Circuits, Vol 37., pp. 1003–1011, 2002. 

5 

4.7 

4.5 

4.3 

4.1 

3.9 

Oscillation Frequency [GHz]


A VERY LOW POWER CONSUMING 5 GHZ 

CMOS VCO CORE WITH 800 MHZ FREQUENCY 

TUNING RANGE 

George von Büren, Frank Ellinger, Heinz Jäckel 

Swiss Federal Institute of Technology (ETH) Zurich, Electronics Laboratory, 

Gloriastrasse 35, CH-8092 Zurich, Switzerland 

E-mail: george.vonbueren@ife.ee.ethz.ch 

ABSTRACT 

A low power consuming VCO core at C-band frequencies 

is presented. With a supply voltage of 2.5 V and a VCO 

core current consumption of only 1.5 mA a phase noise 

between -98 to -104 dBc/Hz is measured. Varying the 

tuning voltage from 1 V to 2.5 V yields a tuning range of 

800 MHz with a center frequency of 4.6 GHz. The fully 

integrated circuit is fabricated on a commercial 0.25 µm 

BiCMOS process. 


High-speed phase-locked loops and clock/data recovery 

circuits require high performance VCOs. The VCO should 

be able to drive several sub-blocks like prescaler, phase 

detector and demultiplexer. Furthermore, the jitter 

generation in the VCO should be minimized. As the VCO 

phase noise is high-pass filtered in PLLs, the phase noise 

spectral power components with a frequency offset from 

the carrier higher than the PLL loop bandwidth should be 

as low as possible. 

2.1 Topology 

2. DESIGN 

The phase noise [1] of a LC VCO expressed in dBc/Hz at 

a frequency-offset ∆f can be approximated by 

⎡ 2 

2kT ⎛ f0 

⎞ 

⎤ 

L{ ∆ f} = 10 log ⎢F⎜ ⎟ ⎥ 

⎢ PSig ⎝2Q∆f ⎠ ⎥ 

⎣ ⎦ 

where F is the noise factor of the active circuit part, k is 

the Boltzmann constant, T the absolute temperature, PSig 

the oscillator output power, f 0 the oscillation frequency, 

and Q the loaded oscillator tank quality factor. The major 

parameters to optimize are the quality factor of the tank 

and the oscillator amplitude. The goal of this design was 

to reduce the power consumption in the VCO core and to 

achieve a wide tuning range while still having an 

acceptable phase noise performance. For the realization, a 

NMOS-PMOS cross-coupled LC VCO topology (Fig. 1) 

was chosen because it reuses current resulting in higher 

oscillation amplitude than a NMOS-only structure. 

Doubling the oscillation amplitude means lowering the 

99 

phase noise by maximum of -6 dB. For a given bias 

current, the negative conductance g ative of a NMOS-PMOS 

structure is -g mn/2-g mp/2 where as the negative 

conductance of a NMOS-only structure is only -g mn/2 with 

g mn and g mp being the transconductances of a NMOS and 

PMOS transistor. A higher transconductance for a given 

bias current results in faster switching of the crosscoupled 

pair. Sizing the PMOS and NMOS transistors that 

g mn≈g mp can improve the rise and fall time symmetry of 

the signals V x, V y having a frequency of f osc and V p 

alternating with 2·f osc. A better signal symmetry 

minimizes the low frequency 1/f-noise up-conversion of 

the tail current noise into sideband frequency components 

around multiples of 2·f osc and results in a lower 1/f 3 noise 

corner frequency [2]. A disadvantage of the additional 

PMOS transistors is the increase of the total parasitic 

capacitance of the tank resulting in a somewhat lower 

tuning range. 

Figure 1. Schematic of the NMOS-PMOS VCO. 

To drive all sub-blocks of a PLL or CDR with the system 

clock a VCO buffer is used. The clock buffer tree 

incorporates two differential amplifier stages. In the 

presented design a third stage is added to provide a 

tapered output buffer for an adequate voltage swing at the 

50 Ω load. The first stage isolates the VCO core from the 

main clock driver and should have a minimal input 

capacitance. The width of transistor should be therefore as 

small as possible but large enough to be able to drive the 

next stage with an equal rise and fall time.

2.2 Tank amplitude 

Fig. 2 shows the model for a parallel LC oscillator in 

steady state, where -g active represents the negative 

conductance of the active devices that compensates the 

losses in the tank represented by g tank. 

Figure 2. Steady-state parallel oscillator model. 

At the resonance frequency, the admittances of the L and 

the C cancel each other. Harmonics of the input current 

Iosc are strongly attenuated, leaving the fundamental of Iosc to generate a differential voltage swing of amplitude 

4/π·Iosc·(gtank) -1 across the tank assuming a rectangular 

current waveform. At high frequencies, the current 

waveform may be approximated more closely by a 

sinusoid. In this case the tank amplitude can be better 

approximated as Vtank≈Iosc·(gtank) -1 . This mode of operation 

is referred as the current-limited regime [2]. 

If Iosc is steadily increased to maximize the tank voltage, 

at a certain current Iosc, the tank voltage saturates at Vlimit, which is close to the supply voltage to the first order. This 

situation is called voltage-limited regime. What we want 

to avoid is to drive the tail current source M5 into triode 

region. Therefore, the goal is to work in the currentlimited 

regime very close to the voltage-limited regime to 

have large tank amplitude to lower the phase noise. The 

tank voltage amplitude is in the range of 

-1 -1 

I osc ⋅(g tank,max ) ≤V tank ≤ I osc ⋅ (g tank,min ) < Vdd-Vdsat5 where Iosc·(gtank,max) -1 signifies the worst-case scenario 

when the varactor capacitance and the tank losses are 

maximal. The lower the losses in the resonator the smaller 

oscillator core current Iosc that fulfils the oscillation startup 

condition can be chosen. The dimension of the tail 

current transistor M5 are: L=0.5µm, W=76.8µm. Vdsat5 is 

0.4 V with a drain-source current of Iosc=1.5 mA. The 

simulated differential tank amplitude varies between 1.4 V 

(gtank,min: 0.7 V

Small signal simulation taking the wiring parasitics into 

account predicted an open-loop gain between 2 and 3 

when varying with the tuning voltage. 

2.4 Resonator and tuning range 

An oscillator can be represented as a tuneable RLC-tank 

with a variable capacitance as tuning element. To have a 

sharp and high tank amplitude and a steep phase roll off in 

the phase domain the L/C ratio should be as high as 

possible and the losses in the resonator should be 

minimized [3]. The octagonal on-chip spiral inductor 

having an inductance of 1.12 nH is a deep-trench inductor 

with an outer dimension of 160 µm, a width of 10 µm, a 

spacing of 5 µm and 2.5 turns. The deep-trench inductor 

uses deep-trench mazes with a high resistance under the 

inductor to reduce the parasitic capacitance. The 

simulated quality factor is Q=14 at 5 GHz, the simulated 

peak quality factor is at 5.68 GHz and the simulated selfresonance 

frequency is around 30 GHz. 

As a varactor a base-collector pn-junction diode used in 

reverse biased mode, having a tuneability of 2:1 and a 

quality factor ranging from 60 to 120 at 5 GHz, is chosen. 

The highest Q can be achieved with the cathode connected 

to ac ground due to the subcollector to substrate 

capacitance, as can be seen in Fig 5. The design of the 

anode width requires a trade-off between higher 

capacitance ratio and lower diode series resistance. A 

square anode will maximize the capacitance ratio. A long 

and narrow diode provides lower series resistance, which 

is more important to have low tank losses. The dimension 

of the used varactor having 26 cathode stripes is 

L=10.28 µm and W=2 µm to reduce the losses in the tank. 

Figure 5. Base-collector pn-junction diode. 

The frequency of the tuning range of the circuit is given 

by: 

1 1 

∆ω = − 

L tan k ⋅ (Cv,min+ C fix ) L tan k ⋅ (Cv,max+ C fix ) 

where Ltank=1.12 nH, Cfix=CPMOS+CNMOS+Cbuf+Cind+Cwiring and the simulated Cv is illustrated in Fig. 6. The lower the 

fixed capacitance Cfix the higher the tuning range. The 

total fixed capacitance Cfix is around 350 fF over the 

whole tuning range. The small signal capacitances are: 

CPMOS=66 fF; CNMOS=21 fF; Cbuf =10 fF; Cind≈225 fF; 

Cwiring≈120 fF. The quality factor of the varactor depicted 

in Fig. 6 decreases with lower tuning voltage Vc and thus 

the loaded quality factor of the tank as well which results 

in a lower phase noise performance. 


101 

Cv [fF] Q 

1100 

180 

900 

700 

500 

300 

5 4.2 3.4 2.6 1.8 1 

Tuning Voltage Vc [V] 

140 

100 

Figure 6. Variable capacitance Cv and its quality factor Q 

simulated at 5 GHz versus the tuning voltage V c. 

2.5 Implementation 

The fully integrated circuit is implemented as an entirely 

symmetric layout in a commercial 0.25 µm BiCMOS 

technology [4]. The overall chip size is 1 mm x 0.7 mm 

but the effective chip size including two spirals is only 

0.5 mm x 0.4 mm. 

Figure 7. Chip photo. 

3. MEASUREMENTS 

All measurements were preformed on-wafer. Fig. 8 shows 

the measured spectrum at a tuning voltage of 2.5 V. With 

a resolution bandwidth of 100 kHz, the phase noise at a 

frequency offset of 1 MHz from the carrier frequency of 

5.011 GHz is (-54-50) dBc/Hz= -104 dBc/Hz. The 

measured single ended output power over the complete 

tuning range taking into account the losses of the spectrum 

analyzer (3.5 dB), the coaxial cable (0.75 dB) and the 

probe (0.5 dB) results in a output power of -1.5 dBm 

corresponding to a peak-to-peak amplitude of 530 mVpp 

at 50 Ω. The simulated transient output peak-to-peak 

amplitude over the whole tuning range is higher than 

0.5 V. The oscillator core draws only 1.5 mA from a 

supply voltage of 2.5 V. The current consumption of the 

whole chip including output buffer is 38 mA while the last 

differential stage needs 27 mA. 

60 

20

Power [dBm] 

-20 

-40 

-60 

5.006 5.01 5.014 

Frequency [GHz] 

Figure 8. Measured output spectrum at 5.01 GHz. 

Resolution bandwidth: 100 kHz. 

Fig. 9 shows the simulated (dotted), measured oscillation 

frequency and the measured phase noise at a frequency 

offset of 1 MHz from the carrier versus the tuning voltage. 

The measured tuning range is 800 MHz by varying the 

tuning voltage from 1 V to 2.5 V. The tuning range 

expressed is 17.4 %. 

Frequency [GHz] Phase Noise [dBc/Hz] 

5.1 

-95 

4.9 

4.7 

4.5 

4.3 

4.1 

sim 

meas 

1 1.5 2 2.5 

Tuning Voltage Vc [V] 


-97 

-99 

-101 

-103 

-105 

Figure 9. Simulated (dotted), measured oscillation 

frequency and the measured phase noise at a 

frequency offset of 1 MHz versus tuning voltage. 

It is possible to increase the tuning voltage V c further. 

With a tuning voltage of V c=5 V the measured oscillation 

frequency is 5.47 GHz and the phase noise at a frequency 

offset of 1 MHz is -110 dBc/Hz. 

Ref. Iosc 

[mA] 

Pcore 

[mW] 

54 dB 

meas 

PN (1 MHz) 

[dBc/Hz] 

Tuning 

range 

[5] 2 3.8 -101 7.2 % 

[6] 10 20 -100 8 % 

[7] 5.5 14 -114 18 % 

This work 1.5 3.8 -101 17 % 

Table. 1. Comparison of 5 GHz CMOS crosscoupled 

VCO implemented in 0.25µm CMOS. 

102 

Table 1 compares the figure of merits of state-of-the-art 

cross-coupled VCOs operating at 5 GHz and implemented 

in 0.25µm CMOS processes. 

4. CONCLUSION 

The presented NMOS-PMOS cross-coupled 5 GHz 

LC VCO core consumes only 3.75 mW. The VCO core 

current was minimized by optimizing the resonator losses 

and the chosen topology. Despite the disadvantage of this 

topology, the measured tuning range is 17 %. If the tuning 

voltage is increased higher than the supply voltage the 

tuning range reaches 1.3 GHz. The phase noise at a 

frequency offset of 1 MHz over the whole tuning range is 

-101 dBc/Hz ±3 dB. 

5. ACKNOWLEGEMENTS 

For funding and access to the BiCMOS technology, we 

would like to thank IBM Research Laboratory Zurich. In 

this context the authors would like to acknowledge 

Dr. M. Schmatz, IBM Research, Zurich, Switzerland, for 

his support and engagement for the IBM/ETH center for 

advanced silicon electronics (CASE). Furthermore, the 

authors are grateful to H. Benedickter for providing 

measurement equipment and support and to D. Barras for 

organizing the waferrun. 

6. REFERENCES 

[1] Leeson D. B., A simple model of feedback oscillator 

noise spectrum, Proc. IEEE, Dec. 1966. 

[2] Hajimiri A., Lee T. H., Design issues in CMOS 

differential LC oscillators, IEEE Journal of Solid- 

State Circuits, vol. 34, n0. 5, pp. 717-724, May 1999. 

[3] Tiebout M., Low-power low-phase-noise 

differentially tuned quadrature VCO design in 

standard CMOS, IEEE Journal of Solid-State 

Circuits, vol. 36, n0. 7, pp. 1018-1024, July 2001. 

[4] St. Onge S. A. et al., A 0.24 µm SiGe BiCMOS 

mixed-signal RF production technology featuring a 

47 GHz f t HBT and 0.18 µm L eff CMOS, 

Bipolar/BiCMOS Circuits and Technology Meeting 

1999, pp. 117 - 120, Sept. 1999. 

[5] Rategh, H. R. et al., A CMOS frequency synthesizer 

with an injection-locked frequency divider for a 

5-GHz wireless LAN receiver, IEEE Journal of 

Solid-State Circuits, vol. 35, n0. 5, pp. 780 – 787, 

May 2000 

[6] Yamagishi, A. et al., A low-voltage 6 GHz-band 

CMOS monolithic LC-tank VCO using a tuningrange 

switching technique, International Microwave 

Symposium Digest, 2000 IEEE MTT-S, vol. 2, 

pp. 735 - 738, June 2000. 

[7] Samori, C. et al., A -94 dBc/Hz@100 kHz, fullyintegrated, 

5-GHz, CMOS VCO with 18% tuning 

range for Bluetooth applications, IEEE Custom 

Integrated Circuits Conference 2001, pp. 201 - 204, 

May 2001.


Design and Optimization of CMOS Prescaler 

Yu Lei, Student Member IEEE, Adil Koukab, 

and Michel Declercq, Fellow IEEE 

Ecole Polytechnique Fédérale de Lausanne (EPFL), Laboratoire d’Electronique Générale, 

Batiment ELB, Station 11, CH-1015 Lausanne, Switzerland 

E-mail: yu.lei@epfl.ch 

Abstract: 

UWB prescaler operating from 1GHz to 25 GHZ 

while drawing about 3.5mA from 1.8V power 

supply has been designed in 0.18 CMOS process. 

The prescaler features new balanced dynamic load 

technique and an asymmetrical latch structure. The 

speed enhancement mainly comes from the 

asymmetrical setting of the D-latch cell, while 

balanced dynamic load significantly widens the 

frequency range and at the same time reduces power 

consumption. The factors and tradeoffs that govern 

the circuit performances are addressed to optimize 

the design. 

I. Introduction: 

High speed prescaler is one of the key components 

in frequency synthesizers. It works at the highest 

frequency of the system and generally consumes a 

significant portion of the total power. The main 

function of the prescaler is to divide de frequency by 

two and to generate quadratic I and Q signals. Dflipflop 

architectures using CML is the most popular 

topology for this circuit [1-6]. Conventional CML 

circuits are preferred due to their high speed, good 

noise immunity and relatively big working 

frequency range. But in high frequency their power 

consumption increase significantly. In this paper, a 

new prescaler topology with a modified dynamic 

load is proposed. This architecture is particularly 

suitable for a high speed, ultra wide band (UWB) 

and low power application. Design parameters 

governing the prescalers operations are investigated 

and analysed and a methodology to optimize their 

performances proposed. 

II. Circuit Design 

A conventional CML prescaler uses constant biased 

PMOS transistor as load is shown in Fig. 1. 

Generally the prescaler comprises two differential 

current mode D-latches mutually coupled in a 

103 

negative feedback. As illustrated in Fig.1, Each Dlatch 

consists of two differential pairs, the transistors 

M7, M8 compose the logic pair which tracking the 

input signal and M5 and M6 compose the latch pair. 

The track and latch modes are determined by the 

clock signals at the inputs of the transistors M9 and 

M10. When the signal CLK is "HIGH", the circuit 

operates in the tracking mode. Most of the current 

provided by the load flows through the logic pair, 

M7 and M8, thereby allowing VOUT (Q, QN) to 

track Vin (D, DN). In the latch-mode, the signal CLK 

is held low and the latch pair is enabled to store the 

logic state at the output. At the same time the 

tracking stage is disabled. M2 and M3 (M12, M13) 

are PMOS transistors which are constant biased as 

the load shared by logic pair and latch pair [1, 4, 7]. 

Resistors were also used as loads in some other 

designs [5, 6]. Based on the conventional designs, 

two major modifications will be introduced in the 

Fig. 1 Conventional Prescaler with constant biased load 

prescaler architecture to improve the operation speed 

and enhance the frequency operating range. The first 

technique consists of using an asymmetrical latch 

design. The second technique is to implement a 

complementary CLK driven load (M1-M4 in fig1). 

This technique will be called balanced dynamic load 

(BDL).

2.1 Asymmetrical latch design 


Fig. 2 High Speed BDL Prescaler 

Traditionally, prescaler was designed in a 

symmetrical topology; same transistor size was used 

in the latch and the logic pairs [4]. However, this is 

not an optimized solution. In fact, the logic pair 

should be designed with large transistors (6-10um 

gate width) in order to enhance its gain. At the same 

time its capacitance load and so the latch transistors 

size should be as small as possible to speed up the 

changing of state. This is why the equally sized 

latch-logic pairs have a limited frequency operating 

range. 

To increase the maximum operating frequency we 

should shrink the transistors of the latch pair. 

However, there is a shrinking limit since the latch 

pair also needs some gain to drive the second Dlatch 

and accelerate its changing state (latching 

mode). On the other hand, the lower limit of the 

operating frequency range increase significantly 

when we size down the latch pair. To deal with this 

problem, the BDL technique will be introduced. 

This method will be discussed in next section. For 

the current process the optimum ratio between logic 

and latch transistors sizes was found to be around 3 

to 1. Thanks to this optimization procedure 30% 

speed enhancement is achieved compared to an 

104 

implementation employing an equally sized 

differential pair and using the same power budget. 

2.2 Balanced dynamic load technique 

The load topology has a very important impact on 

the prescaler performances. Many configurations 

have been presented in the open literature based on 

passive loads [5, 6] and constant biased active loads 

[1, 4, 7]. Recently, a dynamic load technique was 

introduced [2, 3] with a significant success. The aim 

of the technique is to reduce the load and so the RC 

time in the tracking mode, and increase the load in 

the latching mode for higher gain to accelerate the 

positive feedback setup process. For the later, this 

also implies that for the same gain one can reduce 

the latch size thus reduce the current needed for 

charge the capacitance. To achieve this, 

complementary clocks were used to drive the active 

loads of the logic and the latch pairs. A significant 

improvement in the power consumption at high 

frequency was reported [3]. The sources of latch pair 

transistors of this topology have been directly 

grounded and the maximum reported frequency was 

18 GHz. This frequency operating limit was also 

verified from our simulations. To enhance the 

frequency range of this structure, we have 

introduced the transistors M9, M19 to drive the latch 

pair (MDL in Fig.2). This modification increases the 

highest operating frequency by the ratio of about 

30%. 

The effect of adding M9/M19 is analyzed here. At 

first, inserting tail transistors M9/M19 reduce the 

internal signal swing in node D/D*/Q/Q*, thus 

reduce the time of changing state. Secondly, the 

clock-driven latch pair has less capacitive load in the 

tracking mode compare to grounded latch pair in DL 

prescaler of fig.2, thus improve the operation speed. 

The side effect of inserting M9, M19 is that in lower 

frequency range (

III. Simulation result and discussion 

Transistors’ dimension: 

Transistor Gate dimension 

M7/M8 (logic) 6um 

M5/M6(latch) 3um 

M9 (latch tail current) 16um 

M10 (logic tail current) 8um 

M2/M3(load) 8um 

M1/M4(load) 3um 


Table .1 Transistors’ dimension of 

designed BDL prescaler 

Figure 2 illustrates all the circuit topology used in 

simulation. The dimension of all the transistors used 

in the BDL prescaler is shown in table 1. 

Figure 3 shows that both the classical DL and BDL 

prescaler works correctly with 18GHz input. When 

the input is 25GHz, the BDL prescaler still divides 

correctly but the classical DL fails to work. In our 

simulation, 18GHz is the upper limit in of divide 

range of DL prescaler. 

Fig.3 High frequency performance comparison 

Classical DL and BDL architecture 

Figure 4 shows the prescaler input and output signal 

working at 8GHz. In the upper curves the MDL 

prescaler of Fig.1 is used, while in the lower curves 

the BDL prescaler is used. The MDL prescaler fails 

to divide correctly while the BDL prescaler continue 

to work properly. The current flow in the logic and 

latch pairs for these two topologies is illustrated in 

Fig 4 (upper curves for BDL and lower curves for 

MDL). It is obvious that the latch pair consumes 

105 

much less current than logic pair. This is partly due 

to the fact that the latch’s setup process is based on 

positive feedback and consumes only small current 

after “startup”. The shrink of latch transistors also 

contribute to this current saving. In the classical 

implementation which employs resistor or constant 

biased transistors for the loads, the current flow 

through this load is always maintained at the same 

high level which is set by the requirement of the 

logic pair. This is clearly not an efficient solution. 

The DL technique tries to provide high current only 

for the logic pair, thus successfully reduces the 

current consumption of the whole prescaler. 

Fig.4 Low frequency failure of MDL 

Maximum input frequency 25GHz 

Minimum input frequency 0.8GHz 

Output Voltage 2 X 250mV pp 

Divide ratio 2 

Supply voltage 1.8v 

Supply current 3.5mA 

Technology 0.18u CMOS 

Table II. Technical data 

Inserting CLK driven tail current source to latch pair 

(MDL) improves the maximum operation frequency 

by roughly 30% but fails to divide in the low 

frequency range (

timeslot. This negative feedback discharges the 

output node and thus counteracts the setup positive 

feedback process of the latch pair which charring the 

output node. The existence of this negative feedback 

timeslot significantly affects the prescaler’s latch 

setup behavior. This timeslot widen as the frequency 

decreases. After a certain frequency threshold, this 

timeslot will be so big that the latch positive 

feedback is totally inhibited and the latch setup fails. 

At this point the prescaler will cease to divide. In the 

MDL configuration the simulated frequency 

threshold is around 8.5GHz. 


Fig.5 Current flow In D-latch 

In the BDL technique, a second load pair is 

introduced, which is driven by the complementary 

clock signal of the first pair. This successfully 

resolves the problem mentioned above and sets the 

lower threshold to around 1GHz. From the figure 5, 

the effect of the second load pair can be seen clearly. 

It injects current to the output node periodically to 

counteract the effect of negative feedback leakage, 

thus the latching process continue to work even at 

very low frequency. 

IV. Conclusion 

A UBW [1-25GHz], low power [3.5mA from 1.8v] 

prescaler was designed. The detailed technical data 

of the designed prescaler is listed in table II. In this 

paper, a new balanced dynamic load architecture 

which improves the frequency operating range by 30 

% was presented. This research illustrates that by 

handling the current flow in the prescaler correctly, a 

106 

“balanced” ultra wide band design with relatively 

low power consumption can be achieved. 

Reference: 

[1] D-J Yang, Kenneth K.O, “A 14-Ghz 256/257 

Dual- Modulus Prescaler with secondary 

Feedback and its application to monolithic 

CMOS 10.4GHz PLL,” IEEE Trans. on 

Microwave Theory and Techniques VOL.52, 

No.2, pp.461-468, Feb, 2004 

[2] Hongmo Wang , US Patent 6,166, 571, 

Dec. 26. 2000 

[3] Hongmo Wang, “A 1.8v 3mw 16.8GHz 

Frequency Divider in 0.25um CMOS,” in IEEE 

Int. Solid-state circuits Conf. Tech. Dig, San 

Francisco, CA, Feb. 2000, pp.196-197 

[4] A. Shinmyo, M. Hashimoto, “Design and 

optimization of CMOS current mode logic 

dividers,” 2004 IEEE AsiaPacific conference on 

Advanced system integrated circuits, 2004 

[5] Hans-Dieter Wohlmuth, Daniel Kehere, et. Al. 

“A 17GHz Dual-Modulus Prescaler in 120nm 

CMOS,” IEEE Radio Frequency Integrated 

Circuits (RFIC) Symposium, pp.479-482, 2003 

[6] Eric Touriner, Mathilde sie, Jacques Graffeuil, 

“A 14.5GHz 0.35um frequency divider for dualmodulus 

prescaler,” IEEE Radio Frequency 

Integrated Circuits (RFIC) Symposium, pp.227- 

230, 2002 

[7] Behzad Razavi, Kwing, F, Lee and Ran H, Yan, 

“Design of high-speed, low power frequency 

dividers and PLLs in deep submicron CMOS,” 

IEEE J. Solid-state Circuits, Vol30, No.2, pp. 

101-109, Feb, 1995.


EMBEDDED HARDWARE ARCHITECTURE FOR 

STATISTICAL RAIN FORECAST 

Tassilo Meindl, Walter Moniaci, Davide Gallesio, Eros Pasero 

Polytechnic of Turin, Neuronica laboratory, 

Corso Duca degli Abruzzi, I-10129 Turin, Italy 

E-mail: tassilo.meindl@polito.it 

ABSTRACT 

Weather forecasts are a typical problem where a huge 

amount of data coming from different types of sensors 

must be elaborated by means of complex, time consuming 

algorithms. In this paper we present a new embedded data 

mining system, based on a FPGA [1], which performs 

statistical data elaboration on sensorial data and provides 

nowcasting for the next one, two and three hours. The 

statistical algorithm has been tested for forecasts of 

temperature, humidity and rain and provides promising 

results. 


Weather forecast systems are among the most heavy 

equation systems that a computer must solve. A very large 

amount of data, coming from satellites, synoptic stations 

and sensors located around our planet give each day 

information that must be used to foresee the weather 

situation in next hours and days all around the world. 

Weather reports give forecasts for next 24, 48 and 72 

hours for wide areas. Today they are quite reliable but it is 

not unusual that in a restricted region the conditions 

suddenly change. Snow, ice and fog are very dangerous 

events that can occur on the roads giving important 

problems for road safety. So whereas a traditional weather 

forecast system provides a powerful system able to give 

indications about the weather evolution in next days in a 

large area, this embedded system is used to make very 

short-term local prediction and warning decisions. This is 

made possible thanks to a powerful suite of detection and 

prediction algorithms. The usefulness of this approach is 

that the knowledge of the next three hours weather 

conditions, for example, can be used to organize outdoor 

activities. For example the knowledge about a rain event 

in next two hours can be used to choose the right set of 

tires in a formula one competition. The knowledge of fog 

occurrence in next three hours allows the airport 

maintenance staff to take in advance important decisions 

in order to avoid canceling flight at the last minute. The 

realization of an autonomous embedded portable weather 

station that can be used without a PC, able to predict 

microclimate meteorological events and alarms in 

restricted areas within short time is therefore an interesting 

and useful approach different from the classical 

macroclimate meteorological forecast systems. 

107 

2. HARDWARE ARCHITECTURE 

We propose a new hardware architecture for embedded 

data processing of sensorial data. In order to increase the 

field of possible applications a distributed hardware 

architecture has been realized. 

Data Management and Controlling Data Processing 

Onboard 

Sensors 

433 MHz 

Radio 

Transceiver 

Wireless 

Sensors 

Real 

Time 

Clock 

LCD 

Display 

32.768 kHz 

Cygnal 8051 

Microcontroller 

USB 

PC 

In System 

Programming 

Control 

Power 

Supply 

Network 

Battery 

2mbit 

Program 

Flash 

24 MHz 

XILINX Spartan 3 

FPGA 

4mbit 

Data 

Flash 

Embedded Data Processing Station 

Figure 1. Embedded Data Processing Station. 

The system as shown in figure 1 is primarily based on a 

microcontroller, which is the heart of the “Data 

Management and Controlling” part, and a FPGA 

connected to several memory blocks, which constitutes the 

“Data Processing” part. The simple and fast modifiability 

of the microcontroller’s firmware, allows for an efficient 

acquisition of sensorial data and the time stamp, and 

provides user interfaces, including the connection to a PC 

or the on-board buttons and display, whereby the 

elaboration of data and the prevision algorithm has been 

implemented completely in the FPGA. The exact timing is 

one of the key points for data processing of sensorial data 

in order to guarantee data consistency whilst not saving 

time stamps into the data memory. Every 15 minutes the 

microcontroller performs data acquisition from the 

sensors, which are displayed directly to the user by a LCD 

display. The FPGA performs the statistical algorithm 

described in the next section and saves the forecast values 

for the next 1, 2 and 3 hours into a data register, which can 

be read by the microcontroller. During operation on 

battery in the absence of powering from the USB 

connector, the microcontroller performs efficient power 

management.

The FPGA core has been implemented completely using 

VHDL. Interfacing to the external components and the 

controlling part has been implemented directly in VHDL, 

whilst the statistical processing part has been implemented 

using CODESIMULINK, a MATLAB tool developed at 

the Polytechnic of Turin, which automatically generates a 

synthesizable VHDL code. 

3. ALGORITHM DESCRIPTION 

The algorithm is composed of a “Best Day Calculation” 

and the forecast module. The “Best Day Calculation” 

module searches in the historical database the day which 

matches best the current day, based on the last four hour 

measures of a particular parameter selected by the Parzen 

method [4]. The gradient evolution of the historical data 

allows then the Forecast module to perform a simple data 

prevision for the next 1, 2 and 3 hours. The rain prediction 

is not an easy problem to solve. In fact rain is not a 

stationary phenomenon and the classical Auto Regressive 

eXogenous [3] model (ARX) does not provide good 

results. In this paper a new approach, based on statistical 

non parametric method, is shown. First we have to decide 

the variables that have more influence on the rain event. 

We used the Parzen method to establish the correlation 

among rain and other meteorological variables. 

3.1 Parzen method 

The goal is to choose the best “predictors” for the rain 

forecast. We define the entropy of the parameters in the 

following way: 

∫ +∞ 

−∞ 

( p( 

x) 

) ⋅ p( 

x) 

e(x) = − log dx 

(1) 

In this formula p(x) is the Probability Density Function 

(PDF) of a random variable x. e(x) is an index of 

dispersion that lies in the range ]-∞,+∞[. Let Z be the 

vector of all the possible predictors that can be used to 

foresee the variable y (predictand). Now let X1 and X2 be 

two particular subsets of predictors taken from Z. The 

number of elements in X1 and X2 has to be the same. In 

order to establish the best set of predictors between X1 and 

X2 we calculated the following entropy difference: 

d( 

X , y) 

= e( 

X , y) 

− e( 

x) 

= −∫ 

log P( 

X , y) 

⋅ P( 

X , y) 

dXdy 

+ 

(2) 

+ log P( 

X ) ⋅ P X dX 


∫ 

( ) 

where P(X,y) is the joint PDF of X and y and P(X) is the 

PDF of X (the predictors). Both PDFs are unknown and 

therefore it’s impossible to evaluate the integrals in (2). 

We circumvented this problem by estimating the unknown 

PDFs through the Parzen method. This method estimates 

the unknown probability density functions making a sum 

of Gauss kernels, each one centered on a record of the 

database. The formula is the following: 

108 

( x x ) 

n m 

∗ 

1 

PX 

( X ; D, 

Λ) 

= ∑∏ n i= 

1 j= 1 

where, 

1 ⎡ 

⋅ exp⎢− 

2 

2πλ 

⎢ 

j ⎣ 

j − ij 

2 

2λ 

j 

2 ⎤ 

⎥ 

⎥⎦ 

(3) 

• D = {X1, …, Xn}: is the data vector 

• n: database dimension (number of records) 

• xi,xij: these are the j-th component of X and Xi • Λ: standard deviation vector, Λ= ( λ1,….,λm) Each standard deviation in Λ �regulates the resolution of 

the estimator along the corresponding dimension. In its 

turn this allows us to estimate d(X 1,y) and d(X 2,y). The 

best between X 1 and X 2 is the one that gives rise to the 

smallest entropy difference. In the case shown in this 

paper the sets X i are the data of the following 

meteorological variables: 

• Air temperature 

• Relative humidity 

• Solar radiation 

• Ground temperature 

• Atmospheric pressure 

At the end of the Parzen simulation we obtain that the 

most important meteorological variable for rain prediction 

is air relative humidity. Then we have to decide how many 

air relative humidity data in the past are necessary to have 

an affordable forecast. We use again the Parzen method 

and it is put in evidence that the last 4 hour humidity 

values are sufficient to make a good prediction. 

3.2 Forecasting algorithm 

Let X be the vector of the last four hour humidity data 

respect to the forecast time j. We, for each day in the past, 

take the last four hour values of humidity respect to the 

instant corresponding to j. In this way we obtain a matrix 

Z (nxm) containing the past humidity values for each day. 

The number of rows of Z has to be the same of X; the 

number of columns is determined by the number of days 

recorded in the database. Let Y a particular day in the past. 

Then we calculated the mean square error for each past 

day as shown in the following formula: 

n 1 

2 

MSE = ∑ ( X i − Yi 

) 

(4) 

n i= 

1 

At the end of this calculus we have a vector E containing 

the MSE for all the past days. We choose the day with the 

smallest MSE. In this way it’s identified the “matching 

day”: this is the day in witch the humidity trend is closest 

to the humidity values of the forecast day at the time j. 

After this we fit the rain values of the match day in the 

next three hours after j with a polynomial of the third 

order. Then the forecast rain values are obtained adding to 

the last rain measure the rain gradient of the match day, as 

shown in the following formula:

( t + ) = m( 

t) 

+ [ p ( t + 1) 

− p ( t) 

] 

P 1 M 

M 

(5) 

where, 

• P(t+1): is the rain forecast value 

• m(t): is the measured rain at the time t 

• pM(t+1): is the rain value of the match day at 

time t+1 

• pM(t): is the rain value of the match day at time t 

It is important to underline that P M (t) and P M (t+1) are not 

the measured rain values but the value obtained with the 

third order model. In this way we circumvent the problem 

of wrong measures and we have a smoothest rain gradient. 


4. IMPLEMENTATION 

4.1 Database Organization 

In our case 3 values are measured every 15 minutes, 

namely air temperature, humidity and precipitation with a 

precision of 16 bits. This means that for each day 288 

values have to be stored, which requires 4608 bits in the 

data memory. Therefore we selected a 4 Mbit Flash 

memory which allows us to store the values of 

approximately 2 ½ years which is more than sufficient as 

historical database for the statistical forecasting algorithm. 

Since each day contains always exactly 288 measurements 

we can segment the complete memory in day-slots of 4608 

bits representing respectively the separate days with 96 

time-slots each containing 3 measured values. From the 

current time we can then calculate the memory position 

where the next measured values have to be stored into. 

It has to be stressed that for this calculation the current 

measurement time is sufficient. Since we search in the 

historical database only the “Best matching day”, it is not 

problematic if several days in the database are missing e.g. 

due to battery failure. Therefore we do not add these 

missing days to the database but we proceed directly with 

the next free day-slot in the database. Consequently only 

the last saved database position is necessary to perform the 

complete management. After a battery exchange or other 

power failures this last database position can be searched 

easily and in case the current measurement time does not 

represent the expected next database position we try to 

reconstruct the missing values by means of an 

approximation through a typical standard day cycle in 

order to allow anyhow a forecast, which, however, is 

unlikely to be very reliable for the next 4 hours, namely 

till the necessary previous measurements are available for 

the “Best Day Calculation”. 

4.2 Synthetic Database 

In order to make the system at once working it is 

necessary to have a large database for the best day 

calculation. The system would not operate reliable after a 

new installation and several days or even months would be 

necessary till the required data have been collected. To 

avoid this problem we created a synthetic database able to 

represent the meteorological characteristics of the place 

the system is installed in. During a new installation this 

database can be updated from the PC in two modes. In the 

109 

extended version a complete year of the current location is 

loaded into the data memory: However these data might 

not be available always and therefore in the compact 

version only 60 significant days for typical regions in 

Western Europe (see table 1) are loaded into the data 

memory. In this way the system can run at once using this 

synthetic database and then acquired data can be 

appended. 

Table 1. Typical Western European Regions. 

Terrain Features 

Open Open site, open terrain, north facing 

incline, no raised skyline (Applies to 

most sites.) 

Depression Depression on very flat valley floor, 

in which cold air collects, particularly 

the Jura and the Alps 

Sea/lake Shore of sea or larger lake (up to 1 km 

from the shore 

City Center of a larger city (over 100'000 

inhabitants) 

Valley Valley floor in mountainous valley at 

higher altitudes. Valley floor inclined 

(flat valleys are often treated as 

depressions) 

Valley Central Floor of large central Alpine valley 

Alps 

(e.g. Alpine regions of Velais) 

Föhn valley Valley floor of föhn valley (regions 

with warm descending air currents) 

Valley Alpine Valley floor in northern Alpine 

foothills foothills 

4.3 Forecasting process 

As explained in the previous section we only have to find 

the day where the MSE is lowest. This can be achieved by 

means of simple additions and subtraction as can be seen 

in equation 4. In the implementation we even do not need 

the division by n since n remains constant. After 

determining this best matching day the only thing to do is 

to add the gradient for the next 1, 2 and 3 hour to the 

current measurement value as can be seen in figure 2. The 

same procedure can be applied to the temperature forecast. 

For the rain forecast we have to search the “Best Matching 

Day” in the humidity database, but we use the rain values 

for forecasting. However, since the basic algorithm is 

independent from the data type we reuse the same FPGA 

core for all forecasting. 

It must be admitted that up to know the algorithm is quite 

simple and an implementation directly in a FPGA might 

seem unnecessary, mainly because the predictor for the 

rain forecast has been established previously by simulation 

at the PC. But with additional sensorial information such 

as solar radiation and the necessity to determine other 

weather events such as fog or ice formation, the reliability 

of the forecasting process has to be increased by 

dynamically determining the optimal predictors previous 

to each forecasting process and neural networks might be 

necessary to perform the forecasting in order to account 

for cross correlations among several predictors. Both of 

these improvements have just been tested successfully by

means of simulation. However these algorithms are 

elaborate and time-consuming and therefore can be 

implemented best in a FPGA [5]. 

Relative Humidity [%] 

Relative Humidity [%] 

100 

90 

80 

70 

60 

50 

40 

30 

20 

10 

100 

90 

80 

70 

60 

50 

40 

30 

20 

10 


Best matching day 

Humidity Measurements 

Rain Measurements 

Best Day Calculation Forecasting 

Time-slot 

Current day 

Humidity Measurements 

Humidity Forecasts 

Rain Measurements 

Rain Forecasts 

Best Day Calculation Forecasting 

Time-slot 

Figure 2. Example Forecast. 

5. RESULTS 

The algorithm described in the previous section has been 

applied to rain data of a meteorological station positioned 

on the roof of Polytechnic of Turin. The period of 

observations is between 15/03/2004 and 29/03/2004. In 

the following figure are shown the forecast values 

compared with the measured values. 

[mm] 

[mm] 

[mm] 

[mm] 

15 

10 

5 

RAIN MEASURES 

0 

0 200 400 600 Time 800 1000 1200 1400 

15 

1 HOUR FORECASTS 

10 

5 

0 

0 200 400 600 Time 800 1000 1200 1400 

15 


10 

5 

0 

0 200 400 600 Time 800 1000 1200 1400 

10 


5 

0 

0 200 400 600 Time 800 1000 1200 1400 

Figure 3. Forecast and measured values. 

In order to evaluate the quality of the predictions we 

calculate the mean square error for the 1, 2 and 3 hour 

forecasts. We can see that the results are good; in fact even 

in the three hour forecast the mean square error is low if 

we consider that the pluviometer sensibility is 0.2 mm. 

20 

18 

16 

14 

12 

10 

8 

6 

4 

2 

20 

18 

16 

14 

12 

10 

8 

6 

4 

2 

Precipitation [mm] 

Precipitation [mm] 

110 

Table 2. Mean square error values. 

1 h forecasts 2 h forecasts 3 h forecasts 

MSE 0.37 mm 2 0.42 mm 2 0.49 mm 2 

VRC 0.39 0.43 0.51 

Then we calculate also the Variance Reduction Coefficient 

as shown in the following formula: 

1 1 

VRC = ⋅ 

2 

σ N 

where, 

N 

∑ 

i= 

1 

2 

( x − xˆ 

) 

• x i : is the forecast value 

i 

i 

• xˆ i : is the measured value 

• N: is the number of observations 

This index is very meaningful: in fact it puts in evidence 

how much the variability of the process (rain in this case) 

is explained by the predictor used (humidity). Lower is the 

VRC value higher is the forecast value. In this case, being 

the value less than 1 in all cases, it means that the mean 

square error is less than the intrinsic variability of the 

phenomenon expressed by the variance. 

6. CONCLUSION 

The main characteristic of this embedded data processing 

station for sensorial information is that the basic statistical 

algorithm in the FPGA core in future can be exchanges or 

extended with more powerful algorithms such as neural 

networks [1] which have just been tested with MATLAB. 

Then, being this platform independent of the type of data, 

it can be used to monitor and foresee any time series such 

as air pollution data, and so on. 

7. REFERENCES 

[1] E. Pasero, W. Moniaci and T. Meindl, FPGA based 

statistical data mining processor, XV WIRN, Perugia, 

Italy,15-17 September 2004. 

[2] E. Pasero and W. Moniaci, Artificial neural networks 

for meteorological nowcast, IEEE CIMSA, Boston, 

USA 14-16 July 2004. 

[3] E.W. Jensen, P. Lindholm and S.W. Henneberg, 

Autoregressive modeling with exogenous input of 

middle-latency auditory-evoked potentials to measure 

rapid changes in depth of anesthesia, Methods of 

Information in Medicine, Vol 35, pp 256-260, 1996. 

[4] E. Parzen, On Estimation of a Probability Density 

Function and Mode, Ann. Math. Stat., Vol 33, pp 

1065-1076, 1962. 

[5] A.R. Omondi and J.C. Rajapakse, Neural Networks 

in FPGAs, Proceedings of the 9th International 

Conference on Neural Information Processing, Vol.2, 

pp.954-959, 2002. 

(6)


A HIGH THROUGHPUT FPGA CAMELLIA 

IMPLEMENTATION 

Daniel Denning, James Irvine, Malachy Devlin 

Institute of System Level Integration, Alba Centre, Alba Campus, 

Livingston, EH54 7EG, UK 

E-mail: daniel.denning@sli-instiute.ac.uk 

ABSTRACT 

In this paper we present a Field Programmable 

Gate Array (FPGA) implementation of the 

Camellia encryption algorithm. Our 

implementation deeply sub-pipelines the algorithm 

for the FPGA architecture. Camellia has been 

included in both portfolios of the New European 

Schemes for Signatures, Integrity, and Encryption 

(NESSIE) for Europe and the Cryptography 

Research and Evaluation Committee (CRYPTREC) 

in Japan. The implementation is the fastest 

published throughput for the entire block ciphers 

recommended in both portfolios for NESSIE and 

CRYPTREC, and runs at a throughput of 

33.25Gbit/sec. 


The Camellia [1] symmetric-key block cipher has 

been recognised by an open call from NESSIE [2] 

and CRYPTREC [3] as a cryptographic algorithm 

to help protect the current and future information 

society. FPGAs provide a very beneficial platform 

for implementing cryptographic systems because of 

the inherent parallelism of the device. 

NESSIE was a European Union (EU) initiative 

and a project with in the Information Society 

Technologies (IST) of the EU. Camellia was 

selected with three other block ciphers from the 42encryption 

algorithms that were submitted. The 

other two block ciphers being MISTY1 and 

SHACAL-2. The AES algorithm was also selected 

but selected on its evaluation from the National 

Institute of Standards and Technology (NIST). 

Other algorithms included digital signatures, 

identification schemes, public-key encryption, MAC 

algorithms, and hash functions. 

The Camellia algorithm is a 128-bit block 

cipher jointly developed by NTT and Mitsubishi 

Electric Corporation. The algorithm has also been 

submitted to other standardisation organisations and 

111 

evaluation projects such as ISO/IEC JTC 1/SC 27, 

IETF, and TV-Anytime Forum. Previous Camellia 

implementations have been published in [4,5] but 

do not investigate a sub-pipelining architecture. 

2. OVERVIEW OF CAMELLIA 

ALGORITHM 

The Camellia algorithm processes data blocks of 

128-bits with secret keys of lengths 128, 192, or 256 

bits. Note that Camellia has the same interface as 

the AES (Advanced Encryption Standard). In our 

implementation we focus on the algorithm using a 

key length of 128-bits that is key agile. A key agile 

core requires that on each clock cycle new data and 

cipher key must be accepted. 

A key length of 128-bits results in an 18 round 

Feistel structure. After the 6 th and 12 th rounds 

FL/FL -1 function layers are inserted to provide some 

non-regularity across rounds. There are also two 

64-bit XOR operations before the first round and 

after the last, also known as pre- and postwhitening. 

The top-level structure of the algorithm 

can be seen in Figure 1, as well as the inner 6 round 

structure. The key schedule, discussed later in this 

section, generates subkeys for each round, FL/FL -1 

layers, and pre- and post-whitening. 

The FL-function is defined by: 

YR(32) = ((XL(32) ∩ klL(32))

FL 

FL 

M(128) 

kw1 kw2 

k1, k2, 

k3, k4, 

k5, k6 

kl1 

k7, k8, 

k9, k10, 

k11, k12 

kl3 

k13, k14, 

k15, k4, 

k5, k6 

kw3 

64 64 

C(128) 

FL -1 

FL -1 

Figure 2. Key schedule architecture for 

Camellia 

represents a substitution using one of 4 s-boxes that 

are defined by: 

S1(x) = h(g(f(x ⊕ a))) ⊕ b, (4) 

S2(x) = S1(x) > 1, (6) 

S4(x) = S1(x

Camellia 1 

3. SUB-PIPELINING ARCHITECTURE 

In this section we describe the sub-pipelined 

architecture but it includes previous classical 

encryption optimisation techniques to increase the 

algorithms throughput at the higher level within the 

algorithm. These include such optimisations as 

unrolling, round pipelining, and transformation 

partitioning. The implementation is key agile thus 

providing very high security and throughput as new 

data blocks can be encrypted on each clock cycle 

with a different key. 

For the sub-pipelining architecture we have fully 

unrolled and added pipelining registers between 

each encryption round. We have then also added 5 

stages of sub-pipelining shift registers into the F- 

Function. The registers have been added between 

the P-Function, S-Function and the XOR. With a 

pipeline stage also added into the P-Function and a 

register at the output of the F-function. This 

architecture produces a pipeline delay of 108 clock 

1 Included in both CRYPTREC and NESSIE. 

2 Finalists not included in NESSIE portfolio. 

3 Implemented on a Altera FPGA device 

4 Only able to find ASIC implementation 


Table 1. Summary of CRYPTREC and NESSIE 128-bit Block Cipher Winners 

and Finalists on FPGAs 

Algorithm Authors Device Area Key Throughput Efficiency 

Slices 

(BRAMS) 

agility Gbits/sec Mbps/slices 

Authors XC2Vp50 11,287 

(88) 

YES 33.25 - 

AES-128 1 

Zambreno 

et al. [6] 

XC2V4000 16938 YES 23.57 1.39 

MISTY1 1 

Rouvroy et 

al. [7] 

XCV1000 6,322 YES 19.34 3.06 

SHACAL-1 2 McLoone et 

al. [8] 

XC2V4000 13,729 NO 17.02 1.24 

IDEA 2 

Gonzalez et XCV600 12,026 NO 8.3 0.69 

al. [9] 

(estimated) 

RC6 2 

Beuchat XC2V3000 8,554 NO 15.2 - 

[10] 

(80) 

(assumed) 

Hierocrypt-3 3 

Rogawski EPF10K130V 25811 YES 0.397 - 

[11] 

LE 

(assumed) 

CIPHERUNICORN- 

A 3 

NEC [12] EP20K1500E 7072 LE YES 0.044 - 

(66 

ESB) 

SC2000 4 

Shimoyama CPF10K130V 25811 YES 0.397 - 

et al. [13] 

LE 

(assumed) 

113 

cycles but does not have an effect on throughput. 

Further improvements might be made with some 

algorithm optimisations or floor planning. Adding 

the registers into the P-Function means that the 

function now has a branch number of 3 or 2 instead 

of 5 depending on the data path. The architecture 

of F-Function can be seen in Figure 3 on the 

previous page. The registers can be seen inbetween 

each of the F-function operations. 

One other important optimisation techniques 

specific for the FPGA architecture is the use of 

dual-port block-RAM. Every round has its own 

associated F-function, as described earlier, and each 

function utilises 4 different s-boxes for byte 

substitution. Each F-function makes 2 calls to the 

same s-box. For this implementation we have 

chosen to use dual ported block-RAMs for the sboxes. 

4. RESULTS 

We have implemented the sub-pipelined 

architecture on a Virtex-II pro XC2Vp50 device. 

The core was designed with Xilinx’s System 

Generator, which produced the VHDL and 

associated files. The VHDL was synthesised with 

ISE 5.2 and verified with the test vectors that were

submitted to NESSIE. The core runs at a frequency 

of 259MHz that results in a throughput of 

33.25GBits/sec. The implementation requires 

11,287 slices (47%) of the FPGA and uses 88 block- 

RAMs (37%). Generally comparisons against other 

encryption implementations can be difficult and can 

depend on architecture, device, embedded cores 

such as block-RAM, key agility, on-chip key 

scheduling, and other such criteria. Table 1 shows 

a list of other known high throughput FPGA 

architectures for NESSIE and CRYPTREC. For 

implementations that have used block-RAMs we 

have not included the efficiency. It is possible to 

calculate the extra number of slices that the block- 

RAMs would occupy if distributed memory was to 

be used, but this sort of calculation doesn’t take into 

account the extra routing, which would have an 

effect on the total throughput and therefore the 

efficiency. 


5. CONCLUSION 

In this paper we have presented a sub-pipelined 

Camellia implementation that has a throughput of 

33.25Gbit/sec. Compared to other published FPGA 

implementations this is the fastest known 

throughput of all block ciphers (128-bit) 

recommended by NESSIE and CRYPTREC. The 

importance of this algorithm has been proved in the 

open-call by NESSIE and CRYTREC. 

The core is able to receive new secret keys and 

data on every clock cycle. We have utilised the 

available dual-port block-RAMs for use in the F- 

Function and been able to pipeline the algorithm to 

the lowest level and then apply this to the FPGA 

architecture. The core has a very high throughput 

and thus could be used in a secure high 

performance computing application. As the core 

takes less then 50% of the Virtex 2 pro it might be 

possible to put two cores down thus being able to 

obtain a throughput on one FPGA device of around 

66Gbits/sec. This will be part of the work for the 

future. 

6. REFERENCES 

[1] Aoki, K., Ichikawa, T., Kanda, M., Matsui, M., 

Moriai, S., Nakajima, J., Tokita, T., 

“Specification of Camellia – 128-bit Block 

Cipher”, URL: 

http://info.isl.ntt.co.jp/camellia/#Spec, 

September 2001. 

114 

[2] NESSIE, “NESSIE Project Announces Final 

Selection of Crypto Algorithms”, IST-199- 

12324, February 2003. 

[3] CRYPTREC, Information-Technology 

Promotion Agency, Japan, “CRYPTREC 

Report 2002”, 

[4] Denning, D., Irvine, J., Delvin, M., “A Key 

Agile 17.4Gbit/sec Camellia Implementation”, 

proceedings of FPL’04, Antwerp, Belgium, 

Aug. 2004. 

[5] Ichikawa, T., Sorimachi, T., Kasuya, T., 

Matsui, M., “On the Criteria of Hardware 

Evalution of Block Ciphers(1)”, Techn report 

of IEICE, ISEC2001-53, September 2001. 

[6] Zambreno, J., Nguyen, D., Choudhary, A., 

“Exploring Area/Delay Tradeoffs in an AES 

FPGA Implementation”, proceedings of 

FPL’04, Antwerp, Belguim, Aug. 2004. 

[7] Rouvroy. G., Standaert, F.X., “Efficient FPGA 

Implementation of Blcok Cipher MISTY1”, 

proceedings IPDPS’03, France, April 2003. 

[8] McLoone, M., McCanny, J. V., “Very High 

Speed 17 Gbps SHACAL Encryption 

Architecture”, in Proc. Of the 13 th Int’l 

Conference on Field-Programmable Logic and 

its Applications (FPL), Portugal, September 

2003. 

[9] Gonzalez, I., Lopez-Buebo, S., Gomez, F. J., 

Martinez, J., “Using Partial Reconfiguration in 

Cryptographic Applications: An 

Implementation of the IDEA Algorithm”, in 

Proc. Of the 14 th Int’l Conference on Field- 

Programmable Logic and its Applications 

(FPL), Portugal, September 2003. 

[10] Beuchat, J. L., “FPGA Implementations of the 

RC6 Block Cipher”, in Proc. Of the 13 th Int’l 

Conference on Field-Programmable Logic and 

its Applications (FPL), Portugal, September 

2003. 

[11] Rogawski, M., “Analysis of Implementation 

Hierocrypt-3 Algorithm (and its comparison to 

Camellia algorithm) using ALTERA devices”, 

Electronic Edition, CoRR cs CR/0312035, 

2003. 

[12] NEC Corporation, “Self Evaluation Report – 

CIPHERUNICORN-A”, unpublished date. 

[13] Shimoyama, T., Hitoshi, Y., Kazuhiro, Y., 

Takenaka, M., Itoh, K., Yjima, J., Torii, N., 

Tanaka, H., “Specification and Supporting 

Document of the Block Cipher SC2000”, IST- 

199-12324, February 2003.


A NOVEL APPROACH BASED ON DYNAMIC 

RECONFIGURATION FOR PROCESS CONTROLS 

WITH FPGA. 

Tommaso Ramacciotti ‡ , Luca Serafini ‡ , Luca Fanucci ‡ , Stefano Baldacci † 

‡ Department of Information Engineering, University of Pisa, Via Caruso, 56122 Pisa, ITALY 

† Kayser Italia Srl, Via di Popogna 501, 57128 Livorno, ITALY 

E-mail: {t.ramacciotti,l.serafini,l.fanucci}@iet.unipi.it; s.baldacci@kayser.it 

ABSTRACT 

A demonstrative application of dynamically reconfigurable 

FPGA (D_FPGA) is presented along with a 

dedicated novel design methodology and software tools 

which has been developed in the framework of an 

European Community funded project (RECONF). The 

application being developed consists in the re-design, by 

using a D_FPGA, with an embedded microcontroller, of 

the control electronics of a scientific space experiment 

module initially based on an One Time Programming 

(OTP) FPGA. The demo application aims to demonstrate 

the benefit achieved from the design of complex systems 

based on the dynamic re-configuration of SRAM based 

FPGA. Adopting a D_FPGA approach we expect a 

performance improvement in terms of silicon area, power 

reduction and a decrease of the development time/costs. 


In the design of space qualified electronic systems reconfigurable 

FPGA offer the advantage of considerable 

reduction of development time and costs. In fact a design 

error (as trivial as an inverted signal) in an OTP FPGA 

makes this device (once programmed) unusable and a new 

FPGA has to be programmed. This “trial and error” 

approach shows to be costly in terms of development time 

and also in terms of wasted FPGA and printed circuit 

boards (note here that space qualification for PCBs allows 

a maximum of three soldering de-soldering cycles for any 

given pad). Therefore, employment of dynamic reconfigurable 

FPGA is highly desirable in this field, 

because the FPGA configuration can be modified even 

when the device is soldered onto a PCB. 

The bitstream of a D_FPGA[2] is composed by a static 

module (loaded at the system start up and never changed) 

and some dynamic modules (d_module) that can be loaded 

and unloaded asynchronously according to the user 

requirements. Any number of d_modules can be loaded 

and co-exist into the D_FPGA up to its bitstream memory 

size. Any complex design can, in principle, be subdivided 

into small d_modules which implement the same 

functionalities at time division. Using this approach we 

can increase the functional density of an FPGA and 

115 

complex designs can fit into a D_ FPGA with a relatively 

small gate count. 

The limitation to the applicability of this approach for a 

real time control with respect to a standard pipelined 

architecture is represented by the reload time of the 

dynamic modules. In fact to obtain a correct sampling of 

the input signals the system must satisfy the following 

requirement: 

∑ [ Treload] + ∑[ 

Tproc] 

< ⋅Tsampling 

where Treload represent the reload times of all the 

dynamic modules and Tproc are the processing times of 

the modules. Tsampling instead represents the minimum 

time interval at which the fastest input signal must be 

acquired. 

If this condition is satisfied we can approach the system 

design in a dynamic fashion, designing the single 

processes independently and loading them separately in 

the FPGA at run time. 

In spite of the wide availability of re-configurable FPGA 

architectures on the market, there are no adapted design 

methodologies and no tools on the market to support 

electronic designs based on D_FPGA. Developers are still 

using classical design environments, which are not 

adapted to an efficient approach, especially regarding the 

dynamic system specificity. 

In the framework of the European Community funded 

project IST-RECONF[1] new software tools and 

methodology for the design of systems with dynamically 

re-configurable FPGA has been developed and evaluated. 

The aim of this project is to allow the implementation of 

adaptive system architectures by defining a methodology 

and developing the required design environment to take 

full benefits of D_FPGA. The output of the project is a 

complete and validated design environment composed of 

the following parts: 

• New and adapted design methodology addressing 

partitioning and scheduling issues including the 

availability of a Designer’s Guide

• Front-End tools adapted to D_FPGA but 

independent from the IC manufacturer’s technology 

• Back-End tools adapted to D_FPGA and dependent 

on the IC manufacturer’s technology. 

• Configuration controller generator to generate a 

Hardware/software description of the configuration 

controller that will be in charge of managing the 

reconfiguration process. It could be generated 

automatically, or under user constraints. 


2. THE TECHNOLOGY 

The Back-End tools previously introduced which 

implement the modular placement and routing of the 

different module onto the D_FPGA fabric are obviously 

technology dependent. The Back-End tools being 

developed for the RECONF project are dedicated to the 

AT40K and AT94K (a version of the AT40K family with 

an AVR microcontroller embedded) FPGA families from 

ATMEL®. In our work we used the AT94K line of 

products which is briefly introduced (Figure 1). 

Configurable SRAM 

AT40K FPGA 

Figure 1. Atmel® AT94K40 

36K bytes of SRAM 

40K gates 

The ATMEL® users have been using micro controllers to 

control their applications while using FPGAs to 

implement interfaces and glue logic. This fact led the 

ATMEL® Corp. to the development of a new device that 

combines an 8-bit RISC AVR micro controller and an 

AT40K-type FPGA. The ATMEL® Corp. has categorized 

this new device AT94K as a Field- Programmable System 

Level Integrated Circuit (FPSLIC) [4]. There are three 

AT94K devices available (AT94K05, AT94K10, and 

AT94K40). They differ only in the number of the gates, 

and in the size of the AVR program memory. The AVR 

core is based on an enhanced RISC architecture that 

combines a rich instruction set with 32x8 general-purpose 

working registers. The FPGA and AVR share a flexible 

interface which allows for many methods of system 

integration. Four memory locations in the AVR memory 

map are decoded into 16 select lines (8 for AT94K05) and 

are presented to the FPGA along with the AVR 8-bit data 

bus. The FPGA can be used to create additional custom 

peripherals for the AVR micro controller through this 

116 

interface. In addition there are 16 interrupt lines (8 for 

AT94K05) from the FPGA back into the AVR interrupt 

controller. The FPGA I/O selection is controlled by the 

AVR. Another communication can be made through a 

dual-port SRAM between both devices. The port 

connected to the FPGA is used to store data without using 

up bandwidth on the AVR system data bus. Through this 

communication interface AVR can access the 

configuration memory of the FPGA allowing the user to 

re-configure the FPGA through the AVR. This represents 

the basics of dynamic reconfiguration [5]. 

3. A DEMONSTRATIVE SPACE 

APPLICATION 

The demonstrator envisages the re-design of a Micro 

Controller Module (MCM) of an experiment module used 

for a scientific experiment based on a common OTP 

FPGA (static) in addition to a 80KC186 micro by using 

D_FPGA with a microcontroller embedded aiming to 

improve the system performances in terms of power, 

silicon area, system reliability and flexibility. The original 

MCM in addition to the normal experiment parameters 

monitoring operation implements in software on a 

80KC186 controlling loops for Temperature, Pressure and 

Critical Heat Flux, for an experiment chamber in a 

microgravity environment (µg). The original design 

featured a process control cycle timing of about 10 ms for 

the three controls. In the new design we are seeking to 

improve the time performances and to reduce the silicon 

usage as well. 

3.1 Hardware design 

The system being re-designed lends itself to a 

configuration composed of a static part, which implements 

basic functionalities such as memory management and 

peripherals control and three dynamic modules which 

implement the controlling processes of the experiment. 

In the new electronic design the D_FPGA replaces the 

existing OTP FPGA. The controlling processes 

(Temperature, Pressure, Critical Heat Flux) are migrated 

in the D_FPGA. The controlling processes run 

independently and each process is loaded and unloaded 

from the D_FPGA at pre-defined time intervals. The 

initial loading of the static part and the subsequent 

loading/unloading of the d_modules is in charge of the 

configuration controller which is implemented in the 

embedded micro controller (AVR).

AVR 

WDT 

TO EXTERNAL 

MEMORY 

RECONFIGURATION 

INTERFACE 

DAC 

INTERFACE 

ADC 

INTERFACE 

TO AD & DA Converters 

Figure 2. Demonstrator D_FPGA 


SuperMacro 

Static module 

Dynamic module 

TEMPERATURE 

PRESSURE 

HEAT FLUX 

Save and restore register 

FiniteStateMachine 

To PC Simulator 

The complete bitstream including the static part with the 

three d_modules is stored in the SRAM configuration 

memory inside the D_FPGA (Figure 4). 

3.2 Configuration Controller (CC) 

The implementation of the configuration controller holds a 

great importance in the design flow of complex systems 

based on D_FPGA. The configuration controller 

represents the most critical part of a D_FPGA and a 

malfunctioning to this very part of the system would result 

in a serious loss of functionality. 

In the RECONF design flow of D_FPGA based systems 

one must carefully consider the different approaches for 

the implementation of the configuration controller. We 

have chosen an “embedded” implementation using the 

D_FPGA internal microcontroller as configuration 

controller because it leads to a system of lower 

complexity: there is no need of external hardware and 

software to implement the functionalities of the 

configuration controller. 

During the start-up of the system the configuration 

controller is in charge to load the static part from he 

internal SRAM (Figure 4) that remains always placed in 

the same area of the configuration SRAM. Along with the 

static part also the first dynamic module is loaded. The 

next d_module gets loaded in place of the previous one 

after a predefined time interval while the rest of the system 

keeps working without interruption of functionality (see 

Figure 3). 

117 

Silicon 

Area d_mod1 

d_mod1 

d_mod3 

d_mod2 

Static part 

Trl=reload time 

TL=latency time 

Figure 3. d_modules context switching 

. . . 

During the sequential loading/unloading of the d_modules 

the status of the respective data signals are saved first and 

then restored by means of registers implemented in the 

static part of the D_FPGA (Figure 2). 

Static 

module 

D_mod_1 

D_mod_2 

D_mod_3 

Static 

module 

D_module_x 

CC 

AVR 

Figure 4. The CC is in charge to load the 

d_modules from the Configuration SRAM 

3.3 Considerations on fault tolerance 

Several considerations have to be taken in account to 

increase the fault tolerance of the system. For the 

d_modules, the continuous re-load of them eliminates any 

possible configuration error because each d_modules get 

refreshed at every re-configuration cycle. Regarding the 

consistency of the static part, there is no opportunity to 

take advantage of the continuous reloading at each reconfiguration 

cycle. To solve this problem the static part 

(now termed “pseudo-static”) can be implemented by a 

d_module with a double redundancy and an error detection 

circuitry which generates a trigger signal to the 

configuration controller when the outputs of the two 

blocks are different (an error as occurred ). In this case the 

Time

configuration controller re-loads the whole module from 

the D_FPGA internal bitsteam memory (see Fig. 5). 

Static 

Static 

D_FPGA 


Error 

Re-load 

Figure 5. Error detection and correction 

4. CONCLUSION 

Bitstream memory 

Configuration 

Controller 

A design methodology based on ATMEL® technology 

and novel design tools has been presented. The software 

tools have been developed within the framework of the 

European Community RECONF project. 

All the reconfiguration process of the D_FPGA is carried 

out by a configuration controller which can be generated 

automatically, or under user constraints, by the RECONF 

Front-End tools. The configuration controller is 

implemented in the internal micro-controller (AVR). 

The following table reports the results of the tests 

performed with the original implementations of the MCM 

and with the approach based on D_FPGA: 

Table. 1. Comparison of the two designs. 

Complexity 

[used Gates] 

Power 

consumption 

Time 

performances 

Original 

design 

D_FPGA 

design 

Improvement 

60000 35000 - 42% Area 

Usage 

110mA 

(OTP 

FPGA 

+80186 

10 ms 

(controls 

cycle) 

60mA 

(FPGA+A 

VR) 

~10 ms 

(controls 

cycle) 

- 45% Power 

reduction 

unchanged 

118 

We have successfully demonstrated the applicability of 

the Dynamic Reconfiguration to a real process control 

task. This design methodology is well suited in space 

applications where the reduction of the silicon area and 

the power consumption of the FPGA system is of primary 

importance. 

5. REFERENCES 

[1] RECONF Dissemination WWW Server 

http://www.reconf.org/ 

[2] J. Manuel Moreno "Dynamic Reconfigurable 

FPGAs” Second Workshop on Reconfigurable 

Computing and Applications. Almunecar, Spain 

[3] Rafal Kielbik "High-Level Partitioning of 

Digital Systems Based on Dynamically 

Reconfigurable Devices". FPL2002 Montpellier, 

France 

[4] Atmel Corp. AT94K Series FPSLIC, June 2002. 

[5] Atmel Corp. AT94 K Series Cache Logic 

(Mode 4) Configuration, July 2001.


AN OVERVIEW OF SystemC FL 

K.L. Man 

Formal Methods Group, Department of Mathematics and Computer Science, 

Eindhoven University of Technology, P.O.Box 513, 5600 MB Eindhoven, The Netherlands 

Email: kman@win.tue.nl 

ABSTRACT 

This paper describes our on-going research. Recently, we developed 

an algebraic theory based on classical process algebra 

ACP, called SystemC FL , for the specification and analysis of 

SystemC designs. The semantics of SystemC FL is defined by 

means of deduction rules in a standard structured operational 

semantics style that associate a labelled transition transition 

system with a SystemC FL process. In this paper, we first provide 

an overview of the current status of SystemC FL and show 

some practical applications of SystemC FL , as well as some 

key features and results of SystemC FL . Then, we give an outline 

for the latest developments of SystemC FL and point out 

the direction for future work. 


Process algebras are useful tools for the specification and verification 

of various systems. General speaking, process algebras 

describe the behavior of processes, and provide operations 

that allow to compose systems in order to obtain more complex 

systems. Moreover, the analysis and verification of systems 

described using the process algebras can be partially or completely 

carried out by mathematical proofs using the equational 

theory. 

SystemC [1] is a modeling and simulation language (without 

formal semantics) based on C++ for hardware and system level 

design modeling. Recently, SystemC has received an extreme 

increase in industrial acceptance for system specification and 

simulation. 

The goal of developing a formal semantics is to provide a 

complete and unambiguous specification of the language. It 

also contributes significantly to the sharing, portability and integration 

of various applications in simulation, synthesis and 

formal verification. 

Over years, research in formal semantics in electronic community 

mainly focused on Verilog, VHDL, and SystemC. In 

general, their definitions were based on Abstract State Machine 

(ASM) specifications and Denotational Semantics. For instance 

(as previous work for SystemC), the simulation semantics (including 

watching statement, signal assignment, and wait statement) 

of SystemC in the form of distributed Abstract State Machine 

(ASM) specifications and the Denotational Semantics for 

a synchronous subset of SystemC were studied by [9] and [10] 

respectively. It is generally believed that the structured operational 

semantics (SOS style) [4] is more intuitive, and the 

methods of ASM specifications and denotational semantics ap- 

119 

pear to be difficult to apply to describe the dynamic behavior 

of processes (as shown in [5]). Since processes are the basic 

units of execution within Verilog, VHDL, and SystemC that are 

used to simulate the behavior of a device or a system, process 

algebras with the SOS style semantics are instinctively the best 

choices for giving formal specifications of systems in electronic 

community. 

Last year, the introduction of SystemC FL [2] based on classical 

process algebra ACP [3] for the specification and analysis 

of SystemC designs, initiated an attempt to extend the 

knowledge and experience of the field of process algebras to 

the field of hardware/software co-designs. The semantics of 

SystemC FL is defined by means of deduction rules in a SOS 

style that associate a labelled transition transition system with 

a SystemC FL process. A set of SystemC FL properties was 

presented for a notion of bisimilarity. By using this process 

algebra based formalism, we can give unambiguous specifications 

of SystemC designs which are possibly analyzable with 

automated software tools. Furthermore, SystemC FL can be 

purportedly used for formal verification. 

The goal of this paper is to provide an overview of the current 

status of SystemC FL , to show some practical applications, key 

features and results of SystemC FL , as well as the latest developments 

of SystemC FL . 

This paper is organized as follows. In section 2. , we review 

the syntax and formal semantics of SystemC FL . Section 

3. illustrates the use of SystemC FL with some case studies 

taken from literature. Some key features and results of 

SystemC FL are shown in Section 4. . Finally, some concluding 

remarks are made in Section 5. . 

2. FORMAL LANGUAGE SystemC FL 

In this section, we give an overview of the formal language 

SystemC FL proposed in [2] and [8]. For an extensive treatment 

of SystemC FL , the reader is referred to those papers. 

2. 1 SystemC FL date types 

In order to define the semantics of SystemC FL processes, we 

need to make some assumptions about the data types. Let Var 

denote the set of all variables (x0, . . . , xn), and Value denote 

the set of all possible values (v0, . . . , vm) that contains 

at least B (booleans) and R (reals). A valuation is a partial 

function from variables to values (e.g. x0 ↦→ v0). The set of 

all valuations is denoted by Σ. The set Ch of all channels

and the set S of all sensitivity lists with clocks may be used 

in SystemC FL processes that are assumed. 

Notice that the above proposed data types are the fundamental 

ones. Several extensions of data types (e.g. “sc bit” and 

“sc logic”) were already introduced in [6]. 

2. 2 Syntax of the SystemC FL Language 

A process term P in SystemC FL is built from atomic process 

terms AP. SystemC FL consists of various operators that operate 

on process terms, and it is defined according to the following 

grammar: 


AP ::= δ | skip | x := e | ∆en | ≫ 

P ::= AP | P ◭ b ◮ P | b � P | P • P | P ΘP 

P △d P | P � d P | ∗P | P || P | P || ℓ P 

P ∼ P | ∂H(P ) | τI(P ) | π(P ) | �(P ) 

Υ � P 

The operators are listed in descending order of their binding 

strength as follows : {�, •, △, �, ∗}, {◭◮, Θ, ||, || ℓ , ∼ 

}, {∂, τ, π, �, �}. The operators inside the braces have equal 

binding strength. In addition, operators of equal binding 

strength associate to the left, and parentheses may be used to 

group expressions. 

Below is a brief introduction of the formal language 

SystemC FL . The formal semantics of SystemC FL is given 

in Subsection 2. 3. Due to limitation of pages, deduction rules 

for operational semantics of SystemC FL are not given in this 

paper. For those interested in more details, please read [2] and 

[8]. 

SystemC FL has the atomic process terms and operators as 

follows. The deadlock δ is introduced as a constant, which 

represents no behavior. The skip process term performs the internal 

action τ, which is not externally visible. The assignment 

process term x := e, which assigns the value of expression e 

to x (modeling a SystemC “assignment” statement). The delay 

process term ∆en is able to delay the value of numerical expression 

en. The unbounded delay process term ≫ (modeling 

a SystemC “wait” statement) may delay for a long time that is 

unbounded or perform the internal action τ. 

The conditional composition p ◭ b ◮ q operates as a SystemC 

“then if else” statement, where b denotes a boolean expression 

and p, q ∈ P . The watching process term b � p is 

used to model a SystemC “watching” statement. The sequential 

composition p • q models the process term that behaves as p, 

and upon termination of p, continues to behave as process term 

q. The alternative composition pΘq models a non-deterministic 

choice between process terms p and q. 

The timeout process term p △d q (modeling a SystemC 

“time out” construct) behaves as p if p performs a time transition 

before a time d ∈ R>0. Otherwise, it behaves as q. The 

watchdog process term p� d q behaves as p during a period of 

time less than d, at time d, q takes over the execution from p in 

p� d q. If p performs an internal cancel χ action, then the delay 

is canceled, and the subsequent behavior is that of p after χ is 

executed. The repetition process term ∗p (modeling a SystemC 

“loop” construct) executes p zero or more times. 

The parallel composition p || q, the left-parallel composition 

p || ℓ q and the communication composition p ∼ q are used 

to express parallelism (actions are executed in an interleaving 

120 

manner, with the possibility of communication of actions). The 

encapsulation of actions is allowed using ∂H(p), where H represents 

the set of all actions to be blocked in p. The abstraction 

τI(p) behaves as the process term p, except that all action 

names in I are renamed to the internal action τ. The maximal 

progress π(p) assigns action transitions a higher priority 

over time transitions. This operator is needed to establish a desired 

communication behavior. That is, both the sender and the 

receiver must be able to perform time transitions, but if two of 

these can communicate (i.e. performing action transitions), they 

should not perform time transitions. 

The grouping of actions and executing them in one step can 

be done by using �(p). This is defined for the translation from 

SystemC FL to PROMELA (see also [15]). The signal emission 

operator Υ � p requires that the predicate Υ always holds. 

If it is the case, Υ � p behaves like p. Otherwise, it is a δ. 

This operator is newly introduced. It is needed for defining 

user-friendly syntax and the translation from SystemC FL to 

the SMV language (see also [16]). 

Informal semantics of SystemC states that SystemC incorporates 

both point-to-point communication and multi-party communication 

mechanisms for the interaction between concurrent 

processes. However, there are no statements in SystemC for 

modeling these communication mechanisms. In order to capture 

the same communication behaviors between concurrent 

processes in SystemC FL , operators ||, || ℓ , ∼, ∂H, τI, and π 

are introduced to give formal specification for point-to-point 

communication and multi-party communication between concurrent 

SystemC FL processes. 

2. 3 Semantics of the 

SystemC FL Language 

Definition 1 A SystemC FL process is a quintuple 

〈P, Σ, Σ, S, Ch〉. We use the convention 〈p, σ ′ , σ, s, m〉 

to write a SystemC FL process, where p is a process term; 

σ, σ ′ are valuations; s is a sensitivity list with clocks; and m is 

a channel. 

Definition 2 The set of actions Aτ contains at least aa(x,v),χ 

and τ, where aa(x, v) is the assignment action (i.e. the value 

of v is assigned to x), χ is the internal cancel action and τ is 

the internal action. The set Aτ is considered as a parameter of 

SystemC FL and can be freely instantiated. 

Definition 3 We give a formal semantics for 

SystemC FL processes in terms of a Labelled Transition 

System (LTS), and define the following transition relations on 

processes of SystemC FL : 

• −→ ⊆ (P × Σ × Σ × S × Ch) × Aτ × (P × Σ × Σ × 

S × Ch), denotes action transition; 

• −→ 〈�, , , , 〉 ⊆ (P × Σ × Σ × S × Ch) × Aτ × (Σ × 

Σ × S × Ch), denotes termination, where � is used to 

indicate a successful termination, and � is not a process 

term; 

• � ⊆ (P × Σ × Σ × S × Ch) × R>0 × (P × Σ × 

Σ × S × Ch), denotes time transition (so-called delay). 

The three kinds of transition relations can be explained 

as follows. Firstly, an action transition 〈p, σ ′ , σ, s, m〉 a −→

〈p ′ , σ, σ ′′ , s, m〉 is that the process 〈p, σ ′ , σ, s, m〉 executes 

the action a ∈ Aτ starting with the current valuation σ (at the 

moment of the transition taking place) and by this execution p 

evolves into p ′ . Notice that σ ′ represents the previous accompanying 

valuation of the process, and σ ′′ represents the accompanying 

valuation of the process after the action a is executed. 

Secondly, a termination 〈p, σ ′ , σ, s, m〉 a −→ 〈�, σ, σ ′′ , s, m〉 is 

that the process executes the action a followed by termination. 

Thirdly, a time transition 〈p, σ ′ , σ, s, m〉 d � 〈p ′ , σ, σ ′′ , s, m〉 is 

that the process 〈p, σ ′ , σ, s, m〉 may idle during a time d and 

then behaves like 〈p ′ , σ, σ ′′ , s, m〉. 

Two valuations (e.g. previous accompanying valuation and 

current valuation) are defined (as arguments) in the quintuple, 

so that the change of the valuation of variables in the sensitivity 

list of the quintuple can be observed. This is needed for defining 

the deduction rules of some SystemC FL operators (e.g. the 

watching �). 

Notice that modeling designs with the syntax presented in 

Subsection 2. 2 may not be straightforward and intuitive for 

users not having a computer science background. Therefore, in 

[16], we defined an user-friendly syntax in SystemC FL . 


3. CASE STUDIES 

Some complex case studies (memory, synchronous D flip 

flop and remote procedure call (RPC) protocol) of the application 

of SystemC FL to model and to perform analysis of 

SystemC FL designs already appeared in [6]. For illustration 

purpose, in this section, we only give a simple case study: 

counter and test-bench to show how SystemC FL can be put 

to practical use to model the fundamental SystemC processes. 

3. 1 Method process 

When events occur on signals that a process is sensitive to, then 

the process executes. Below is an example (written in SystemC 

code) that implements an integer counter. 

// count.h 

# include ’’systemc.h’’ 

SC_MODULE(count) { 

sc_in load; 

sc_in din; 

sc_in clock; 

sc_out dout; 

int count_val; 

void count_up(); 

SC_CTOR(count) { 

SC_METHOD(count_up); 

sensitive_pos

where σ ′ , σ and s are defined as in Subsection 3. 1. 

If Condclock evaluates to true, the outermost � process term 

executes. Then the innermost � process term executes also. 

First the value 0 and true are assigned to din and load respectively, 

then performs some delay. After that, false is assigned 

to load and performs some other delay. 

Since processes (counter and test-bench) execute concurrently, 

the parallel composition operator is used to model the 

complete system. The complete system is modeled as follows: 

〈Condclock (σ ′ , σ, s) � (((countval := din ◭ load ◮ 

countval := countval + 1) • dout := countval) || (true � 

(load := true • din := 0 • ≫ • load := false • ≫ 

))), σ ′ , σ, s〉 for some σ ′ , σ, s (are defined as before). 

4. KEY FEATURES AND RESULTS 

This section presents some key features and results of 

SystemC FL . 

A key feature of SystemC FL is to have a single-formalism 

that can be used to describe various systems. Another 

key feature is that formal SystemC FL specifications can be 

purportedly used for formal verification. Analysis/formal 

verification takes place by extracting simpler designs from 

SystemC FL designs that are tailored to some specific properties 

of interest. Moreover, it can be specifically used for specifying 

concurrent systems, finite state systems and real-time systems. 

Desired properties of these systems/designs modeled in 

SystemC FL can be verified with existing formal verification 

tools (from free-public domain) by translating them formally 

into different formalisms that are the input languages of the existing 

formal verification tools. 

For instance, [15] reported that safety properties of concurrent 

systems modeled in SystemC FL that can be verified by 

translating them to PROMELA that is the input language of 

the SPIN Model Checker. Similarly, safety and liveness properties 

of finite state systems described in SystemC FL can be 

fed into the SMV [12] Model Checker to verify them (reported 

in [16]). Also, a formal translation was defined in [7] from 

SystemC FL to a variant (with very general settings) of timed 

automata [13]. The practical benefit of the formal translation 

from a SystemC FL design (modeling real-time systems) to a 

timed automaton is to enable verification of properties of realtime 

systems described in SystemC FL using existing verification 

tools for timed automata, such as Uppaal [14]. 

5. CONCLUDING REMARKS 

In this paper, we have presented the main aspects of the current 

status of the formal language SystemC FL . Then, we have 

illustrated the use of the SystemC FL through some case studies 

taken literature. We have also shown some key features and 

results of SystemC FL . 

Our future works will focus on defining the formal semantics 

(also in SOS style) in SystemC FL for modeling mixed-signal 

designs. This semantics intends to support the development of 

system-level analog and mixed-signal specifications, and will 

be a conservative extension to the existing SystemC FL . 

We hope that SystemC FL will also be widely used by the 

chip designers and verification engineers in electronic commu- 


122 

nity to give specifications and analysis of SystemC designs and 

various systems. 

6. REFERENCES 

[1] “SystemC User’s Guide and SystemC Language 

Reference Manual (version 2.0),” are available at 

(http://www.systemc.org). 

[2] K.L. Man, “SystemC FL : Formalization of SystemC,” in 

IEEE Proceedings of the 12th Mediterranean Electrotechnical 

Conference - IEEE/MELECON 2004, Dubrovnik, Croatia, 

Vol. 1, pp. 201-204, May, 2004. 

[3] J.C.M. Baeten, W.P. Weijland, “Process Algebra,” Number 

18 in Cambridge Tracts in Theoretical Computer Science, 

Cambridge University Press, 1990. 

[4] Gordon D. Plotkin, “A Structural Approach to Operational 

Semantics,” Report DAIMI FN-19, Computer Science Department, 

Aarhus University, 1981. 

[5] Luca Aceto, Wan Fokkink, Chris Verhoef. “Structural Operational 

Semantics”. In Bergstra et al. BPS01, pp. 197-292, 

1999. 

[6] K.L. Man, “Modeling with the Formal Language of SystemC 

: Case Studies,” in Proceedings of the 11th International 

Conference Mixed Design of Integrated Circuits and 

Systems - IEEE/MIXDES 2004, Szczecin, Poland, pp. 407- 

411, June, 2004. 

[7] K.L. Man, “Analyzing SystemC FL Designs Using Timed 

Automata,” in INSPEC IEE Proceedings of the 9th Baltic 

Electronics Conference - IEEE/BEC 2004, Tallinn, Estonia, 

pp. 155-158, October, 2004. 

[8] K.L. Man, “The Formal Communication Semantics of 

SystemC FL ,” to appear in IEEE Proceedings of the 8th Euromicro 

Conference on Digital System Design - IEEE/DSD 

2005, Porto, Portugal, September, 2004. 

[9] W. Mueller, J.Ruf, D. Hofmann, J. Gerlach, T. Kropf, 

W.Rosenstiehl. “The Simulation Semantics of SystemC,” in 

Proceedings of DATE, 2001. 

[10] Ashraf Salem. “Formal Semantics of Synchronous SystemC,” 

in Proceedings of DATE, 2003. 

[11] G. J. Holzmann, The SPIN Model Checker, Addison- 

Wesley, 2003. 

[12] The SMV model checker is available at http://www- 

2.cs.cmu.edu/ modelcheck/. 

[13] R. Alur, D.L. Dill, “A Theory of Timed Automata,” Theoretical 

Computer Science, Vol. 126, No. 2, pp. 183-236, 

April, 1994. 

[14] Kim G. Larsen, Paul Pettersson, Wang Yi, “UPPAAL in a 

Nutshell,” Journal of Software Tools for Technology Transfer 

(STTT), Vol 1, No. 1-2, pp. 134–152, 1997. 

[15] K.L. Man, “Formal Verification of SystemC FL Designs 

Using the SPIN Model Checker,” unpublished, March 2005. 

[16] K.L. Man, “ Verifying SystemC FL Designs Using the 

SMV Model Checker,” in Proceedings of the 8th IEEE 

Workshop on Design and Diagnostics of Electronic Circuits 

and Systems - IEEE/DDECS 2005, Sopron, Hungary, pp. 

244-247, April, 2005.


A 600mV 1.32mW 75dB-DR 4 th -order Baseband Analog Filter 

for UMTS Receivers 

M. De Matteis (Ph.D. Student) , S. D’Amico (Ph.D. Student) , A. Baschirotto 

Department of Innovation Engineering 

University of Lecce, Italy 

Email: marcello.dematteis@unile.it, stefano.damico@unile.it, andrea.baschirotto@unile.it 

ABSTRACT 

In this paper a 600mV supply voltage 4 th order lowpass 

analog filter for UMTS receivers is presented. 

The filter is designed using two 2 nd order filtering 

stages based on biquadratic cells, where a suitable level 

shifter allows to achieve rail-to-rail input and output 

swing, while operating at a supply voltage of Vth+3Vov. 

From a single 600mV supply voltage in a CMOS 

0.13µm technology the single-ended analog filter 

features a THD=-49dB for a 480mVpp output signal 

amplitude. 


Low-voltage and low-power issues are more and 

more important in the design and realization of 

portable terminals. 

The state-of-the-art is operating at 1.8V, while 

research activities are designing blocks and complete 

transceiver operating with a power supply of 1.2V or 

lower [1]. This trend is also due to the lower supply 

voltage, which can be sustained by the scaled CMOS 

technology. 

In this paper the design of the analog base-band filter 

is addressed. This block appears stringent since at this 

level of the receiver chain the signal has been amplified 

and so large linear range has to be guarantee. 

For this design the case of the UMTS has been 

develop, with reference to the front-end designed in 

[2]. In this case, the receiver requires a 4 th -order 

Butterworth low-pass filter whose transfer function 

parameters are given in Table I. 

Table I. LP Filter Transfer Function 

Cell 1 Cell2 

f-3db 2. 11MHz 2. 11MHz 

Adc 

Q 

(quality factor) 

16dB 16dB 

1.3 0.5411 

The stringent requirements on noise 

(IRN

In order to reduce the VDDmin, the current source 

made up by MB has been added. This current source 

(together with the control loop with the low-pass filter) 

allows to fix VoutDC=VDD/2. 

As a consequence, the virtual ground principle forces 

to have Vopamp_inDC=VB, which is fixed to be 

VB=Vov=200mV, i.e. the MB saturation/overdrive 

voltage. It follows that: 

VDDmin=Vov+VGSinputpair+Vsat_currentsource=Vth+3Vov (6) 

which is much lower that VDDmin in (5). 

So to fix the DC voltage at the opamp negative input, 

a biasing circuit has been added. This control loop 

circuit acts only at very low frequencies, in fact the RC 

pair in the control-loop places a zero at the DC and a 

pole at low frequency (2KHz). 

The filter input signal is a wide band input signal 

(approximately 2Mhz), so when the control loop circuit 

acts as high pass filter there are no significant 

performances degradations in the receiver. 

But there is another aspect which has been 

considered with the control loop circuit. 

In the UMTS receivers the input signal filter is 

usually a base band signal, which includes the zero 

frequency. This can cause many problems in terms of 

offset voltage. 

The natural solution is to implement a high-pass 

filter with a cut-off frequency around the KHz. In the 

filter presented in this paper the control-loop has been 

designed to place the zero-pole pair to cut off the 

frequencies until a few KHz. 

The control loop pole position in the frequency 

domain depends on: 

1- the dc gain control loop opamp (Adc_loopOPAMP); 

2- the MOSFET MB transconductance (gm) ; 

3- the feedback resistance (Rf) ; 

4- the RC constant time value. 

In order to minimize the RC value it has been used a 

unity gain configuration opamp in the control loop. So 

the pole frequency is: 

flow_frequency=(1-Gloop)(1/2πRC) 

where Gloop=-gmAdc_loopOPAMPRf . 

These additional singularities in the overall 

frequency allow to relax the front-end dc-offset 

performance without a significant signal degradation 

[3]. 

In the following design in a 0.13µm CMOS 

technology, the Vth is around 300mV. Using 

Vov=90mV, the safe value of VDDmin=600mV is used in 

order to guarantee the target performance for any 

temperature, aging, and technological (worst case) 

spread. 


124 

V inDC 

R 1 

C 1 

R f 

R 2 

M B 

V B 

C L 

_ 

+ 

R L 

C 2 

Figure 1. LV Biquadratic cell 

_ 

+ 

V O 

V outDC 

2.1 Low Voltage Operational Amplifier 

The opamp to be embedded in the multi-path cell of 

Figure 1 is shown in Figure 2 [4]. It has to satisfy the 

low-voltage requirements, as described in the previous 

section, in addition to frequency response, noise and 

linearity requirements as required by the UMTS 

application. 

The opamp is composed of two gain stages. The first 

gain stage is composed of a differential P-MOS pair 

(M1 and M2) and a N-MOS pair used as a current 

mirror (M3 and M4) to implement the “differential-tosingle 

ended” transformation. The second stage is a 

Common Source (M12-M11) stage to maximize the 

output swing. Between the two gain stages, there are 

M8 and M5 transistors. M5 is used as a cascode device 

to fix the VDSM4. 

The opamp UGBW is designed to be about 100 

times higher that the filter cut-off frequency in order to 

reduce the effects of its lag on the filter frequency 

response. The opamp input-refered noise reaches the 

output with a gain equal to 2 and it has been 

consequently kept low (up to 3nV/√Hz) in order to 

make it negligible respect to the other noise 

contributions. 

Table II. LP Filter Transfer Function 

Power supply 600mV 

Current consumption 1.1mA 

UGBW 200MHz 

Adc 

60dB 

IRN 3nV/√Hz 

Phase Margin 60°

Figure 2. Low Voltage OPAMP Structure 


The 4 th order filter had been designed using a 

0.13µm standard CMOS technology, with 

VTH≈300mV. The filter is designed to operate with 

VDD=600mV. A single-ended implementation is used 

since it is sufficient for demonstrate the low-voltage 

design approach. 

On the other hand the linearity performance given in 

the following may validate such a design approach. Of 

course a performance improvement is expected with a 

fully-differential implementation. 

The values of the capacitors and resistors (given in 

Table) have been calculated with a MATLAB 

procedure, in order to satisfy the frequency response, 

the noise and the linearity requirements. The noise of 

the 1 st cell is dominated by the thermal noise of R1 and 

R2. On the other hand, due to the large gain of the 1 st 

cell, the noise of the 2 nd cell is relaxed, and then the 

resistors can be larger. The overall filter transfer 

function is given in agreement with the specifications. 


Table III. Component Sizes 

Cell 1 Cell 2 

C1 [pF] 62.9 5.9 

C2 [pF] 1.25 0.64 

R1[kΩ] 3.46 12.7 

R2 [kΩ] 3.29 19 

Rf [kΩ] 21.8 80 

The linearity performance is reported in the next 

figure. A large linearity performance is achieved, in 

fact a THD=-46dB is obtained for a 480mVpp 

sinewave, i.e 50mV close to the rail. 

In Table IV, the proposed filter is compared to an 

important example from the literature [1]. 

125 


In this paper a 600mV continuous-time filter is 

proposed to be embedded in a UMTS receiver. The 

filter presents a multi-path active-RC structure, with a 

voltage level shift which allows to optimally bias the 

structure. This allows to operate the design with a 

VDDmin=Vth+3·Vov and to guarantee rail-to-rail output 

swing. Using a single-ended implementation, the THD 

is -49dB for a 480mVpp output signal swing. This 

demonstrates the validity of this design approach, 

which may be extended to the fully-differential 

implementation 

Table IV - Filter Performance Summary 

This Design [1] 

VDD [V] 0.6 0.6 

Technology 

[µm] 

0.13 CMOS 0.18 CMOS 

VTH [mV] 300 

Current 

Consumption 

[mA] 

2.2 4.3 

Power 

Consumption 

[mW] 

1.32 2.58 

Filter order 4 th 

5 th 

f-3db [MHz] 2.11MHz 135KHz 

Adc [dB] 32dB 0 

IRN 

[nV/√Hz] 

17 30 

THD [dB] -49@170mVrms -50@50mVrms 

In Band IRN 30 

[µVrms] 

65 

DR 

[dB] 

75@THD=-49dB 58@THD=-50dB 

Magnitude (dB) 

40 

30 

20 

10 

0 

-10 

-20 

-30 

-40 

10 3 

10 4 

10 5 

Frequency (Hz) 

10 6 

Figure 3. Filter frequency response 

10 7

Figure 4. Filter HD2 and HD3 vs. output 

signal amplitude 


Reference 

[1] S. Chatterjee, Y. Tsividis, P. Kinget, “A 0.5V 

Filter with PLL-Based Tuning in 0.18µm 

CMOS”, Proceedings of ISSCC 2005 

[2] D. Mastretta, R. Castello, F. Gatta, P. Rossi and F. 

Svelto “A 0.18 µm CMOS Direct-Conversion 

Receiver Front-End for UMTS”, Proceedings of 

ISSCC 2002 

[3] A. Springer, L. Maurer, and R. Weigel, RF System 

Concepts for highly Integrated RFICs for W- 

CDMA Mobile Radio Terminals”, IEEE Trans. 

On Microwave Theory and Techniques, Jan. 

2002 

[4] A. Baschirotto, R. Castello, "A 1V 1.8MHz CMOS 

Switched-opamp SC filter with rail-to-rail 

output swing", IEEE J. of Solid State Circuits - 

December 1997 - pag. 1979-1986 

126


A 2.45 GHz Remotely Powered RFID System 

Jari-Pascal Curty, Norbert Joehl, Catherine Dehollain, Michel Declercq 

Laboratoire d’électronique générale, STI/IMM/LEG, 

Ecole Polytechnique Fédérale de Lausanne, Switzerland 

E-mail: jari.curty@epfl.ch 

ABSTRACT 

This paper presents a fully integrated remotely powered 

and addressable Radio Frequency IDentification (RFID) 

transponder working at 2.45 GHz. The achieved operating 

range at 4 W Effective Isotropically Radiated Power 

(EIRP) base-station transmit power is 12 m. The Integrated 

Circuit (IC) is implemented in a 0.5 µm siliconon-sapphire 

technology. A state of the art rectifier design 

achieving 37% of global efficiency is embedded to supply 

energy to the transponder. The necessary input power 

to operate the transponder is about 2.7 µW. 

1. Introduction 

The IC presented in this article offers a solution in terms 

of performances for long range RFID applications. A 

reading distance of 12 m has been achieved using stateof-the-art 

IC design and antenna techniques. Today’s 

existing RFID technology at 2.45 GHz are available in [1], 

[2], [3]. 

Reader 

Power + ID of transponder B 

Data from transponder B 

Transponder 

C 

Transponder 

A 

Transponder 

B 

 

Modulator 

Rectifier 

+ 

Limiter 

Figure 1: Operational principle. 

V+ V- 

Detection 

+ 

Logic 

The general application framework is described in 

Fig. 1. The concept is to address a group of hardcoded 

passive transponders in order to wake up only 

one of them. The reader sends an N-bit address (ID) 

and only the transponder that contains this ID wakes 

up. All others switch into quiet mode. If a transponder 

with the emitted ID is found, it starts modulating 

its input impedance to enable backscattering communication 

with the reader. The latter can then verify the 

transponder’s ID to check if it matches the one sent. Ev- 

127 

ery step in a communication session is reader controlled. 

Transponders which retrieve their operating power from 

the reader’s transmitted energy thus operate in a masterslave 

configuration. 

2. Transponder description 

Rectifier 

+ 

Limiter 

Data Slicer 

V+ V- 

IF 

Oscillator 

V- 

V+ V+ 

V+ 

CV+ 

CV- 

Power on 

reset 

V- V- 

V+ 

Shift Reg. 

& Logic 

Figure 2: System architecture. 

Due to tight power constraints, the number of building 

blocks and their complexity are limited. The reader-tag 

communication link is implemented using a tiny pulsewidth 

demodulator. The backscattering technique [4] is 

used to enable the tag-reader communication link. Because 

of the 1/f noise that occurs, the tag data are modulated 

at an Intermediate Frequency (IF) rate. The IF 

frequency is generated by a typical relaxation oscillator 

structure. The latter is technology dependant and the 

frequency obtained may vary from die to die. One could 

solve this issue by using a calibration technique at the 

cost of a larger protocol preamble and a higher circuit 

complexity. Another possibility is to use a large IF bandwidth 

filter at the reader side, but the sensitivity of the 

system will be affected because of the noise level. Our 

approach is to develop a solution based on the architecture 

shown in Fig. 3 The IF bandwidth of the loop is 

V-

IF 


LNA Mixer Bandpass 

VCO, fC 

A 

D 

µC 

RSSI 

Figure 3: IF demodulation architecture. 

kept to a minimum that ensures the desired datarate. 

The micro-controller sweeps the voltage-controlled oscillator 

frequency fC between fC and fC +(IFmax − IFmin) 

until the Received Signal Strength Indicator (RSSI) circuit 

detects some signal power located at the tag’s IF 

frequency. 

3. Rectifier issues 

The rectifier is a key block in every remotely powered 

system. A typical two stage modified-Greinacher structure 

is shown in Fig. 4. The use of low threshold voltage 

and low reverse current diodes and capacitors makes it 

possible to obtain a relatively high output voltage (1-2 V) 

given a sinusoidal input signal of about 200 mV. These 

values depend on the received power, the DC output current 

delivered to the load, and the impedance matching 

quality between the antenna and the rectifier’s input. 

vin 

C1 

C ′ 

1 

D1 

D2 

D ′ 

1 

D ′ 

2 

C2 

C ′ 

2 

Stage 1 

D 

Stage 2 

A 

Cout 

Cout 

Vout 

Figure 4: 2-stage modified-Greinacher full-wave 

rectifier. 

A thorough study is available in a preceding article 

[5, 6] in which the circuit of Fig. 5 models the rectifier 

fabricated in a given technology as an input and output 

impedance as well as a voltage controlled voltage source. 

The model allows the prediction of the power needed to 

supply a given DC output current at a constant output 

DC voltage. Furthermore, it provides the rectifier input 

and output impedance. If the input capacitance Cin is 

128 

inductively compensated, the input voltage amplitude �vin 

is equal to 

�vin =2 √ Rin 

2PAVRant 

(1) 

Rin + Rant 

where PAV is the available power from the antenna and 

Rant is its impedance real part. From Eq. (1), it is clear 

that to increase �vin, one has to increase Rant while simultaneously 

keeping Rin = Rant, i.e. power match. This 

is necessary in order to increase the performances of the 

rectifier. 

vin Rin Cin 

V0 

Rout 

Vout 

Figure 5: Equivalent circuit for the rectifier. 

Based on [5, 6], the minimal input power for a 3 stage 

rectifier with a 300 Ω radiation resistance antenna is 

equal to -16 dBm for an output current consumption of 

1 µA. This power value could be reduced with better 

antenna-tag impedance matching. 

4. Modulator issues 

The backscattering modulation technique is based on the 

variation of the reflection coefficient Γ at the input of a 

transponder. The power part being reflected enables tagto-reader 

communication. Γ can vary either in amplitude 

or in phase. As a result, two modulation types are possible: 

ASK (AM) and PSK (PM). 

The modulation type choice is a strict trade-off between 

the power dedicated to the tag operations and 

power devoted to the communication. In ASK, the modulator 

switches the input impedance between a matched 

state and a reflection state, wheras in PSK, it switches 

the impedance reactive part seen by the antenna between 

two complex conjugate values. The available power to 

the tag is thus kept constant during the PSK modulation 

states. This could be seen as an advantage of PSK 

over ASK but, it can be shown that there exists an optimum 

for both modulation in terms of Bit Error Rate 

(BER), average available power and voltage amplitude 

at the tag input. In this case, the PSK is only 0.74 dB 

superior to ASK (see Fig. 6), the average power available 

to the tag is 50% of the received power for both types and 

the input voltage amplitude is more than twice better in 

ASK but only during one modulation state (since in the 

other state, the rectifier input is shorted). In the circuit 

of this article, an ASK modulation type is used. It is 

implemented with the help of a simple analog switch. 

5. Antenna issues 

The transponder input impedance is mainly influenced 

by the rectifier. Its impedance is composed of an imag-

BER 

10 0 

10 −1 

10 −2 

10 −3 

10 −4 

10 −5 

10 −6 

−1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 

Eb dB 

N0 0-7803-9345-7/05/$20.00©2005 IEEE. 

0 5 10 15 

Optimal backscattering PSK 

Optimal backscattering ASK 

Standard PSK 

Figure 6: Optimal ASK and PSK BER comparison. 

inary part due to the parasitic capacitances and a real 

part that depends on the output current consumption. 

The other blocks of the RF front-end (the detector and 

the modulator) bring a small contribution (for the ASK 

case). 

Antenna 

R ant 

Vs C R Vs L C R 

Transponder 

Antenna 

R ant 

Inductive 

matching 

Transponder 

Figure 7: Impedance matching for the transponder. 

At low received power, inductive matching can be 

added to resonate with capacitance C (see Fig. 7). In 

this case, optimum power transfer between the antenna 

radiation resistance Rant and the input resistance R is 

achieved if they are both equal. As a result, the global 

efficiency of the RF front-end increases. The inductance 

can be realized in conjunction with the antenna design 

with no added cost in terms of fabrication. 

In section 6. , the operating ranges for a transponder 

with and without inductive matching (see Table 2) for 

different antenna types are compared. 

There are several types of antennas that can be used 

with a high frequency transponder. The choice is closely 

related to the target application [7]. Patch antennas are 

well suited for metallic objects since it is possible to make 

use of their bodies as a ground plane. Other types of materials, 

e.g. wood, cardboard, etc. also allow differential 

antennas. These antennas offer the advantages of higher 

radiation resistance compared to single-ended versions, 

and of less capacitive losses. As shown in [5], [6], higher 

radiation resistance is desirable. For the circuit of this 

particular article an impedance level of 300 Ω offered the 

best results in terms of operating range. 

129 

6. Experimental results 

A version of the circuit has been realized in a fully depleted 

silicon on sapphire technology [8]. This competitive 

process offers low threshold voltage CMOS transistors 

that is a clear advantage for remotely powered 

devices[9]. The isolated devices present a low parasitic 

capacitance compared to a standard bulk process. The 

input impedance in the absorptive state is shown in Table 

1. The model presented in [5] predicted electrical 

Table 1: Input admittance measurement at 

2.45 GHz. 

Freq. GHz RkΩ CfF Vout V Iout µA 

2.45 3.4 500 1 1 

parameters (input impedance, efficiency, etc.) that were 

in excellent agreement with on-wafer measurements. The 

layout of the RF front-end has to be done with particular 

care, i.e. parasitic capacitances should be minimized. 

Extracted layout simulation is essential in order to estimate 

and reduce parasitics that are directly connected 

to the antenna. 

A complete transponder is shown in Fig. 9. The antenna 

is optimized for 2.45 GHz. Its radiation resistance 

is approximately 300 Ω. 

Figure 8: Die micro-photograph (size: 

400 µm×550 µm without the test pads). 

The measured operating ranges at 2.45 GHz are summarized 

in Table 2. Results show a clear advantage for 

the folded dipole antenna with inductive matching. In 

this particular case, the path loss at 12 m is 124 dB. 

With an emitted power of 36 dBm and no losses coming 

from the transponder, the backscattered power returning 

to the emitting antenna is equal to -88 dBm. The 

measured power at the receiving antenna is equal to - 

92 dBm. The losses due to the tag antenna mismatch 

are thus equal to 4 dB. In the case of the folded dipole 

without inductive compensation, those losses were equal 

to 14 dB.

Table 2: Operating range for different antenna types 


Freq. MHz Antenna Range m 

2450 λ/2-dipole 

λ/2-dipole with 

6 

2450 

inductive 


9 

2450 folded dipole 

folded dipole 

7 

2450 with inductive 


12 

The power impinging the transponder antenna (2 dB 

gain) at 12 m is equal to -25.7 dBm, i.e. about 2.7 µW. 

With a 300 Ω radiation resistance antenna, the equivalent 

voltage source amplitude is 80 mV. With an input 

impedance after inductive matching of 3.4 kΩ, the input 

RF voltage amplitude is 73.5 mV and the output 

DC voltage of the rectifier reaches 882 mV (multiplication 

factor of 12 for the present rectifier structure). The 

transponder sensitivity is thus 73.5 mV or -25.7 dBm on 

a 300 Ω antenna. Finally, the global efficiency of the 

rectifier in this extreme case is about 37% (considering 

1 µW of ouptut power). 

Figure 9: Picture of the complete 2.45 GHz 

transponder. 

The distance could be increased by using a smaller 

operating frequency, e.g. 900 MHz. In this case, the 

achievable distance can be more than doubled. 

7. Conclusion 

This paper presents a remotely powered addressable 

UHF RFID system. Using state of the art analysis 

and design techniques, a SOS 0.5-µm CMOS technology 

and inductive matching between the antenna and 

the transponder, an operating range of 12 m with 4 W 

EIRP transmitted power was achieved. At this distance, 

the available power for the transponder is 2.7 µW which 

means about 37% global efficiency for the rectifier since 

the estimated (simulation) power consumption of the 

whole system is approximately 1 µW. 

As shown in this article, the system complexity is 

principally on the reader side (master-slave architecture). 

The available functions on the tag side are 

kept to a minimum with the goal of ultra-low power 

consumption. However, if a higher amount of power 

is necessary for a given application, this circuit is 

still usable at the cost of a smaller operating range. 

130 

Table 3: Operating range for 4 W EIRP at 

2.45 GHz RFID systems. 

Range 

Mod. 

a 

type 

Process Reference 

0.4 m ASk 

0.18 µm 

CMOS 

[2] 

1.8 m n/a n/a [3] 

2.6 m b 

PSK 

0.5 µm 

CMOS + 

Shottky 

[1] 

12 m ASK 0.5 µm SOS This work 

a 

Tag-reader modulation. 

b 

Calculated value 

This paper also presents in conjunction with [5] the 

trade-offs that occur for remotely powered systems. Using 

silicon-on-sapphire in conjuction with state-of-theart 

RF design allowed us to reach an operating range of 

12 m. This is an important improvement compared with 

the available technologies today [1], [2], [3] (see Table 3). 

8. REFERENCES 

[1] U. Karthaus and M. Fischer, ”Fully integrated passive 

UHF RFID transponder IC with 16.7 µW minimum 

RF input power”, IEEE Journalof Solid-State 

Circuits, vol. 38, no. 10, pp. 1602-1608, October 2003. 

[2] “Hitachi µchip product”, 2004, 

http://www.hitachi-eu.com/mu 

[3] “Philips uCode product”, 2004, 

http://www.semiconductors.philips.com/markets/←↪ 

identification/products/ucode/index.html 

[4] K. Finkenzeller, ”RFID handbook, Radio-Frequency 

Identifications Fundamentals and Applications”, 2nd 

edition, Wiley, 2003, ISBN 0-470-84402-7. 

[5] J.-P. Curty et Al., ”A model for µ-powered rectifier 

analysis and design”, To be published in IEEE Transactions 

on Circuits and Systems I. 

[6] J. P. Curty, ”A web interface for diode 

rectification ability evaluation”, 2004, 

http://legwww.epfl.ch/direct 

[7] P. R. Foster and R. A. Burberry, ”Antenna problems 

in RFID systems”, IEE Colloquium on RFID technology, 

no. 1999/123, pp. 3/1-3/5, 25 Oct. 1999. 

[8] J. C. S. Woo, ”High performance silicon on sapphire 

technology”, 1998, 

http://www.ucop.edu/research/←↪ 

micro/98-98/97 208.pdf 

[9] “UTSi Process Advantages”, 2004, 

http://www.peregrine-semi.com.au/←↪ 

Process/UTSIProcess2.html


A 0.13µm CMOS VGA FOR MULTISTANDARD 

RECEIVERS 

S. D’Amico (Ph.D. Student) , V. Chironi, A. Baschirotto 

Department of Innovation Engineering 

University of Lecce, Italy 

E-mail: stefano.damico@unile.it, vchironi@email.it, andrea.baschirotto@unile.it 

ABSTRACT 

A fully balanced variable gain amplifier (VGA) in 

0.13µm CMOS technology to be used in a 

multistandard receivers (WLAN, UMTS, GSM, and 

Bluetooth) is reported. The overall architecture 

where the VGA is emebedded presents considerable 

different requirements (bandwidth, dc-gain, and 

common mode input voltage) for the four telecom 

standards to be processed. The VGA features 4 gain 

steps with a IIP3 better than 30dBm and an inputreferred 

noise voltage lower than 5nV/√Hz at 0dB 

dc-gain. 


Reconfigurable wireless systems (multistandard 

terminals) identify a new wireless technology with 

a great research and market interest. These 

equipments will allow the transceiver 

reconfigurability to process different telecom 

standards for wireless technologies, like: 802.11.x 

WLAN and Bluetooth (indoor), and GSM,UMTS 

(outdoor). This approach allows sharing the same 

circuital blocks for all the selected standards. Fig.1 

shows the architecture of a reconfigurable receiver 

under development by the Italian Research Project 

FIRB [1]-[2]. In this scheme the VGA (marked as 

VGA1) links the two GSM/UMTS and 

WLAN/Bluetooth RF receive-chains. These two RF 

channels present different characteristics (i.e supply 

voltage, dc-gain, and bandwidth). Thus the VGA 

has to process different features for the selected 

standards [3]-[4], as reported in Table I for the most 

critical cases. 

131 

Fig. 1 - Reconconfigurable Receiever architecture 

In this paper a circuit solution for the VGA designed 

in a 0.13µm CMOS technology is proposed. 

2. CIRCUIT PRINCIPLE AND 

DESIGN 

The schematic of the designed VGA is shown in 

Fig. 2. It uses an open-loop structure, which consists 

of a V-I converter (input opamps, M1-M2, and Rdeg), 

a resistive load (RL) and an output level shifter (M7- 

M8). Such an open-loop structure allows to satisfy 

more efficiently the target specifications than with a 

closed loop structure. 

Parameter WLAN UMTS 

Bandwidth 12 MHz 2.11MHz 

DC-gain -10÷20 dB -10÷35 dB 

IRN@0dB dcgain 

5nV/√Hz 5nV/√Hz 

IP3@0dB dcgain 

30 dBm 30 dBm 

Input VCM 1.25 V 600 mV 

Table I -VGA Specs for different standards


Fig. 2 – The VGA circuit. 

M1 and M2 operate in source follower configuration; 

the differential input voltage v 

+ − 

v − v is 

in = in in 

copied over the series impedance of the two 

nonlinear transconductance gm1 

and the linear 

degeneration resistors Rdeg. The gm1 linearity is 

improved by closed-loop structure including the 

input opamps, which uses a single differential pairs 

for large bandwidth and low noise level. 

The VGA dc-gain, G, is calculated as 

follows: 

G = 

R 

deg 

R L 

Ao 

R L 

⋅ ≅ 

1 ( 1 + A ) R 

+ 

o deg 

g ( 1 + A ) 

m1 

o 

(1) 

where gm1 is the M1-M2 transconductance while A0 

is the input opamp dc-gain. With this solution, the 

different input common-mode voltage of the 

different standard is “absorbed” by the input 

differential stage, which passes to the output load 

just a current proportional to the input differential. 

The VGA gain is the adjusted by a digital control, 

which changes the value of RL and Rdeg, as shown in 

Fig. 3, and reported in Table II. For a dc-gain lower 

than 0dB (i.e. for large input signals, with reduced 

requirements for low-noise, but large requirements 

for large linearity) the Rdeg is changed (reduced). On 

the other hand, for a dc-gain larger than 0dB (i.e. for 

small input signals, with large requirements for lownoise, 

but reduced requirements for large linearity) 

the Rdeg is set to a minimum value, while RL is 

increased. This reflects in the frequency response, 

which presents a single pole at the gain node of RL, 

at the frequency fp=1/(2·π·RL·Cout), where Cout is the 

capacitive load. For the -10dB and 0dB gain level, 

RL does not change and, accordingly also the fp 

value. For larger dc-gain the fp value reduces, while 

guaranteeing a sufficient bandwidth for the VGA. 

132 

AV 

[dB 

] 

Table II –Resistors values for gain setting 

RL 

[Ω] 

Rdeg IRN [nV/sqrt(Hz)] IIP3 [dBm] 

[Ω] UMTS WLAN UMTS WLAN 

-10 150 400 12.8 13.4 39 39.8 

0 150 150 4.8 4.9 31.3 30.9 

20 2k 150 4.22 4.24 -3.7 -3.6 

35 32k 150 4.2 4.2 -18.2 -17.8 

Fig. 3 - Structure for the gain control 

The input-referred noise, IRN, is calculated, 

approximalively, as follows: 

2 

⎛ Rdeg 

⎞ 2 

IRN = 4 ⋅ kT ⋅ Rdeg 

⋅ 

⎜ 

⎜1 

+ + vin 

_ op 

R ⎟ (2) 

⎝ L ⎠ 

The VGA IIP3 is calculated as follows: 

2 2 2 

2 2 2 

( 1+ 

g R A ) ≈ 384⋅ 

I ⋅ R A 

IIP = ⋅ (3) 

2 

3 96⋅Vov1 

⋅ m1 

deg o 

2 deg o 

where Vov1 is the M1-M2 overdrive. The maximum 

opamp gain is limited by the technology. Thus, the 

VGA linearity performance is depends on the I2 

current level. 

The output stage is a unity gain level shifter. It 

provides a 1.25V output common mode voltage. 

This solution allows to keep M1-M2 in saturation 

region. 


The proposed VGA has been designed in a standard 

0.13µm CMOS technology. The frequency response 

for different gain level is shown in Fig. 4. It can be 

seen that the different gain levels correspond to

different bandwidth, satisfying the requirements for 

the different standards. Table III summarizes the 

VGA performance, for the different standards. Fig. 

5 shows the layout of the device, which is under 

fabrication. The active chip size is 0.5mm x 1.5mm. 


Fig. 4 – VGA transfer functions 

Table III -VGA performance at 0dB dc-gain 

Standard UMTS WLAN 

VCMin [V] 0.6 1.25 

IIP3 [dB] 31.7 30.6 

IRN [nV/sqrt(Hz)] 4.9 

Current consumption 

Differential stage 1.65mA x 2 

Opamp 1.15mA x 2 

Level shifter 0.40mA x 2 

Total 6.4mA 

Power supply 2.5V 

THD (@500mV) -50dB 

133 

Fig. 5 – Chip layout 


A high-linearity, low-noise VGA in a 0.13µm 

CMOS technology is proposed. The VGA is 

embedded in a reconfigurable receiver able to 

process different telecom standards (WLAN, 

UMTS, GSM, and Bluetooth). The VGA is then 

able to satisfy all the requirements for each 

standards in terms of dc-gain, bandwidth and 

common mode input voltage. The proposed VGA 

consumes about 6.4mA, its IRN is lower than 

5nV/√Hz and the IIP3 is more than 30dBm at 0dB 

DC-gain. 

ACKNOWLEDGMENT 

This research has been partially supported by the 

Italian National Program FIRB, Contract n° 

RBNE01F582. 

5. REFERENCES 

[1] “Enabling Technologies for Wireless 

Reconfigurable Terminals” FIRB Project, 

WebPage: http://ims.unipv.it/firb/ 

[2] S. D’Amico, A. Baschirotto, A. Vigna, N. 

Ghittori, and P. Malcovati, “Low-power 

reconfigurable baseband block for 

UMTS/WLAN transmitters”, Proc. of 

NORCHIP 2004. 

[3] A.A. El-Adawy, A.M. Soliman, H.O. Elwan; 

“Low voltage fully CMOS voltage mode


digitally controlled variable gain amplifier”. 

Microelectronics Journal 31 (2000) 139-146 

[4] J.J.F, Rijns; “CMOS Low-Distortion High- 

Frequency Variable-Gain Amplifier”. IEEE 

Journal of Solid-State Circuit, July 1996 

134


FULLY INTEGRATED RF FRONT−END FOR WLAN: A NEW 

STEP TOWARD SINGLE-CHIP TRANSCEIVERS 

Domenico Zito, Francesco D’Ascoli, Bruno Neri 

Dipartimento di Ingegneria dell’Informazione (DIIEIT), RFLab, University of Pisa 

G.Caruso 16, I-56122 Pisa, Italy 

e-mail: d.zito@iet.unipi.it 

ABSTRACT 

The RF stages of a fully integrated front-end on standard 

silicon technology for low power Wireless Local Area 

Network applications are presented. The circuit solution 

herein proposed includes an innovative Tx/Rx antenna 

switch which does not require any additional 

technological steps and gives better performance with 

respect to those which commonly use PIN diodes as 

switching element. The operating principle is highlighted 

and the most representative performances are 

summarized. 


The integration of as more devices as possible into a 

single-chip allows the cost reduction and the increasing of 

the performances. Actually, since undesired parasitic 

effects due to the packaging are avoided and buffer stages 

towards external components are not necessary, a 

reduction of the dissipated power and an increasing of the 

design reliability are obtained. All these factors contribute 

drastically to the cost reduction of the entire transceiver 

[1], which represents the main target toward the mass 

market of radiofrequency interfaces for Wireless LAN 

applications. The most widespread standards for these 

applications are IEEE 802.11a and HiPerLAN/2. Both of 

them operate in the 5-6 GHz band and are based on Time 

Division Duplexing protocol and Orthogonal Frequency 

Division Multiplexing modulation. The topmost level of 

the admitted output power for 5.15-5.35 GHz indoor 

applications is in the range of 50-250mW [2]. Even 

though these values are not so low, the integration of the 

Power Amplifier (PA) can be approached too, so that the 

WLAN systems offer the interesting prospective to realize 

fully integrated transceivers on standard silicon 

technologies. 

However, the low quality factor of integrated LC filters 

(often limited by the inductors) represents a strong 

limitation to the realization of almost ideal resonant filters 

on standard silicon technologies. For this reason, the most 

widespread commercial solutions consist of using bulky 

and expensive components external to the chip, such as 

MEMS [3] or GaAs devices [4]. Although fully integrated 

transmitter and receiver solutions for WLAN are even 

more widespread in literature [2, 5], the Tx/Rx antenna 

switch is still remaining the last obstacle to the complete 

integration of the transceiver. Only recently, some active 

circuits have been realized as switching element on 

135 

standard microelectronic technologies [6,7]. Their main 

drawback is given by a not negligible insertion loss (near 

to 1.5 dB). The novel solution presented in this paper uses 

an active circuit named ‘Boot-Strapped Inductor’ (BSI) 

which has been demonstrated capable of giving equivalent 

inductance L eq (which can be varied by means of a control 

voltage by even a factor of 10) with a quality factor Q in 

excess of 50 [8, 9]. Exploiting these peculiarities, the BSI 

circuit can be driven from a low impedance to a high 

impedance state. Thus, the power in the circuit can be 

guided from the PA to the antenna during the transmission 

time interval (Tx) and from the antenna to the Low Noise 

Amplifier (LNA) during the reception time interval (Rx), 

as it will be explained hereinafter. This paper is organized 

as follows: in Section 2, the operating principle of the 

novel antenna switch, the LNA and the PA are 

highlighted. In the Section 3, the fully integrated RF frontend 

design for 5-6 GHz Wireless LAN is reported and 

discussed. Moreover, the main performances are reported 

and compared with those of other solutions. Finally, in 

Section 4, the conclusions are drawn. 

2. THE CIRCUIT NOVELTY 

The basic idea of the innovative circuit solution is 

represented by the antenna switch (patented) which has 

been proposed in the past for 2.4 GHz WLAN systems. 

The antenna switch is implemented by exploiting the BSI 

circuit to realize high quality LC filter as blocking 

impedance for signal [10]. A BSI consists of an integrated 

transformer and a current amplifier, as shown in Fig.1. 

Figure 1. Basic scheme of the BSI. L 1 and L 2 are 

the inductances of the two spirals of an integrated 

transformer (IT); the cascode amplifier is used in 

stead of a current amplifier (CA). 

From a simplified small signal analysis of the BSI circuit 

shown in Fig.1, it derives that: 

Z = [ R + r − ω M g r sin ϕ] + jω[ L + M g r cos ϕ] 

(1) 

* * 

IN 1 π 12 m π 1 12 m π

where g m * is the tranconductance gain of the CA, ϕ is the 

phase difference (due to the capacitive effects) between 

the currents which flow in the spirals of the integrated 

transformer (L 1, L 2), M 12 is their mutual inductance and R 1 

is the parasitic resistance of the primary. The formula 

shows that Z IN is mainly depending on the current gain 

(both magnitude and phase). To be noted that, if ϕ results 

very close to zero (this can be done introducing a properly 

sized additional inductor in order to compensate the 

parasitic capacitance seen at the input the CA [8]) then an 

almost ideal equivalent inductance (L eq) is obtained. By 

acting on the quiescent points of the transistors Q 1 and Q 2 

(in principle, that can be done by means of I B1 and V B2, as 

reported in the scheme of Fig.1), the transconductance 

gain and the input capacitance of the amplifier can varied 

[8] and so also the value of the equivalent inductance L eq. 

This approach has been successfully adopted to realize the 

LC resonant circuit (L realized by means L eq of the BSI 

circuit) in a tunable LNA with excellent selectivity 

(f 0 / B 3dB > 25, where f 0 is the central frequency and B 3dB 

the bandwidth at minus 3dB) for 1 GHz applications. The 

measured results are reported in Fig. 2. The reliability of 

such an approach has been demonstrated by a test 

campaign on several prototypes. The robustness against 

temperature has been proved [11] and moreover, in [9], a 

self-calibration digital system has been proposed and 

successfully investigated in order to compensate the 

spreading of process parameters, temperature and aging 

effects. 

However, in the case of the Tx/Rx antenna switch, the BSI 

circuit presents two operating conditions of interest: the 

former, in which the current amplifier is switched-on and 

then the boot-strap effect on the equivalent inductance is 

obtained; the latter, in which the current amplifier is 

switched-off and then the aforementioned effect is 

missing. The scheme of Fig. 3 clarifies the way in which 

the BSI circuit can be properly exploited to implement the 

novel Tx/Rx antenna switch. Particularly, the capabilities 

of the BSI have been used in two different ways in 

receiver and transmitter. During Tx, the BSI circuit at the 

input of the LNA (which is switched-off) is active, so 

providing a high impedance path (L eq is resonant with C) 

with respect to that of the antenna (typically, 50 Ohm�). 

Figure 2. Transducer gain G T (measured) of the 

tunable LNA based on the BSI circuit. The inset 

on top reports the central frequency f 0 (where 

G T=G Tmax) of the frequency responses obtained 

for three different couples of I B1,V B2. 


136 

Figure 3. Scheme of principle of the Tx/Rx 

antenna switch. The current amplifier (CA) of 

each BSI can be switched ON/OFF. To be noted 

the different approaches used to realize the 

blocking impedance in the receiver (R) and 

transmitter (T). 

During the receive time intervals (Rx), the CA of the LNA 

(which is switched-on) is in off state therefore the value of 

the equivalent inductance (1) is switched to the low value. 

At the same time, the BSI circuit at the output of the PA 

(Fig. 2) is activated in order to present a high impedance 

path from the antenna toward the PA. For sake of clarity, 

in this case, the BSI circuit has been properly designed in 

such a way the phase difference ϕ (1) is in the fourth 

quarter, so obtaining a high impedance value, both for real 

and imaginary parts. 

The different approaches (resonance for the Rx path and 

high impedance for the transmitter one) are related to the 

different linearity constrains of the receiver and 

transmitter channels. The resonant solution has 

demonstrated reaching for higher blocking impedance and 

a larger linearity range. The proposed solution can be 

implemented in many different technologies and 

processes, in a single ended or in a fully differential 

architecture (as shown in Fig. 3), and it can be adapted for 

a wide range of RF frequencies. The key factor for a 

successful design is to size the driving circuitry and the 

transformer in order to obtain a nearly perfect power 

match alternatively between the antenna and LNA or PA. 

3. 5-6 GHZ RF FRONT-END: 

CIRCUITS AND PERFORMANCES 

The design of the RF front-end with the BSI based 

antenna switch, has been realized for low power (50 mW) 

5.15-5.35 GHz WLAN systems, relatively to a fully 

differential topology with a 50 Ω antenna impedance. For 

reasons of space, a single ended equivalent and simplified 

schematic is reported in Fig. 4. The LNA is implemented 

by a cascode stage with inductive emitter degeneration 

(L E) for an integrated matching to 50 Ω of the antenna and 

a subsequent emitter follower buffer stage.

Figure 4. Simplified and equivalent single ended 

scheme of the fully integrated RF front-end, 

inclusive of the BSI Antenna Switch. The CAs are 

made of two cascode stages put in cascade. 

The PA is realized by a cascade of two cascode emitter 

stages with inductive degeneration and LC resonant load 

filters (L 1C 1, L 2C 2) realized by means of on-chip 

integrated inductors. 

The circuits have been designed by using the HBTs of a 

standard SiGe-CMOS 0.35 µm technology (S35 by AMS) 

with a top metal thickness of 2.5 µm and a maximum cutoff 

frequency of 75 GHz. The chip picture is reported in 

Fig. 5. Circuit and electromagnetic simulations have been 

performed by means of SpectreRF, Advanced Design 

System and Momentum, respectively. 

The transducer gain (GT) of the LNA is nearly 20 dB (see 

Fig. 6) and the Noise Figure (NF) is 3.74 dB. The inputreferred 

CP 1dB is -21 dBm. The total power consumption 

is equal to 27 mW @ 3V of power supply (3 mA drained 

by the buffer). As for the PA, the power gain amounts to 

22.5 dB (see Fig. 7), the power saturation level is nearly 

equal to 12 dBm and the total power consumption is 144 

mW. 

In Rx mode, the input impedance of the receiver chain is 

very close to 50 Ω, whereas the output impedance of the 

transmitter (|Z T|, see Fig. 3) is about 840 Ω. In Tx mode, 

Z T is very close to 50 Ω, whereas |Z R| becomes 

approximately equal to 1 KΩ (see Fig. 8). 

PA 

Figure 5.Chip picture (the total area is 2.4 mm 2 T 

R 

IN/OUT 

). 


LNA 

137 

The power consumption of the BSI circuits amounts to 

12.9 and 26 mW, in Rx and Tx mode, respectively. The 

Power Ratio (PR), defined as the ratio between the power 

delivered to the antenna and that lost in the receiver, is 

greater then 10 up to +12 dBm of output available power 

of the PA (Pout_pa), as shown in Fig. 9.a. The relevant 

insertion loss, defined as the ratio between the power 

available from source and the power delivered to load, is 

0.235 dB and 0.585 dB (at most is 1.1 dB at 50 mW) for 

Rx and Tx mode operations, respectively. These results 

have been obtained by a non-linear steady state analisys 

and they are shown in Figg. 9 and 10. 

Figure 6. Transducer gain (GT) and available 

power gain (GA) of the LNA vs. frequency. The 

load impedance is equal to 100 Ohms. 

Figure 7. The power gain (Gp) of the Power 

Amplifier vs. frequency. The source impedance is 

equal to 100 Ohms. 

Figure 8. The blocking impedance (resonant) seen 

from the input of the receiver during Tx. The 

value of the real part of Z R is higher than 500 

Ohms (ten times R ANT) in a frequency range of 

400 MHz around 5.25 GHz.


a) 

b) 

Figure 9. Results relative to the Tx mode. a) The 

Power Ratio (PR) between the power delivered to 

the antenna and that lost in the receiver vs. the 

available power at the output of the PA (Pout_pa); 

b) the insertion loss (IL). They has been obtained 

by non-linear analysis (Harmonic Balance). 

a) 

b) 

Figure 10. Results relative to the Rx mode. a) The 

Power Ratio (PR) between the power delivered to 

the input of the receiver and that lost in the 

transmitter vs. the available power at the antenna; 

b) the insertion loss (IL). They have been obtained 

by non-linear simulations (Harmonic Balance). 

138 

These results are very promising if compared with those 

which are typically obtained by using external switches or 

duplexer which not only have to be added as external 

components to the transceiver, but they also introduce an 

insertion loss of at least 1-2 dB. The chip has been just 

realized and the measurements have already started and 

they will be carried out in the next weeks. 


The RF stages of a innovative fully integrated RF frontend 

comprehensive of antenna switch have been presented 

and demonstrated at simulation level. The circuit has been 

implemented in a 0.35 µm SiGe-CMOS standard process. 

If the obtained results will be confirmed by the 

measurements on the prototypes, this fully integrated RF 

front-end for WLAN in the 5-6 GHz frequency band will 

represent a significant new step toward the realization of 

single-chip transceivers. 

REFERENCES 

[1] M. Steyaert, “Single chip CMOS RF transceivers: 

wishful thinking or reality”, IEE Seminar on Low 

Power IC Design (Ref. No. 2001/042), 2001, pp.1-6; 

[2] H. Samavati, T. H. Lee et al, “5-GHz CMOS 

Wireless LAN” IEEE MTT , vol. 50, pp. 268-280, Jan 

2002; 

[3] C. Goldsmith, J. Kleber, et al. “RF MEMS: benefits 

& challenges of an evolving RF switch technology”, 

Tech. Digest of IEEE GaAs IC Symp. 2001, pp.147- 

148, Oct 2001; 

[4] C.-H Lee, S. Chakraborty, et al., “Broadband highly 

integrated LTCC front-end module for IEEE 802.11a 

WLAN applications”, Proc. of IEEE MTT Symp. 

2002, vol. 2, pp.1045-1048, Jun 2002; 

[5] M. Zargari et al., “A 5-GHz CMOS Transceiver for 

IEEE 802.11a Wireless LAN Systems” IEEE JSSC, 

vol. 37, is. 12, pp. 1688- 1692, Dec 2002; 

[6] Feng-Jung Huang, K.O, “A 0.5-µm CMOS T/R 

switch for 900-MHz wireless applications” IEEE 

JSSC, vol.36, is.3, pp.486-492, Mar 2001; 

[7] N. A. Talwalkar, C.P. Yue, et al., “Integrated CMOS 

Transmit-Receive Switch using LC-Tuning Substrate 

Bias for 2.4-GHz and 5.2 GHz Applications”, IEEE 

JSSC, vol.39, n.6, pp. 863-870, Jun 2004; 

[8] G. D’Angelo, A. Monterastelli, B. Neri et al., “Highquality 

active inductors”, IEE Electronics Letters, 

vol. 35, n. 20, 30 Sep 1999; 

[9] D. Zito, De Bernardinis and B. Neri, “Modeling and 

Design of High Q Tunable Low Noise Amplifier for 

WLAN”, Proc. of IEEE ICSES 2004, pp.253-256, Jul 

2004; 

[10] L. Fanucci, A. Hopper, B. Neri, D. Zito “A Novel 

Fully Integrated Antenna Switch for Wireless 

Systems”, Proc. of IEEE ESSDERC 2003, pp.553- 

556, Sep 2003; 

[11] S. Di Pascoli, B. Neri, D. Zito et al., “Single-chip 1.8 

GHz band pass LNA with temperature selfcompensation”, 

Proc. of IEEE ISSCS 2003, vol.1, 

pp.125-128, Jul 2003.


Hierarchical FPGA clustering to improve routability 

Zied Marrakchi, Hayder Mrabet, Habib Mehrez 

LIP6-ASIM Laboratory, Université Paris 6, Pierre et Marie Curie 

4 Place Jussieu, 75252 Paris, France 

E-mail: zied.marrakchi@lip6.fr 

ABSTRACT 

In this paper we present a new clustering technique, 

based on the multilevel partitioning, for hierarchical 

FPGAs. The purpose of this technique is to reduce 

area and power by considering routability in early 

steps of the CAD flow. We will show that this 

technique can reduce the needed tracks in the 

routing step by 15% compared with the other 

packing tools. 


Field Programmable Gate Arrays (FPGAs) have gained 

rapid commercial acceptance thanks to their 

reconfigurability and low cost. Speed and area efficiency 

of an FPGA are directly related to the granularity of its 

logic blocks. If the logic blocks are fine grained, the 

circuit to be implemented will be distributed over a larger 

number of logic blocks. This has a negative impact on 

routability since more blocks need to be interconnected. 

Recently FPGA vendors have introduced hierarchical 

FPGAs consisting of logic clusters. Examples of such 

devices are the Xilinx Virtex and the Apex from Altera. In 

these architectures several Look Up Tables (LUTs) are 

clustered into one logic block to provide better 

performances specially for communication and to exploit 

signal sharing among LUTs. Our work focuses on the way 

to adapt an existing multilevel partitioning tool to the 

FPGA clustering problem. In fact, some constraints 

imposed by the architecture (number of pins and cluster 

size) must be respected. 

2. PREVIOUS WORK 

Prior research on clustered FPGA architectures has 

focused mainly on area and delay optimisation. Betz et al. 

[1] proposed a packing/clustering algorithm: Vpack for 

hierarchical FPGAs [5]. The main idea in their work was 

to pack a technology-mapped circuit into clusters of a 

given size and input/output pin constraints. The same 

authors introduced a tool, T-Vpack [2], using a timing 

driven packing approach based on the idea of packing 

blocks on timing-critical paths to exploit fast local 

interconnects. The clusters generated using T-vpack use an 

average of 12% fewer tracks than the clusters generated 

using Vpack for the same array size. A recent work, Rpack 

[3] presented a routability-driven packing algorithm 

which first identifies routability factors and prioritizes 

these factors into an improved clustering function. This 

approach produces routing track counts comparable to 

those generated by T-Vpack. 

139 

3. ARCHITECTURE OVERVIEW 

The FPGA we are targeting is of island-style structure. As 

it can be seen in figure 1, the circuit is composed of 

clustered logic blocks (CLBs), switch blocks, connection 

blocks, and I/O blocks. Each CLB, which implements the 

user’s logic, has inputs and outputs connected by the 

routing network. It contains N basic logic elements 

(BLEs) grouped together. Each BLE contains a k-input 

lookup table (a K-LUT) followed by a bypass flip-flop. 

The LUT inputs are chosen from among a set of shared 

cluster inputs. In our case k = 4. 

The Connection block connects the input and output pins 

of a CLB to the routing channel, and the Switch block 

connect the wires of two intersecting channels. The 

number of tracks between any two neighboring clusters is 

uniform and is called the channel width. The number of 

logic clusters that each wire-segment spans before going 

through a switch box is called the track segment length. 

We assume that a cluster of size n has (2n + 2) input pins 

and n output pins. Indeed, this is sufficient to achieve full 

logic connectivity as shown by Betz in [1]. In addition we 

assume that all segments are of length 1. 

Figure 1. General architecture model 

4. MULTILEVEL LOGIC 

CLUSTERING APPROACH 

Clustering is done in 2 phases. First we apply a k-way 

partitioning to the circuit. So having a circuit consisting of 

set of modules and set of signal nets, we want to divide it 

into k clusters such that the number of inter-cluster signal 

nets is minimized. As we will use an existing partitioning

tool we can’t impose several constraints in advance like 

the number of pins per cluster. That’s why in the second 

phase we have to move some vertices among the partitions 

to respect such constraints. 

4.1 Partitioning running 

In this phase, we present the multilevel partitioning 

algorithm that we have applied to divide the BLEs into 

clusters. As in the FPGA partitioning problem, BLEs must 

be divided into k roughly equal parts, we use an algorithm 

that computes directly the k partitions: hMETIS-Kway [4]. 

The hMETIS-Kway is k-way partitioning algorithm based 

on the multilevel paradigm. 

As shown in figure 2, the hypergraph is coarsened 

successively and it is directly partitioned into k parts. Then 

this k-way partitioning is successively refined as the 

partitioning is projected back into the original hypergraph. 

Corsening 

phase 

Figure 2. The various phases of the multilevel clustering 

approach 

If during the clustering special properties of the 

interconnect can be exploited, significant gains can be 

obtained in terms of routability. when we run the 

partitioning we choose an objective function that 

minimises the number of external nets and eliminates nets 

with high density: A net with a larger number of terminals 

is harder to route. 

4.2 Respecting Constraints 

When the k-way hMetis partitioning is run, it’s impossible 

to impose the constraints concerning the partitions’ size 

and the number of inputs per cluster. As it can be seen in 

figure 1 a “constraints respecting” step was added at the 

end of the uncoarsening phase. First we have to verify for 

each cluster if the number of blocks exceeds the limit 

imposed by the FPGA architecture. In this case we have to 

move some blocks from some clusters and to place them 

in other ones. In a second step we have to verify if the 

number of external input nets exceeds the number of 

cluster’s input pins allowed by the architecture. In this 

case we have also to move some blocks. When we do such 

moves we will modify the partitions that we have obtained 

and this can have a bad effect on the objective function. So 

in both cases we have to select the candidates to move 

with the best gain. The gain is defined as the number of 

external nets (~number of pins per cluster) to reduce when 

we move a bloc B from a cluster C. 


Constraints 

respect 

Uncorsening 

phase 

140 

Gain ( B, 

C) 

= 

∑ 

i∈Nets( 

B) 

g( 

i, 

Nets( 

C), 

B) 

Now we present how the gain for each net is computed. 

Note that each block output pin is accessible from outside 

and there is no sharing among the output pins. Therefore 

there would be no output pin constraints for the clusters. 

According to this observation, saving on output pins 

doesn’t bring any gain. 

Cluster C 

i0 out 

i1 

N2 

i2 

i3 

N1 

N3 

i0 out 

i1 

i2 

i3 

Block to move 

i0 out 

i1 

i2 

i3 

i0 out 

i1 

i2 

i3 

N4 

Figure 3. Logic block being moved from a cluster 

In figure 3, we show a candidate basic block B and a 

cluster C. The nets N1, N2, N3 and N4 have different 

contributions to the gain of moving the block B. 

N1 is connected to input pins of two blocks inside the 

cluster C. So N1 has no improving effect since the 

external input pin will be kept. So the gain obtained by 

moving B from cluster C corresponding to net N1 is 0. 

However since all terminals of the net N2 are inside the 

cluster (internal net), one input pin of the cluster would 

be used for N2 if we move the block B. So the gain of 

moving logic block B to the cluster due to N2 in terms of 

used input pins per cluster is -1. N3 is connected to only 

an input pin of the block B in the cluster C. So when we 

move B an input pin gets free and the gain is 1. The 

driving pin of N4 is the output of the logic block B. There 

is an input pin of net N4 inside the cluster C. If we move 

the block B we need to use an input pin of the cluster to 

connect the net N4 to other terminals of the net outside 

the cluster. According to this reason the net N4 has a 

contribution to the block gain equal to -1. 

All different cases yielding different gains are presented in 

table 1, for one net connected to the candidate block. 

Table. 1. Gain of moving a block according to a single 

net 

pin in B -> Staus in-pin 

pin in C 

gain 

out -> out B has the 

only pin 

0 

out -> out Other in pins 

in C 

-1


in -> in B has the 

only pin 

1 

in -> in Other in-pins 

in C 

0 

in -> in All pins in C -1 

in -> out - 0 

Once we have selected the candidate block to move, we 

must select the best cluster receiver. The cluster receiver 

must verify the following conditions: 

• Number of blocks is less than the limit number 

imposed by the architecture; 

• Number of input pins doesn’t exceed the 

number imposed by the architecture. 

When we add a block to a cluster we must not exceed the 

number of inputs. So we compute a gain function for each 

cluster. The gain is the number of the inputs that will be 

added (negative value) or reduced (positive value) when 

we insert the block into the cluster. 

Cluster receiver C 

i0 out 

i1 

i2 

N2 

i3 

N1 

N3 

i0 out 

i1 

i2 

i3 

Block to insert 

Figure 4. Logic block being inserted in a cluster 

In figure 4, a block B and a candidate cluster C are 

presented. Block B has two common nets with cluster C: 

N1 and N2. An input pin of the net N1 is inside the cluster 

C. By adding the block B to the cluster, another input 

terminal of the net N1 would be inside the cluster. This 

will not lead to any change concerning the input pins, the 

gain is equal to 0. The driving pin of net N2 is the output 

of the logic block B. There is an input pin of net N2 inside 

the cluster C. If we insert the block B there will be no need 

to use an input pin of the cluster to connect the net N2 to 

other terminals of the net outside the cluster. By adding 

block B to cluster C, an input pin of the cluster gets free 

and can be used for another net connection. The gain 

corresponding to this net is eqaul to 1. Net N3 has no pins 

inside the cluster C. One pin of the cluster will be used for 

N3. So the gain of moving logic block B to the cluster due 

to N3 in terms of used input pins per cluster is -1. 

The gain for each block inserting in cluster C can be 

computed as follows: 

Gain( 

B, 

C) 

= 

∑ 

i∈Nets( 

B) 

i0 out 

i1 

i2 

i3 

i0 out 

i1 

i2 

i3 

g( 

i, 

Nets( 

C), 

B) 

141 

g(I, Nets(C), B) is defined as the gain obtained in input 

pins of cluster C as defined in table 2. 

Table. 2. Gain of inserting a block according to a single 

net 

pin in B -> 

pin in C 

Status in-pin gain 

in -> out 

in -> in 

- 0 

out -> in - 1 

in New net -1 

out - 0 


We have implemented our clustering technique, on the top 

of VPR [5], we have used a Pentium-4 machine 3 GHz. 

We placed and routed 18 of the largest MCNC random 

benchmark circuits [6] on clustered FPGAs. Cluster size 8 

was used in our experiments. 

5.1 Routability and power consumption 

Table 3 shows the routing tracks results for T-VPack [2], 

RPack [3] and our clustering technique. For the same 

number of clusters T-VPack and R-Pack use about 15% 

more tracks than our clustering technique. Less number of 

tracks does not only mean saving wiring area but also 

decreasing the size of the routing switches. The reduction 

of needed tracks is directly related to the amount of 

interconnect power saving. 

Table. 3. Routing tracks 

T-Vpack R-Pack Ours 

Circuits Clusters Channel Channel Channel 

alu4 192 26 34 26 

apex2 240 34 35 33 

Apex4 165 37 35 35 

bigkey 214 17 15 11 

des 200 17 18 15 

diffeq 189 20 19 17 

dsip 172 14 24 11 

elliptic 454 37 32 30 

ex1010 599 41 42 31 

ex5p 139 37 36 31 

frisc 446 39 34 36 

misex3 178 29 32 29 

pdc 582 52 56 51 

s38417 802 29 25 18 

s38584 806 32 26 20 

seq 221 33 37 34 

spla 469 42 48 39 

tseng 133 21 21 13 

average 344.48 30.49 31.16 25.94

5.2 Circuit speed and run time 

Now we will check the effect of our clustering method on 

circuit speed. We placed and routed the same benches on 

clustered FPGAs using a timing-driven algorithm. Table 4 

shows the critical path results for T-VPack [2] and our 

clustering technique. We have almost the same speed 

performance. Our clustering method can deal with the area 

and speed problems in the same time. 

Table. 4. Critical path and run time 

T-Vpack Ours 

Circuits C.Path Run time C.Path Run time 

(ns) (s) (ns) (s) 

alu4 59.8 47.3 55.3 50.2 

apex2 76.0 100.2 69.1 90.3 

Apex4 65.7 71.5 63.4 57 

bigkey 43.6 58.2 29.6 38 

des 46.5 68.3 54.9 62.4 

diffeq 43.7 41.5 56.7 39.1 

dsip 52.4 45.4 33.4 41.9 

elliptic 81.29 260.5 99.7 265.3 

ex1010 86.8 525 98.6 495.4 

ex5p 110.6 65.2 108.3 56.7 

frisc 53.9 280.3 60.0 290.8 

misex3 59.3 59.3 57.5 60.7 

pdc 126.7 818.7 121.7 825.5 

s38417 87.3 360 77.7 341.4 

s38584 59.3 420.3 55.9 413.8 

seq 63.5 79.5 62.7 88.2 

spla 98.1 314 98.7 320.7 

tseng 51.3 33.3 50.4 35 

average 70.2 202.7 69.6 198.5 

The time consumed in our partitioning method is 

relatively important and this is due essentially to the 

“uncoarsening” and the “constraints respecting” phases. 

In table 4 we show the time consumed to run clustering, 

placement and routing in both cases. We notice that by 

spending more time in the clustering stage we reduce the 

time that will be consumed in the placement and routing 

phases. 


6. CONCLUSION 

In this paper we proposed a multilevel partitioning method 

for cluster-based FPGAs. This method improves the 

routability by decreasing the number of required tracks in 

the FPGA routing. This method has also a good effect on 

optimising the critical path. Those improvements were 

achieved thanks to the multilevel partitioning and the 

choice of the objective function. Those results in terms of 

area and power reduction are important for FPGA 

embedding on SOC. 

142 

7. REFERENCES 

[1] V.Betz, J.Rose and A.Marquartdt, “Architecture and 

CAD for Deep-Submicron FPGAs”, Kluwer 

Academic Bublishers, 1999. 

[2] A.Marquart, V.Betz and J.Rose “Using Cluster-Based 

Logic blocks and Timing-Driven Packing to improve 

FPGA speed and density” ACM/SIGDA International 

Symposium on Field Programmable Gate Arrays, 

Montrey, CA, February 1999, pp.37-46. 

[3] E.Bozogzadeh, S.Ogrenci-Memik, M.Sarrafzadeh, 

“RPack: Routability-driven Packing for cluster-based 

FPGAs”, Proceedings, Asia-South Pacific Design 

Automation conference, January 2001. 

[4] G.Karypis and V.Kumar, “Multilevel k-way 

Hypergraph Partitioning”, DAC99, New Orleans 

Louisiana. 

[5] V.Betz, J.Rose “A New Packing, Placement and 

Routing tool for FPGA research”, Proc Seventh 

FPLA, pp.213-222, 1997. 

[6] S.Yang, “Logic synthesis and optimization 

benchmarks” user guide version 3.0. MCNC, Jan. 

1991.


AN EVOLUTIONARY APPROACH FOR 

SYMMETRICAL FIELD PROGRAMMABLE GATE 

ARRAY PLACEMENT 

M. Yang 1 , A.E.A. Almaini 1 , L. Wang 2 , P.J. Wang 3 

1 School of Engineering, Napier University, 10 Colinton Road, Edinburgh, EH10 5DT, UK 

2 Microelectronics Department, Fudan University, 220 Handan Road, Shanghai, 200433, China 

3 Faculty of Information Science and Technology, Ningbo University, 315211, China 

E-mail: m.yang@napier.ac.uk 

ABSTRACT 

An evolutionary computation method is used to place a 

set of different Microelectronics Center of North Carolina 

(MCNC) benchmark circuits on traditional symmetrical 

Field Programmable Gate Array (FPGA). The 

experimental results are compared to the state-of-the-art 

results from Versatile Placement and Routing (VPR). The 

proposed algorithm achieves promising performance, in 

terms of routing channel density. 


The logic capacity of commercial FPGAs has significantly 

increased as the process geometry shrunk to 

deep-submicron such as 0.13 micron. Placement is an 

NP-complete problem, thus new challenges arise from the 

continuous growth in the number of logic elements. 

The routing resources in the FPGA are prefabricated and 

are crucially limited compared to Mask Programmable 

Gate Array (MPGA). To achieve 100 percent placement 

and routing, many algorithms such as genetic algorithm 

(GA) [1] [2], simulated annealing (SA) [3] [4] [5] and 

particle swarm optimization (PSO) [6] were proposed. 

The objective of this paper is to present a placement 

solution for the traditional symmetrical FPGA [7] by 

using GA, one of the evolutionary computation methods. 

GA is stochastic search algorithm based on biological 

evolution models, whose main advantages lie in its 

robustness of search and problem independence. The basic 

concepts of GA were developed by Holland in 1975 [8]. 

Although GA has characteristics of robustness and wide 

range search space, it normally takes a large number of 

generations to converge to optimum, resulting in long 

CPU consumption. This makes fast prototyping of FPGA 

difficult. As a result, a modified GA with greedy scheme 

is introduced. 

In this paper, section 2 gives a brief description of 

symmetrical FPGA architecture. In section 3 the proposed 

genetic algorithm is given. Experimental results showing 

the effectiveness of the proposed approach are presented 

in section 4. Conclusion is then given in section 5. 

143 

2. FPGA ARCHITECTURE 

Symmetrical FPGA [7] consists of three fundamental 

components: logic blocks, input and output (I/O) blocks 

and programming routing resources. Logic blocks and 

routing resources are surrounded by I/O blocks. The 

symmetrical FPGA used by Xilinx is shown in Fig. 1. 

Figure 1. Symmetrical FPGA architecture. 

Fig. 2 shows a logic block of symmetrical FPGA. It is 

composed of one 4-input look-up table (LUT), which is 

used to implement combinational logic, one D flip-flop 

and one multiplexer to select combinational or sequential 

logic. 

Figure 2. A logic block.

3. EVOLUTIONARY APPROACH 

3.1 Algorithm 

The GA is a search technique which mimics the natural 

process of evolution as a means of progressing to the 

optimum. 

Basically, it starts with an initial set of random solutions 

termed as population. Each individual in the population 

consists of a string of bits termed as genes. The string 

which is made up of genes is termed chromosome. The 

chromosome represents a solution to the problem. During 

each iteration, which is termed generation, the individuals 

in the current population are evaluated using measurement 

of fitness function. Those individuals with high fitness 

values, i.e. good placement solutions, are more likely to 

be selected. Genetic operators such as crossover and 

mutation are employed to find good solution. As a result, 

the fitness of population evolves as the number of 

generations increases. 

Figure 3. Proposed genetic algorithm. 

Fig. 3 shows the pseudo code for the proposed GA. The 

proposed algorithm modifies standard genetic algorithm in 

three ways. First one is selection operator. 30 percent of 

population with higher fitness remains intact while the rest 

is selected probabilistically based on the fitness of the 

individual. The higher the fitness, the more likely it can be 


144 

selected. Second is greedy scheme. Selection of individual 

for greedy improvement is also probabilistic. It works on 

selected individuals in order to improve visible fitness by 

swapping two positions of two blocks at a time for a 

number of iterations. Third one is elitism. Elitism is used 

to ensure the survival of good solutions to the next 

generation. 

3.2 Representation 

One possible representation of an individual can be 

binary. A binary individual consists of a string of binary 

digits. A 0 or 1 in the string corresponds to if condition is 

false or true, as shown in Fig. 4. Fig. 5 shows a vector of 

positive integer representation. 

Figure 4. Binary representation. 

Figure 5. Positive integer representation. 

The vector of positive and negative integers is more 

natural in our placement optimization. As a result, it is 

used to represent each individual. 

In the representation, only one negative integer value is 

used, which is -1. It represents empty. Positive integer can 

be in the range of [0, ∞] and depends on the number of 

logic blocks. For example, if the number of logic blocks is 

11, the positive integers are then 0, 1, 2, … 9, 10. The 

logic block at the location (x,y) of the FPGA has a 

corresponding position in the chromosome. The position is 

calculated as shown in Eq. 1 

position = ( x −1) 

× size + ( y −1) 

Eq. 1 

where position stands for position of gene and size stands 

for the size of FPGA. For example, if the size of a FPGA 

is 4 by 4, then size = 4. 

Figure 6. A simple example of representation.

A simple example is illustrated in Fig. 6. An empty Logic 

Block which is located at (1,1) corresponds to the gene at 

the 1st position of the vector, resulting in negative integer 

-1. Logic Block 10 which is located at (1,2) corresponds 

to the gene at the 2nd position of the vector, resulting in 

positive integer 10. 

3.3 Fitness function 

The quality of placement is evaluated by fitness function. 

The higher the fitness, the higher the quality of placement. 

Since a benchmark circuit will have hundreds of nets or 

even more, the measure is judged by average fitness value 

of all nets not just by any partial one, which is shown in 

Eq. 2. 

f 

N 

= maxcost− 

∑ C(i)[ bbx 

(i) + bb y 

(i)] 

i = 1 

Eq. 2 

where maxcost stands for the worst cost for placement, N 

stands for the total numbers of nets. For each net i, bb x(i) 

and bb y(i) denote the horizontal and vertical spans of its 

bounding box respectively. C(i) compensates for the fact 

that the bounding box wire length model underestimates 

the wiring necessary to connect nets with more than three 

terminals. Its value depends on the number of terminals of 

the net i. 

3.4 Genetic operators 

Since GA works on a population, a population of 

individuals is initialized, and then genetic operators are 

employed on the population of the individuals. In the 

proposed algorithm, the population is initially evaluated 

according to fitness function which is mentioned in 3.3. 

The fitness values of population are sorted in increasing 

order according to fitness of individual. Individuals of 30 

percent of population with higher fitness value in the 

current population are intact and remain in the next 

population. The rest, i.e. 70 percent of current population, 

works as follows. 

The fitness of each individual is considered as a slot of a 

sized pie. M equidistant markers are placed around the 

pie, where M = 0.7 × K and K is the number of 

individuals in the population. Fig. 7 shows the sized pie 

and markers around the pie. A total fitness value of 70 

percent of the population corresponds to the whole size. A 

random decimal number greater than zero but less than 

one is generated. This decimal number corresponds to the 

rotation of the markers. If the marker is inside the slot, the 

corresponding individual is selected. As a result, M 

individuals are simultaneously selected. Although the 

selection procedure is random, the chance of being 

selected for each individual is proportional to its fitness. 

For example, if M = 6 and the random decimal number is 

0.125, the markers will rotate 45 degrees. The selected 

individuals are therefore 2, 3, 3, 4, 5 and 5, as shown in 

Fig. 7. 


145 

Figure 7. An example of a sized pie according to 

the fitness of each individual and the rotation of 

the markers. 

The one-point crossover operator [1] is then employed to 

produce two new individuals, offsprings, by combining 

two individual parents. Diversity of the population is 

maintained by using the mutation operator [1]. 

3.5 Greedy scheme 

In order to overcome long CPU consumption in standard 

GA, greedy scheme which works for randomly selected 

individual is introduced. It begins by randomly selecting 

one individual from the population. Then two genes are 

randomly selected for swapping in the selected individual, 

i.e. two logic blocks are randomly selected and swapped. 

The swapping might result in either increase or decrease 

of fitness value. Only when fitness value increases after 

swapping, the swapping is accepted. Those swaps that 

reduce fitness value are discarded. This scheme is carried 

out in each generation. In each generation, swapping two 

blocks is performed for several iterations. 

4. RESULTS 

This section presents the experimental results obtained by 

the proposed algorithm. The implementation of the 

algorithm was written in the C programming language. All 

experiments were performed on Intel Pentium 2.4 GHz 

with 512M memory under RedHat Linux Enterprise AS3. 

Performance is measured using 19 Microelectronics 

Center of North Carolina (MCNC) benchmark circuits. 

The fixed parameter values are selected for all tested 

benchmarks following some experiments and based on 

previous experience. POP_SIZE = 50, Pcrossover = 0.6, 

Pmutation = 0.005, Pgreedy = 0.3 and Preserve = 0.3. 

The placement is an intermediate stage of the Electronic 

Design Automation (EDA) flow. The way to measure the 

quality of a placement is to route the placement. The 

placements generated by VPR and our algorithm are both 

performed on the smallest possible size of a FPGA and 

routed by VRouter [3] with same parameter settings for 

the purpose of fair comparison. The numbers of channel 

tracks required to route a placement is used to judge the 

quality of the placement, as illustrated in Table 1. The less 

the channel tracks needed for the circuit, the better the

placement. One routing example of tested benchmark 

9symml is given in Fig. 8. 


5. CONCLUSION 

An evolutionary placement algorithm for symmetrical 

FPGA is described. The proposed genetic algorithm can 

achieve as good performance as the state-of-the-art 

placement tool VPlace. Only 2 out of 19 tested MCNC 

benchmark circuits, which are clip and k2, perform worse 

than VPlace. These two benchmark circuits consume one 

more track each. 

Table 1. The comparison results of routing 

channel tracks between VPR and GA. 

Placer Smallest VPlace [3] GA 

Router size VRouter [3] 

5xp1 8x8 4 4 

9symml 10x10 5 5 

alu2 15x15 6 6 

apex7 11x11 5 5 

b9 8x8 4 4 

cc 6x6 3 3 

comp 7x7 4 4 

clip 12x12 5 6 

count 7x7 4 4 

e64 17x17 8 8 

example2 19x19 5 5 

f51m 8x8 4 4 

k2 23x23 9 10 

lal 6x6 4 4 

ldd 7x7 4 4 

pcler8 6x6 4 4 

term1 10x10 5 5 

too-lrg 14x14 7 7 

vda 18x18 8 8 

Total 98 100 

146 

Figure 8. Final routing of 9symml. 

6. REFERENCES 

[1] M. Yang and A.E.A. Almaini, Hybrid Genetic 

Algorithm for Xilinx-style FPGA Placement, Proc. of 

the First Intl. Conf. on CAD/ECAD, Durham 

University, UK, pp. 95-100, 2004. 

[2] V. Schnecke and O. Vornberger, Hybrid genetic 

algorithms for constrained placement problems, IEEE 

Transactions on Evolutionary Computation, vol. 1, 

no. 4, pp. 266-277, 1997. 

[3] V. Betz and J. Rose, VPR: A New Packing, 

Placement and Routing tool for FPGA research, 

Proceeding of the Seventh Field Programmable 

Logic Applications, pp. 213-222, 1997. 

[4] W. Vigerske, B. Stube and M. Pleßow, Automatic 

Wiring in Switch Cabinets, Proc. of the First Intl. 

Conf. on CAD/ECAD, Durham University, UK, pp. 

90-94, 2004. 

[5] C. Sechen and A. Sangiovanni-vincentelli, 

TimberWolf3.2: A new standard cell placement and 

global routing package, Proc. of the 23rd DAC, pp. 

432-439, 1986. 

[6] V. G. Gudise and G. K Venayagamoorthy,., FPGA 

Placement and Routing Using Particle Swarm 

Optimization, Proc. of the IEEE Computer Society 

Annual Symposium on VLSI Emerging Trends in 

VLSI Systems Design (ISVLSI’04), pp. 307-308, 

2004. 

[7] Xilinx Inc., XC4000E and XC4000X series FPGAs, 

Data sheet. 1997. 

[8] D. E. Goldberg, Genetic algorithms in search, 

optimization, and machine learning, Addison 

Wesley, 1989.


RoRA: A RELIABILITY-ORIENTED PLACE AND 

ROUTE ALGORITHM FOR SRAM-BASED FPGAS 

Luca Sterpone, Matteo Sonza Reorda, Massimo Violante 

Politecnico di Torino, Dipartimento di Automatica e Informatica (DAUIN), CAD group 

C.so Duca degli Abruzzi 24, Torino, Italy 

E-mail: luca.sterpone@polito.it 

ABSTRACT 

SRAM-based FPGA designs are extremely susceptible to 

Single Event Upset (SEUs). Since the configuration 

memory defines which is the circuit an SRAM-based 

Field Programmable Gate Array (FPGA) implements, any 

change induced by SEUs in the configuration memory 

may modify drastically the implemented circuit. When 

such devices are used in safety-critical applications, fault 

tolerant techniques are needed able to mitigate the effects 

of SEUs in FPGA’s configuration memory. In this paper 

we present a reliability-oriented place and route algorithm 

that is able to mitigate the effects of the considered 

upsets. 


SRAM-based Field Programmable Gate Arrays (FPGAs) 

are programmable devices used for different application, 

such as signal processing, prototyping and networking. 

They are composed of a fixed number of routing resources 

(wires and programmable switches), memory modules, 

and logic resources (i.e., look-up tables or LUTs, Flip- 

Flop FFs): all these components are programmed by 

downloading into a on-chip configuration memory a 

proper bitstream giving the FPGA the capability of 

implementing nearly any kind of digital circuit on the 

same chip. 

The content of the configuration memory is crucial for the 

correct operations of the circuit the FPGA implement. In 

SRAM-based FPGAs the mapped circuit is totally 

controlled by the configuration memory. When energetic 

particles hit the surface of the SRAM-based FPGAs, they 

can alter the bits composing the configuration memory, 

and therefore the circuit the FPGA implements may 

change its original behavior. 

In SRAM-based FPGA, both combinational and sequential 

logic are implemented by several customizable SRAM 

cells which are extremely sensitive to radiations that may 

cause SEUs [1]. If an upset affect the combinational logic 

in the FPGA, it provokes a bit flip in one of the LUTs 

cells or in the cells that control the routing. This upset has 

a permanent effect, and is correctable only at the next load 

of the configuration bitstream. Viceversa, when an upset 

affect the user sequential logic it has a transient effect 

because the flip-flop’s next load corrects it. 

147 

An earlier solution consisted in developing radiationhardened 

FPGAs by resorting to special manufacturing 

technologies. Although effective, this solution is very 

expensive because radiation-hardened FPGAs cost several 

orders of magnitude more than commercial-of-the-shelf 

devices. The solution that is currently under investigation 

consists in adopting fault-tolerant architectures to 

implement hardened circuits while using commercial-offthe-shelf 

FPGA. 

Triple Modular Redundancy (TMR) design technique is 

the high-level SEU mitigation technique most often used 

today to protect designs synthesized in SRAM-based 

FPGA since memory elements, interconnections and 

combinational gates are all susceptible to SEUs and fullmodule 

redundancy must be adopted. The TMR 

implementation uses three identical logic blocks 

performing the same task in parallel with corresponding 

outputs being compared trough majority voter. Although 

TMR is suitable for protecting FPGA memory elements, 

interconnections and combinational gates, TMR is able to 

mitigate only partially the effects of SEUs affecting those 

resources, as we have been observed through a detailed 

analysis of FPGA resources and extensive fault-injection 

experiments [2]. 

In this paper we propose a reliability-oriented place and 

route algorithm (RoRA) able to place and route the logic 

functions and the signals of a design in such a way that the 

number of SEUs affecting the configuration memory and 

possibly causing FPGA misbehaviors is significantly 

reduced with respect to the TMR approach. The algorithm 

is applicable to every kind of design implemented on 

SRAM-based FPGAs. 

2. PRELIMINARIES 

A Field Programmable Gate Array consists of an array of 

logic blocks that can be interconnected selectively to 

implement different designs. An FPGA logic block is 

typically capable of implementing many different 

combinational and sequential logic functions. Today, 

commercial FPGAs use logic blocks that are based on 

transistor pairs, basic small gates such as two-input 

NANDs or exclusive ORs, multiplexers, Look-up tables 

(LUTs) and wide-fanin AND-OR structures. An FPGA 

routing architecture incorporates wire segments of varying 

length that can be interconnected via electrically 

programmable switches. The distribution of the length of

the wire segments affects directly the density and 

performance achieved by an FPGA. 

The SRAM-based FPGA generic model used in this work 

consists of three kinds of resources, as shown in fig. 1 : 

logic blocks, switch boxes and wiring segments. The logic 

blocks contain the combinational and sequential logic 

required to implement the user circuit. The input and 

output signals are connected to adjacent switch boxes 

through wiring segments. The switch boxes are switch 

matrices where several programmable interconnect points 

(PIPs) (i.e. pass transistor), called routing segments 

controlled by the configuration memory, are available. We 

modeled the resources within a SRAM-based FGPA as 

vertices and edges of a graph. Thus we have logic vertices 

that model the FPGA’s logic blocks, routing vertices that 

model the input/output points of the switchboxes, routing 

edges that model the PIPs and wiring edges that model the 

FPGA’s wiring segments. Edges and vertices are colored 

to indicate the corresponding FPGA’s resource is used to 

implement a circuit. In the case the FPGA implements 

different circuits, or different replicas of the same circuits, 

different colors are used to mark each circuit. 

Logic 

Block 


Wiring segments 

Logic 

Block 

Switch box Switch box 

Figure 1. Generic FPGA architecture model 

3. SEU EFFECTS ON FPGA’S 

CONFIGURATION MEMORY 

The effects induced by SEUs on SRAM-based FPGAs 

have been recently investigated thanks to radiation 

experiments [3]. More recently, an analysis that combines 

the results of radiation testing with those obtained while 

analyzing the meaning of every bit in the FPGA’s 

configuration memory was presented in [4]. Although 

SEUs are transient by definition, when they are originated 

in the configuration memory their effects are permanent, 

since SEUs remain latched until the configuration memory 

is rewritten with new configuration data. The errors 

produced by SEUs in the FPGA’s configuration memory 

can be classified in two different categories: errors that 

affect logic blocks and errors that affect the switch boxes. 

Considering the logic-block errors, several different 

phenomena may be observed, depending of which 

resource of the logic block the SEU modified: 

1. LUT error: the SEU modified one bit of a LUT, thus 

changing the combinational function it implements. 

148 

2. MUX error: the SEU modified the configuration of a 

MUX in the logic block; as a result, signals are not 

correctly forwarded inside the logic block. 

3. FF error: the SEU modified the configuration of a 

FF, for example changing the polarity of the reset 

line, or that of the clock line. 

In order to model faulty logic blocks in the routing graph 

we described in the previous section, we assumed to use 

the black color to mark each vertex corresponding to a 

faulty logic block. 

As far as switch boxes are considered, different 

phenomena are possible. Although a SEU affecting a 

switch box modifies the configuration of one PIP, both 

single and multiple effects can be originated. Single 

effects happen when the modification induced by the SEU 

after the affected PIP, only. In this case one situation may 

happen is Open the SEU changes the configuration of the 

affected PIP in such a way that the existing connection 

between two routing segments is opened. In the routing 

graph we model such a situation by deleting the routing 

edge corresponding to the PIP that connects the two 

routing vertices. 

In order to describe the multiple effects in terms of 

modifications to the routing graph, let us consider a pair of 

connection between four routing vertices AS/AD and 

BS/BD as shown in fig. 2.a. Depending on the FPGA 

architecture, it is possible that one and only one 

configuration memory bit controls two or more routing 

segment. Thus, a SEU affecting it may modify two or 

more routing segments provoking a multiple errors. 

According to our graph model, SEUs affecting 

configuration memory bits controlling routing resources 

can modify two or more edge, generating multiple errors. 

We identified the following modifications that could be 

introduced between AS/AD and BS/BD: Short (fig. 2.b) a 

new edge is added, Open (fig. 2.c) two edges are deleted 

and Open/Bridge (fig. 2.d) both one edge is added and one 

is deleted. 

A D 

A S 

B D 

B S 

A D 

A S 

B D 

B S 

(a) (b) (c) (d) 

Figure 2. Possible multiple effects induced by one SEU 

Since one SEU may be responsible for multiple errors, 

hardening techniques developed accordingly to the singlefault 

assumption are not adequate to cope with the effects 

of SEUs in the configuration memory. As a result of the 

analysis we performed on FPGA architectures, we defined 

the following constraints that must be enforced by the 

place and route algorithm in order to develop a faulttolerant 

graph marking: 

1. All the circuit modules and connections must be 

replicated three times; 

A D 

A S 

B D 

B S 

A D 

A S 

B D 

B S

2. The outputs of the three circuit replica must be voted 

according to the TMR principle; 

3. The elements of the resulting TMR architecture (logic 

functions and connections among them) must be 

placed and routed in such a way that, given the 

corresponding routing graph, each new edge that is 

added (or deleted) to (from) the graph cannot provoke 

any fault belonging to the following categories: 

a. Short between different connections belonging 

to different circuit replicas; 

b. Open different connections belonging to 

different circuit replicas. 


4. THE RORA ALGORITHM 

/*Placement*/ 

generate_functions_replicas (F1, F2, F3) 

generate_majority_voter (F4) 

generate_partitions (S1, S2, S3, S4) 

for each logic function LF ∈ Fi 

place LB on Si where i = {1, 2, 3, 4} 

/*Routing*/ 

FVSi = ∅ where i = {1, 2, 3} 

for each source vertex SV ∈ Fi 

{ 

for each destination vertex DV of SV 

RT = route (SV, DV) 

update (FVSi,RT) 

} 

Figure 3. The flow of the proposed Reliability-Oriented 

Place and Route Algorithm RoRA 

In general, the commonly used design-flow to map 

designs onto a SRAM-based FPGA consist of three 

phases. In the first phase, a synthesizer is used to 

transform a circuit model coded in a hardware description 

language into an RTL design. In the second phase a 

technology mapper transforms the RTL design into a gatelevel 

model composed of look-up tables (LUTs) and flip 

flops (FFs) and it binds them to the FPGA’s resources 

(producing the technology-mapped design). In the third 

phase, the technology mapped design is physically 

implemented on the FPGA by the place and route 

algorithm. 

The problem of how to physically implement a circuit on a 

FPGA device is divided into two sub problems: placement 

and routing. The main reason behind such decomposition 

is to reduce the problem complexity. Our proposed 

reliability-oriented place and route algorithm, called 

RoRA, firstly reads a technology mapped design. Then, it 

performs a reliability-oriented placement of each logic 

functions, and finally it routes the signals between 

functions in such a way that multiple errors affecting two 

different connections are not possible. 

The algorithm we developed is described in fig.3, where 

the placement and routing steps are shown in a C-like 

pseudo-code. Our proposed RoRA Placement algorithm 

149 

performs a robust placement, which implements the TMR 

principle, executing four distinct functions: 

1. The generate_functions_replicas () firstly reads the 

design description produced after the technology 

mapping and identifies the logic functions in the 

design. Secondly, it generates three replicas of the 

logic functions belonging to the original design. Let 

F be the set of the original design’s logic functions: 

at the end of this step the three sets F1, F2 and F3 are 

produced. 

2. The generate_majority_voter () analyzes the three 

logic function sets F 1, F 2 and F 3, and generates a 

logic functions set F 4 that performs the majority 

voting between them. 

3. The generate_partitions () partitions the routing 

graph’s vertices in four non-overlapping sets, where 

each set S i (i=1,2,3,4) has enough logic vertices to 

contain the logic functions of each set F i (i=1,2,3,4). 

4. Every logic function in set F i is placed heuristically 

to the logic vertices in set S i, where i=1, 2, 3, 4. This 

phase takes care of marking the graph, by assigning 

each logic function to exactly one logic vertex in our 

routing graph. 

The RoRA placement algorithm places each logic 

functions in Fi to the graph vertices belonging to Si, as 

well as the majority voter on S4. After the placement 

process, each set Si contains exclusively the function of set 

Fi. This solution allows us to guarantee that single or 

multiple effects within one set Si only do not provoke any 

misbehavior of the circuit. Indeed, accordingly to our 

placement, only multiple effects on the border of two 

different sets Si ≠ Sj may generate multiple errors that 

affect two different replicas. 

When all the logic functions are placed to the 

correspondent logic vertex set, RoRA performs the routing 

of the interconnections between the logic vertices. 

Basically, the RoRA Routing algorithm works on the 

routing graph we developed, and it routes each connection 

between two logic vertices through the shortest path it can 

find. During path selection, the RoRA Routing algorithm 

labels dynamically the graph’s routing vertices, in such a 

way that it avoids the instantiation of two connections that 

may be subject to Short effects. Each graph routing vertex 

(RV) are labeled as free, used or forbidden, with the 

following meanings: 

1. Free: the routing vertex is not used by any 

connection. 

2. Used: the routing vertex is already used by a 

connection. 

3. Forbidden: a routing vertex RV is forbidden if and 

only if: 

a. It belongs to set Si (RV∈Si), and 

b. At least one routing edge, or one wiring edge 

exists between RV and another vertex RV’ 

belonging to Sj (RV’∈Sj), where i ≠ j.

If RV is added to the circuit and a SEU affects the routing 

resources in such a way that both RV and RV’ are 

affected, the TMR does no longer work as expected. The 

Forbidden Vertices Sets (FVSs), which are empty at the 

beginning of the RoRA routing, contain the vertices 

marked as forbidden and belonging to the correspondent 

graph routing vertices set S i. 

RoRA performs the routing of each net by taking into 

consideration all the graph’s vertices labeled as free, and it 

updates progressively the FVSs adding the vertices 

marked as forbidden. 

As soon as the net is routed, and the marking of the graph 

has been updated (i.e., the vertices in the routing graph, 

and the associated edges, have been marked as used by the 

circuit implementation), the update () function is used to 

modify the set i of forbidden vertices (FVSi), which is 

empty at the beginning of RoRA routing. 


We evaluate the robustness of the circuit obtained from 

RoRA using the fault injection environment presented in 

[2]. We considered four benchmark circuits (two adders, 

one multiplier and a filter) and we placed them on a Xilinx 

Spartan ® XC2S200EPQ208 [5], the characteristics of the 

adopted circuits are reported in table 1 where we report the 

number of FPGA slices that circuit occupies (column 

Area) as well as its maximum working frequency (column 

Speed), for the plain, the TMR and the RoRA versions. It 

is interesting to observe that, for the considered 

benchmarks, RoRA does not introduce any area overhead 

with respect to the traditional TMR solution (which is 

about 3 times larger than the plain circuit). Conversely, 

when placed and routed through RoRA, the circuits 

become 22% slower on the average than their TMR 

versions. This effect is the result of the dependabilityoriented 

routing algorithm that RoRA implements: the 

shortest path is not always selected as the best solution, 

since it may not be acceptable from the dependability 

point of view. To measure the hardness of the obtained 

circuit we injected 15,000 randomly selected SEUs in the 

FPGAs configuration memory. The results are reported in 

tab. 2, where Injected Faults is the number of injected 

SEUs and Wrong Answer is the number of SEUs for 

which the faulty circuit produces outputs that differ from 

the fault-free one. 


Table 2. Fault Injection results. 

Circuit Injected Wrong Answer [#] 

Faults Plain TMR RoR 

A 

Add8 15,000 14,587 1,352 30 

Add16 15,000 14,598 1,692 41 

Mul8 15,000 14,603 1,977 23 

Filter 15,000 14,642 1,981 44 


In this paper we propose a reliability-oriented place and 

route algorithm able to reduce the effects of SEUs in 

SRAM-based FPGAs. Its effectiveness was evaluated on 

some benchmark circuits by means of fault injection 

experiments in the FPGA configuration memory. For the 

considered benchmarks, the capability of tolerating SEU 

increases up to 85 times. This improvement comes without 

any additional area cost with respect to the TMR design 

technique, while a performance penalty of 22% on the 

average is observed. 

7. REFERENCES 

[1] E. Normand, “Single Event Upset at Ground Level”, 

IEEE Transaction on Nuclear Science, vol. 43, No. 6, 

Dec. 1996 

[2] P. Bernardi, M. Sonza Reorda, L. Sterpone, M. 

Violante, “On the evaluation of SEUs sensitiveness 

in SRAM-based FPGAs”, 10th IEEE International 

On-Line Testing Symposium, 2004, pp. 115-120 

[3] M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, 

M. Ceschia, A. Paccagnella, M. Rebaudengo, M. 

Sonza Reorda, M. Violante, P. Zambolin, 

“Evaluating the effects of SEUs affecting the 

configuration memory of an SRAM-based FPGA”, 

IEEE Design Automation and Test in Europe, 2005, 

pp. 1290 - 1295 

[4] M. Ceschia, M. Violante, M. Sonza Reorda, A. 

Paccagnella, P. Bernardi, M. Rebaudengo, D. 

Bortolato, M. Bellato, P. Zambolin, A. Candelori, 

“Identification and classification of single-event 

upsets in the configuration memory of SRAM-based 

FPGAs”, IEEE Transaction on Nuclear Science, Dec. 

2003, Vol. 50, No. 6, pp. 2088-2094 

[5] “Spartan-II 2.5 V FPGA family”, Xilinx, 2003. 

Table 1. Characteristics of the adopted circuits. 

Circuit 

Plain version TMR version RoRA version 

Speed [Mhz] Area Speed [Mhz] Area Speed [Mhz] Area 

[# slices] 

[# slices] 

[# slices] 

Add8 105 26 86 100 64 96 

Add16 105 28 85 103 62 105 

Mul8 105 41 64 127 54 125 

Filter 104 46 65 132 58 138 

150


EFFICIENT VLSI IMPLEMENTATION 

OF MULTIPLICATION IN GF(2 n ) 

Krzysztof Gołofit 

Warsaw Univesity of Technology, Faculty of Electronics and Information Technology, 

Ul. Nowowiejska 15/19, 00-665 Warsaw, Poland 

E-mail: kgolofit@elka.pw.edu.pl 

ABSTRACT 

The paper focuses on the possibilities of hardware 

implementation (above all VLSI proposals) of the 

multiplication in GF(2 n ). Encouraging solutions were 

implemented in technology 0.35 µm and served as the 

models for the projection of the main circuits parameters 

(silicon area, speed, power consumption) for currently 

used and more advanced technologies. 


It is common knowledge that multiplication is the most 

difficult and time-consuming operation independently of 

computational platform. For the hardware solutions, 

binary fields (arithmetic in GF(2 n ) ) are attractive since the 

operations involve only shifts and elementary operations 

like conjunction and bitwise addition modulo 2. The aim 

of this article is to present the logical way from theoretical 

backgrounds of multiplication in GF(2 n ), through the 

consecutive models – which are often difficult (or even 

unable) to perform in such hardware – to efficient and 

useful implementations. As a result of our considerations 

two alternative solutions will be shown. The first one 

assumes stream data processing and is based on systolic 

structure. The second one concerns fast multiplication 

where almost all of the operations are performed 

simultaneously – this case requires ONB (Optimal Normal 

Bases) to be use. Models of these two and other crucial 

solutions were implemented at the lowest possible design 

level – full custom VLSI (Very Large Scale Integration) 

technology. Such approach allows us to obtain 

implementation possibilities (first of all depending on field 

extensions) as well as basic circuits parameters. 

Familiarity with the advantages of more advanced 

technologies (for example additional layers of 

metallization) makes a few more interesting solutions 

possible – still giving an estimation of achievable 

parameters for each of analysed technologies. 

2. HARDWARE IMPLEMENTATION 

OF MULTIPLICATION 

2.1 Theoretical backgrounds of multiplication 

in GF(2 n ) 

The extensive computation number theory gives us 

methods to simplify and optimize almost every arithmetic- 

151 

cal operation in finite fields. Obviously the most 

computational complex operation still remains the 

multiplication which can be less demanding when normal 

bases (especially ONB) are used. A normal basis can be 

formed using the set 

2 

n−1 

2 2 2 

{ , β , β , ... , } 

N = β β 

(1) 

where β∈GF(2 n ) unambiguously determines the basis N. 

Every element A over GF(2 n ) can be uniquely represented 

as a linear combination of elements of N (and can be 

written in the form of vector) 

A 

n−1 

= ∑ 

i= 

0 

i 

0 1 n−1 

i 

2 

a ⋅ β = ( a a ... a ) (2) 

Multiplication of the two elements A and B over finite 

field GF(2 n ) can be defined as follow 

n−1 

n−1 

n−1 

n−1 

k 

k 

( k ) 2 

2 

A ⋅ B = ∑∑∑aib 

jtij 

β = ∑ ck 

⋅ β = C (3) 

k= 

0 i= 

0 j= 

0 

k= 

0 

where C∈GF(2 n ) is the result of multiplication and 

T − 

( k ) 

k = tij 

= t 

(4) 

j−i, 

k i 

are n multiplication tables of size n-by-n, 0 ≤ k, i, j ≤ n–1. 

Every table Tk can be regularly produced from the table 

T = [tij] n×n. Table T can be calculate from following 

equation 

∑ − m 1 

ij 

j= 

0 

i 

2 

β ⋅ β = t ⋅ β 

(5) 

i 

Optimal normal bases require optimal complexity in every 

multiplication table Tk – it means that the quantity of the 

nonzero elements has the minimal value (2n–1). 

Practically we have at the most two elements in every row 

and every column of the matrix. Transformation from the 

table Tk to the table Tk+1 (for both NB and ONB) results in 

a regular slanting shift of the elements in the table – what 

can be undemandingly implemented in hardware. 

The equation describing k bit of vector C can be finally 

written – on the basis of definition (3) – as multiplication 

of n-by-n matrix T and elements A and B written in the 

form of n-by-1 vector 

c k 

k AT B' 

= (6) 

where B' stands for the transpose of the vector B.

2.2 VLSI hardware multiplication 

The first idea for the hardware VLSI implementation is to 

build a computational array following almost directly the 

theoretical basis. The main cell of the array consists of 

three elements: flip-flop, binary conjunction and addition 

modulo 2. Multiplied vectors A and B are delivered 

horizontally and vertically to the array respectively, during 

the time when flip-flops are holding values analogous to 

the current multiplication matrix T k. Following the 

formula (3) every single cell of the array is making binary 

multiplication of bits t ij (k) (elements tij of the matrix T k), a i 

and b i. The results are first added vertically (in the 

columns) and then horizontally (under the array) giving 

consequently binary value of the bit c k. Cyclic process 

together with regular slanting shifts (among the flip-flops) 

provides us with the whole vector C. Unfortunately we can 

observe cubic dependence of processing time on field 

extension n (caused by sequence: vertical addition, 

horizontal addition, n-time cyclic process). 

Figure 1. The structure of the cells for the cyclic 

multiplication circuit. 

Computation time can be shortened from dependence n 3 

to n 2 +1 by making second addition (the horizontal) 

in the cycle for the next bit – while the next vertical 

addition is processed. Outlook on practical implementation 

of the complete array model for GF(2 11 ) 

with the vertical signals addition (at the top of the array) 

is presented in Figure 2. 

Furthermore, we can design the array, where all of the 

array cells will systematically process the data at the same 

time – it will give us the linear dependence of computation 

time on n. Both the multiplied vectors and the 

temporary intermediate results must be transported 

between cells in such solution. The single cell consists of 

binary conjunction, addition modulo 2 and 3 flip-flops 

– for the multiplied bits ax, by and the intermediate result 

(there is no need to save and transform the values of the 

table T – the set can be rigidly arrange). The first 

intermediate results of c1 can be compute in the first row 

(alongside the vector A) and the first column (alongside 


152 

Figure 2. VLSI layout of the cyclic multiplication 

circuit model for GF(2 11 ). 

the vector B) of the cells. The outcomes (as well as the 

vectors A and B) will be deliver to the second row and the 

second column – where will be the next step of the 

computations. In the second step the first row and the first 

column (spare at the time) can take up computations of 

the bit c2. Graphically, the computation wave progress 

vertically and horizontally to the corner of the array 

– therefore the computation time is shortened to the linear 

dependence on n. Unfortunately, from the practical point 

of view, such solution is restricted by the field extension 

n. The single cells located in the diagonal line should 

provide the rest of the cells in the same rows and columns 

with the multiplied signals ax and by – it can not be 

effectively implemented. Illustration of this case, being 

less practical, will be pass over in this article, however, on 

this ground we can consider next solution. 

Definitely more interesting instance is the systolic model. 

Systolic array is characterized merely by communication 

between adjoining cells. In this construction the 

computational wave is moving diagonally. 

Figure 3. The systolic structure – the single array cell. 

Flip-flops are used as the memory of intermediate results 

and current multiplied bits a x and b y. We have also binary 

conjunction of the bits a x, b y and t ij (values of the table T 

are rigidly placed) as well as addition modulo 2 for the 

actual and previous intermediate result. The last column 

and the last row must make binary addition of 4 signals, 

however, binary conjunction is not required for the first

ow and the fist column. The multiplied vectors A and B 

are delivered respectively, but in the first step we need to 

deliver the bits a1 and b1 to the first row and the first 

column, in the second step b2 and a2 to the first and the 

second row and the column, in the third step a3 and b3 to 

the first three columns and rows respectively, etc. 

Consequently we have two major advantages. First, linear 

(2n) dependence of time on n. Second, the input data 

should be delivered in the order from 1 to n, making 

stream data processing possible! 

The models illustrated in the Figure 1 and 3 have been 

modeled in full custom VLSI technology (0.35 µm). Both 

solutions are characterized by square dependence of the 

silicon area on n and square dependence of the dissipated 

power on n. In the first case the area of one cell is equal to 

590 µm 2 and in the second one to 1100 µm 2 . Power 

consumption strongly depends on field extension 

(obviously square dependence), input data, and cell 

structure (consists of a quantity of flip-flops and gates). 

Speed of the elementary cell in both circuits is comparable 

– processing time of one cell amount to 2.56 ns. 

Differences between circuits can be noticed in dependences 

on n – the first one is characterized by square 

dependence: n 2 +1, the second by linear dependence: 2n. 

Simplicity and recurrence of presented structures are 

indisputable advantages of those solutions. Moreover, in 

the systems where pipelined solutions are required systolic 

multiplication can find excellent application. But there are 

examples where stream data processing cannot be 

exploited – the cases of specific cryptography solutions, 

where vectors are rotated between multiplications (making 

squarins). Therefore other multiplication methods must be 

considered. 

2.3 Fast multiplication 

When optimal extension field (OEF) is used multiplication 

can be done in the particular way. The difference relates to 

the fact that we resign from universal solution in aid of the 

parallel but rigid construction. Making n multiplication 

arrays (each for the different matrix T k) building of the 

flip-flops can be passed over (as a matter of course most 

area involving factor comes off). Remembering that in 

every column at the most two nonzero elements appear we 

can arrange all the computation gates into one line and 

only cross their connections. 

Figure 4. The structure of the fast multiplication 

circuit (for one bit). 


153 

For the reason that we have to build n similar constructions 

– for every bit of the vector C – square dependence 

of gates area is obvious nevertheless crossed connections 

result in cubic dependence of area on n. It is graphically 

depicted in Figure 5 – area with cubic dependence is 

marked at the top of the middle picture and is equal to 

5.75 µm 2 in 0.35 µm technology. Square area factor (on 

the left in Fig.5) is approximated to 105 µm 2 . 

Figure 5. VLSI layout of the fast multiplication 

circuit for GF(2 11 ). 

The greatest advantage of this solution is that the circuit is 

very fast and the dependence of processing time from n is 

negligible (about ⎡log 2n⎤ ). It takes place because almost 

all possible computations are performed parallely. The 

time of one multiplication in mentioned technology with 4 

metallization layers for n = 500 is equal to 4 ns. 

General estimation of the circuit area for the 0.35 µm 

technology with 3 metallization layers is presented by 

the equation 

3 

2 

P = pk 

3 ⋅ n + pop 

⋅n 

+ ps 

⋅ ⎡ 2 n⎤+ 

pr 

3 log (7) 

where pk3 – area of the elementary connection (5,75µm 2 ); 

pop – area of the ‘oper’ component (104,19µm 2 ); ps – area 

of addition modulo 2 (115,65 µm 2 ); pr – supplementary 

area factor (n 2 + ⎡log 5 n⎤ )·30µm 2 – mainly responsible for 

distribution of multiplied signals. 

The main difficulty with the speed analysis are the 

increasing lengths of the circuit intra-connections. The 

numbers can be not precise, but their orders of values are 

reliable. We estimate the circuit processing time by 

T = 2 tin 

⋅ ⎡log25 n⎤+ 

toper 

+ ts 

⋅ ⎡log2 n⎤+ 

t (8) 

out 

where t_ are the elementary times of: t in – input amplifier 

(160ps); t oper – ‘oper’ component (380ps); t s – addition 

modulo 2 (300ps); t out – output amplifier (100ps). 

Nevertheless it is possible to determine exactly the number 

of transistors (what can be identified with dissipated 

power). 

2 

L 1, 26 ⋅ ⎡log25 n⎤+ 

10 ⋅ n + 2 ⋅ ⎡log 2 n⎤ 

= (9) 

Both parameters processing time and circuit area are 

inseparably related to applied technology. The series of

improvements are possible (precisely described in [12]) 

leading to decrease in silicon area up to 65% depending on 

applied technology. Percentage of reduction depending on 

additional layers of metallization (from 4 up to 7 layers) is 

shown in relation to the technology with 3 metallization 

layers (illustrated in Figure 6). 

Figure 6. Reduction of circuit area in different 

technologies in comparison to 3 met. layers techn. 

The size of the circuit – and connected with that 

implementation possibilities – still remains the major 

problem. Fortunately there is the perspective on exchange 

of processing speed to less silicon area making this 

solution more flexible and useful. Following the equation 

(4) we can observe that the differences between 

consecutives tables T k and T k+1 in definition (3) may be 

replaced with invariable table T 0 and proper rotation of 

multiplied vectors A and B 

n−1 

n−1 

n−1 

∑∑∑ 

i j ij 

k= 

0 i= 

0 j= 

0 


n−1 

n−1 

n−1 

( 0) 

∑∑∑a( 

i+ 

k) 

mod nb( 

j+ 

k) 

mod ntij 

k= 

0 i= 

0 j= 

0 

( k) 

a b t = 

(10) 

where 0 ≤ k, i, j ≤ n–1 (this trick have been used as well in 

systolic array implementation). Extremely we can build 

only one structure illustrated in Figure 4 and with the aid 

of n rotations of the A and B we obtain the entire vector C 

– the time of multiplication in this case take at least n 

times longer. 

3. CONCLUSION 

Comparing the proposals, the most significant point is the 

establishment that the linear dependence of computation 

time on n in the systolic solution was rearranged to 

negligible dependence of time in fast circuit. The cost of 

such reformation was cubic dependence of silicon area 

instead of square dependence. Universal solution 

(applicable to any binary field), simple implementation 

(resulting from highly modular structure) and ability 

to stream data processing are indisputable advantages 

of systolic model. Nevertheless the parallel and 

asynchronous method – difficult to implement and 

applicable only to ONB – makes hundreds more 

multiplications possible. 

As usual the faster and bigger parallel circuits would 

be probably used in highly specialized hardware 

accelerators (for example cryptographic coprocessors) 

154 

while the cyclic or systolic circuits can be implemented at 

less demanding solutions where economizing on area or 

pipelined algorithms would be applied. 

An estimation of achievable parameters depending on 

technological possibilities, speed requirements and 

universality or type of data processing is feasible through 

the specific design methods which take into account the 

fixed nature of presented models. 

4. REFERENCES 

[1] S. Gao, Normal Bases over Finite Fields, Waterloo, 

Ontario, Canada, 1993. 

http://www.math.clemson.edu/~sgao/pub.html 

[2] S. Gao, S. A. Vanstone, On Orders of Optimal 

Normal Basis Generators, Waterloo, Ontario, 

Canada, 1994. 

http://www.math.clemson.edu/~sgao/pub.html 

[3] J. Gawiniecki, J. Szmidt, Zastosowanie ciał skończonych 

i krzywych eliptycznych w kryptografii, 

WAT, Warsaw, 1999. 

[4] N. Koblitz, Algebraiczne aspekty kryptografii, WNT, 

Warsaw, 2000. 

[5] International Technology Roadmap for Semiconductors, 

ITRS Edition, Update, 2002. 

http://public.itrs.net. 

[6] A. Menezes, P. Oorschot, S. Vanstone, Handbook of 

Applied Cryptography, CRC Press, 1996. 

http://www.cacr.math.uwaterloo.ca/hac/ 

[7] S. Roman, Field theory, New York, Berlin, Heidelberg, 

Springer Verlag, 1995. 

[8] P.B. Bhattacharya, S.K. Jain, S.R. Nagpaul, Basic 

abstract algebra, Cambridge University Press, 1994. 

[9] W. Mochnacki, Kody korekcyjne i kryptografia, 

Oficyna Wydawnicza Politechniki Wrocławskiej, 

Wrocław, 1977. 

[10] K. Gołofit, Implementacja systemów podpisów cyfrowych 

wykorzystujących krzywe eliptyczne, Master 

thesis (in Polish), PW, ISE, 2003. 

[11] K. Gołofit, Implementacja mnożenia w technologii 

VLSI dla zastosowań krzywych eliptycznych, III KKE 

Kołobrzeg, 2004. 

[12] K. Gołofit, Analiza możliwości implementacyjnych 

mnożenia nad GF(2 n ) w technologiach VLSI, 

IV KKE Darłówko Wschodnie, 2005.


MULTIDIRECTIONAL CATV TRANSFORMERS 

Dariusz Krzemieniecki 1 and Ewa Hermanowicz 2 

1 GZT Telkom-Telmor, Gdansk, Poland dariusz.krzemieniecki@telmor.pl 

2 Gdansk University of Technology, Faculty of Electronics, Telecommunications and Informatics 

ul. Narutowicza 11/12, 80-952 Gdansk, Poland hewa@eti.pg.gda.pl 

ABSTRACT 

In this paper we propose novel multidirectional 

transformers, intended for application as passive power 

dividers, operating in the frequency range from 5 MHz to 

862 MHz in multimedia separators for CATV systems. 

The performance of these transformers is analysed in 

MATLAB by means of node voltage technique and 

compared with the results of measurements. 


The objective of this article is to present the performance 

of multidirectional transformers intended for application 

as passive power dividers in multimedia separators. These 

are exploited in CATV systems in the frequency range 

from 5 MHz to 862 MHz. The proposed multidirectional 

transformers substitute for hitherto solutions based on 

cascades of traditional unidirectional transformers. The 

novel solutions presented here afford the possibility of 

dividing the signal into branches of identical coupling. 

This highly desirable feature is very difficult to achieve in 

the corresponding cascades of unidirectional transformers. 

Moreover, the multidirectional transformers are capable of 

having uniformly shaped loss characteristic versus 

frequency and offer more economical solutions because of 

lower material consumption and lower cost of labour. 

2. UNIDIRECTIONAL 

TRANSFORMER 

A unidirectional transformer can be realized in four 

configurations. The first two of them are shown in Fig. 1. 

These are the basic (traditional) configuration and inverse 

configuration [1], [2], [3]. Each of the other two 

configurations, shown in Fig. 2, involves an additional 

element: the co called zero-resistor. This resistor can be 

used to achieve a slight improvement in the values of IN – 

the mismatch loss at the input, and TAP – the mismatch 

loss at the coupled line output. Fig. 3 presents the 

measured performance of a unidirectional transformer, 

constructed by the first author of the paper, in basic 

configuration. This is the so-called 10dB transformer. It 

means that the nominal value of the IN-TAP attenuation is 

10dB. All measurements here (see also Figs. 7 and 11) 

were done using the Rohde-Schwarz ZVR 1.70 analyzer. 

The meaning of symbols: 

• IN-OUT (attenuation in the main line between the 

input IN and output OUT), 

• IN-TAP (attenuation in the coupled line between the 

input IN and the branch TAP), 

155 

• OUT-TAP (attenuation between the main output OUT 

and the coupled branch TAP), 

• IN (as above), 

• OUT (mismatch loss at the output), and 

• TAP (as above), 

all expressed in dB, is the same as in [1]. The frequency 

characteristics have also been analyzed in the MATLAB 

environment [2], [3]; see Fig.4, by using the node voltage 

analysis technique under the quasi-static assumption [4]. 

This assumption is permissible for frequencies up to 

approximately 1.8 GHz for objects fulfilling the condition 

f [ GHz] 

< 150/ 

D[ 

mm] 

, where D stands for the diagonal 

of the physical object under consideration. 

Figure 1.Basic (top) and inverse (bottom) 

configurations of unidirectional transformer. 

Thus in modeling the admittance and scattering matrices 

were used, supposed that the circuits are composed only of 

lumped elements. A comparison of the calculated 

frequency characteristics of the designed transformers 

with their measured counterparts confirms that the above 

supposition is valid in the frequency band of interest here. 

The analysis is based on the complex-valued formula for 

the frequency dispersion of the ferrite permeability 

µ i 

µ ( f ) = 1+ 

(1) 

1+ 

jf / fm 

given by (5) in [1], where µ i stands for the initial 

permeability and f m is the frequency of relaxation, and 

j = −1 

. Influences of the initial permeability on the 

parameters of the 10dB unidirectional transformer in basic 

configuration are presented in Fig.5.

5 

0 

-5 

-10 

-15 

-20 

-25 

-30 

-35 

-40 

Figure 2. Configurations of the unidirectional 

transformer with zero-resistors. 

IN-OUT 

IN-TAP 

OUT 

-45 

0 100 200 300 400 500 600 

f [MHz] 

700 800 900 1000 


TAP OUT-TAP 

IN 

Figure 3. The performance of the 10dB 

unidirectional transformer in basic configuration – 

measurement results, µ = 1400 . 

IN − OUT 

IN − TAP 

OUT 

TAP 

IN 

Figure 4. The 10dB unidirectional transformer 

characteristics computed in MATLAB, basic 

configuration, µ = 1400 . 

i 

i 

OUT - TAP 

156 

0 

-5 

-10 

-15 

-20 

-25 

-30 

IN − TAP 

OUT 

TAP 

OUT - TAP 

IN − OUT 

-35 

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 

µ i 

IN 

Figure 5. The performance of the 10dB 

unidirectional transformer in basic configuration 

versus the initial permeability, f=5 MHz. 

3. MULTIDIRECTIONAL 

TRANSFORMERS 

Fig.6 shows the basic configuration of a novel twodirectional 

transformer [2]. The measured characteristics 

of the 15dB two-directional transformer are presented in 

Fig.7. 

Figure 6. The two-directional transformer in basic 


Fig.8 presents computed characteristics of this 

transformer. 

Note that the two-directional transformer should be 

realized in two configurations only: basic and inverse. 

Such transformers without zero resistors are impractical 

because of mismatch in coupled lines. Obviously, for the 

two-directional transformer we distinguish an additional 

parameter: an isolation loss TAP A-B between the coupled 

branches.

IN-OUT 

IN-TAP 

-10 

-15 

-20 

-25 

-30 

-35 

-40 

-45 

0 100 200 300 400 500 

f [MHz] 

600 700 800 900 1000 


5 

0 

-5 

IN 

OUT 

TAP A-B 

OUT-TAP 

TAP 

Figure 7. Experimental characteristics of the 15dB twodirectional 

transformer in basic configuration, µ = 1400 . 

An influence of the initial permeability on the parameters 

of the 15 dB two-directional transformer in basic 

configuration is presented in Fig.9. 

Figure 8. Calculated characteristics of the 15dB twodirectional 


0 

-5 

-10 

-15 

-20 

-25 

-30 

-35 

IN − OUT 

IN − TAP 

TAP 

IN 

IN 

OUT - TAP 

IN- 

TAP 

OUT 

TAP A - B OUT - TAP 

Figure 9. Influence of the initial permeability on 

the characteristics of the 15dB two-directional 

transformer in basic configuration, f=5 MHz. 

i 

OUT 

TAP A - B 

-40 

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 

µ 

i 

IN - OUT 

TAP 

i 

157 

Figure 10. The four-directional transformer in basic 


Fig. 10 shows the four-directional transformer in basic 

configuration [2]. The base for the construction of this 

transformer is similar as for the two-directional 

transformer. The four-directional transformer includes 

four coupled branches. The measured and calculated 

characteristics of the 18dB four-directional transformer are 

shown in Fig.11 and Fig.12 respectively. Similarly as for 

the unidirectional and two-directional transformers, an 

influence of the initial permeability on the parameters of 

the four-directional transformer in basic configuration was 

calculated. The results are presented in Fig.13. 

IN-OUT 

IN 

OUT 

OUT-TAP 

TAP A-B 

IN-TAP 

TAP 

Figure 11. Experimental characteristics of the 18dB fourdirectional 


i

-10 

-15 

-20 

-25 

-30 

-35 

-40 

-45 

0 100 200 300 400 500 600 700 800 900 1000 

f [MHz] 


5 

0 

-5 

Figure 12. Calculated characteristics of the 18dB fourdirectional 


0 

-5 

-10 

0 

-5 

-10 

-15 

-15 

-20 

-20 

-25 

-25 

-30 

-30 

-35 

IN 

IN - OUT 

OUT 

TAP A - B 

IN 

OUT 

OUT 

TAP A - B 

IN- 

TAP 

TAP A - B 

OUT - TAP 

OUT - TAP 

IN - TAP 

-35 

-40 

0 1000 2000 3000 4000 5000 6000 7000 8000 

TAP 

9000 10000 

-40 

0 1000 2000 3000 4000 

µ i 

5000 6000 7000 8000 9000 10000 

µ i 

Figure 13. Influence of the initial permeability on 

the performance of the 18dB four-directional 

transformer in basic configuration, f=5 MHz. 


The proposed multidirectional transformers, capable of 

substituting for a cascade of unidirectional transformers, 

offer: 

1.The possibility of dividing the signal into branches of 

identical coupling, which is very difficult to achieve in the 

corresponding cascades of unidirectional transformers. 

2. Uniform attenuation characteristic versus frequency. 

3. More economical solutions because of lower material 

consumption and lower cost of labour, especially in case 

of multidimensional transformers having four and more 

coupled branches. 

IN 

OUT - TAP 

IN- 

TAP 

TAP 

i 

IN- 

OUT 

IN - OUT 

158 

REFERENCES 

[1] D.I.Kim, M. Takahashi, K. Araki and Y. Naito, 

Optimum Design of Power Dividers with Ferrite 

Toroids for CATV and/or MATV Systems, IEEE 

Transactions on Consumer Electronics, vol. CE-29, 

no. 1, pp. 27-38, 1983. 

[2] D. Krzemieniecki, Modelling and Design of 

Directional Transformers, PhD Thesis under 

preparation, Faculty of Electronics, 

Telecommunications and Informatics, Gdansk 

University of Technology, Poland (in Polish). 

[3] D. Krzemieniecki, Analysis and Optimisation of a 

Wideband Directional Transformer, Electronics and 

Telecommunications Quarterly, 2005, 51, no. 1, 

pp.105-135. 

[4] D. De Zutter, J. Sercu and T. Dhaene, New 

approaches to increase the efficiency of the 

electromagnetic modelling of planar RF and 

microwave circuits, Department of Information 

Technology, Ghent University, 2004. 

http://www.win.tue.nl/masci-net/Events/DeZutter1.pdf 

pp. 6, 10, 18.


FABRICATION AND ELECTRICAL 

CHARACTERIZATION OF HIGH 

PERFORMANCE COPPER / POLYIMIDE 

INDUCTORS 

Marcelo B. Pisani (1, 2) , Cyrille Hibert (2) , Didier Bouvet (1) , Catherine Dehollain (1) and 

Adrian M. Ionescu (1) 

École Polytechnique Fédérale de Lausanne (EPFL), 

(1) Electronics Laboratory (LEG), ELB Building, Station 11, and 

(2) Center of Micro and Nanotechnology (CMI), BM Building, Station 17, 

CH-1015 Lausanne, Switzerland 

E-mail: marcelo.pisani@epfl.ch 

ABSTRACT 

This paper presents fabrication and RF characterization 

results of spiral inductors fabricated using a developed 

damascene-like thick-copper / polyimide process module. 

This module has low thermal budget and is compatible 

with current IC interconnect architectures, making it 

suitable for CMOS above IC integration of high quality 

factor passive devices. Thick, high-conductive copper 

layers associated with low κ polymers and high resistivity 

substrates can provide RF performances that cannot be 

achieved using conventional thin aluminum films on lowresistivity 

substrates. Peak quality factors of about 20 and 

exceeding 10 over a wide frequency range (1–6 GHz) are 

demonstrated, with a self-resonant frequency of about 

10 GHz. Measurements and equivalent circuit extraction 

results are also presented and discussed. 


There is a strong demand for high quality factor passive 

devices in communication applications in order to reduce 

power consumption, reduce noise and increase both 

operating frequency and usable bandwidth of the circuits 

[1, 2]. 

Inductors are key RF passive components that can be cointegrated 

with CMOS circuits using the local metal 

interconnects to produce spirals with inductances typically 

in the range of 1 to 100 nH. In spite of its simplicity, this 

approach produces low quality factor and low-bandwidth 

devices. Peak quality factors in the range of 5 to 10 and 

resonant frequencies that do not exceed 5 GHz are 

commonly reported using these technologies [3]. These 

poor performances are mainly related to the limited metal 

conductivity (in general, thin aluminum), substrate losses 

(in general low-resistivity substrate used in RF 

applications) and high capacitance between spiral interturns 

and between the spiral and the substrate (in general, 

SiO2 is used as inter-metal dielectrics). There is a number 

of techniques like the use of patterned ground shields 

159 

underneath the inductor [4] and special substrate contact 

techniques [5] than can be employed to increase the 

quality factor, but their impact in the final performance of 

the devices is limited since the main limitations come 

from the metal resistivity and thickness available for a 

given technology, associated with the low-resistivity 

silicon substrate losses. 

The use of copper / low κ or gold / low κ interconnects 

can improve the performance of the devices, providing 

metals with better conductivity and dielectrics with lower 

dielectric constant, reducing both series resistance and 

parasitic capacitances [1, 6]. The association of these 

materials with high-resistivity substrates [7] and other 

microfabrication techniques [8] can provide the best 

combination of fabrication techniques to achieve high RF 

performances. 

We report on a 5 µm-thick-copper / polyimide process 

module [9] on high resistivity silicon wafers (8 kΩ cm) 

capable of providing high quality factor inductors (in 

excess of 10) for broadband RF applications in the 

frequency range of 1 to 10 GHz, covering applications like 

ISM, GSM, Bluetooth and HIPERLAN. An equivalent 

circuit model is proposed and extracted for the fabricated 

devices. 

2. FABRICATION PROCESS AND 

CHARACTERIZATION 

METHODOLOGY 

2.1 Fabrication process 

Figure 1 shows schematically a cross-section view of the 

technology profile used to fabricate the inductors. The 

wafer is insulated from the devices using a 0.6 µm SiO 2 + 

0.2 µm Si 3N 4 stress-compensated bi-layer (a). Polyimide is 

then spun on (PI 2610 from Dupont, ε R = 2.9) at typical 

thicknesses of 1.5 µm (the thickness of the first metal 

layer). Polyimide film is then cured at 300 o C for 1 h.

A 0.3-µm thick sputtered SiO 2 layer is used as hard-mask 

to pattern the polyimide mold using an O 2-based plasma 

etch recipe (c, d). This process enables to fabricate vertical 

walls with up to 5 µm resolution for 10 µm-thick lines. A 

40 nm-thin tantalum layer and a 0.2 µm-thick copper layer 

are deposited by sputtering (e), working as diffusion 

barrier between copper and polyimide and as seed layer 

for the electroplating of a thick copper layer (f). The 

copper lines are then defined by a fast removal rate 

chemical-mechanical polishing step (CMP, g) capable of 

polishing films much thicker than the ones traditionally 

used in thin-metal layer interconnects. The successive 

repetition of these process steps (h-p) provide a second 

level of metal with a via in between. 


a 

b 

c 

d 

e 

f 

g 

Materials: 

Si N 3 4 

SiO 2 

Si 

h 

i 

j 

k 

l 

RF Ports 

m 

n 

o 

p 

M2 

M1 

Polyimide 4 - 8 µm 

ECP Cu 4 - 8 µm 

Ta 40 nm + Cu Seed 200nm 

Figure 1. Technological process flow used to 

fabricate polyimide embedded thick-copper spiral 

inductors. 

1.1 RF characterization method 

Fabricated inductors were measured using a Cascade 

Microtech prober coupled to an HP 8719D vector network 

analyzer, operating in the 0.05 to 13.51 GHz frequency 

range. The measurement probes have a coplanar 

waveguide ground-signal-ground configuration (GSG), 

with a 150 µm in-line pitch. They are connected to the 

analyzer using low-loss coaxial cables and calibrated 

using an alumina substrate for the short circuits on port 1 

and 2, 1 ps through, open-circuit and 50 Ω load references 

(ISS/SOLT calibration technique). 

There are a number of quality factor definitions, 

depending on the device application and on the circuit 

parameters of interest [10]. For isolated devices operating 

160 

below the self-resonant frequency, usually measured and 

calibrated S-parameter data are converted into Yparameter 

data and equivalent inductance L and quality 

factor Q, as a function of the frequency, are calculated as: 

imag( 

1/ 

y11) 

L = 

2π 

f 

(1) and 

imag( 

1/ 

y11) 

Q = 

real( 

1/ 

y ) 

(2), 

11 

where f is the frequency and 1/y 11 is the equivalent 

complex impedance of port 1 when port 2 is connected to 

the ground. 

The resonant frequency is defined when the equation (2) 

goes to zero, which means that the device behaves as a 

capacitor above this frequency. 

The same extraction procedure can be applied over Sparameter 

data obtained from electromagnetic field solver 

simulators. In this work, we have used ASITIC [10] to 

make initial performance estimation and design of the 

spirals. 

For circuit simulation purposes, it is necessary to have a 

broadband equivalent circuit that fits the measured data. 

This π-equivalent circuit is showed in figure 2 [2]. 

Figure 2. Equivalent 2-port π circuit used to 

model the fabricated inductors. 

In this model, L S accounts for the series self-inductance 

of the device. R S represents the series inductor resistance 

term, related directly to the ohmic losses in the metal 

tracks. This resistance can be reduced using wider and 

thicker tracks, but this reduction trend is limited in very 

high frequencies due to the skin effect and proximity 

effect current confinement [11]. At the same time, the use 

of thicker and wider tracks will also increase the 

associated parasitic capacitances due to the increase in the 

device area. C INS1,2 are associated with the spiral-wafer 

insulation and can be reduced using lower κ and thicker 

films for this layer. R SUB1,2 and C SUB1,2 are associated with 

the silicon substrate. These parameters are roughly 

proportional to the inductor surface and are strongly 

dependent of the substrate resistivity. The use of highresistivity 

wafers contribute to increase R SUB1,2 values and 

provide at the same time higher quality factors and higher 

self-resonant frequencies.

2. RESULTS AND DISCUSSION 

Figure 3 shows a top view of a typical fabricated spiral 

inductor with the RF prober padding for the RF electrical 

characterization. Typically, fabricated inductors have 250 

to 400 µm external diameter, track widths between 10 and 

40 µm, track spacing between 5 and 20 µm, and 

inductance values between 1 and 10 nH. 

Figure 4 shows a focused ion beam (FIB) cross-section 

view of a stacked 1.5-µm metal 1 / 3-µm via / 5-µm metal 

2 structure on the insulated silicon wafer. The interface 

between the metal levels is clean and smooth, with a 

contact resistance that does not exceed 35 mΩ/via for a 

minimum via size of 10 x 10 µm 2 . The walls are well 

defined and vertical, and good electroplating filling can be 

observed for via size down to 2.5 µm. 

Figure 3. Top view of a fabricated square spiral 

with RF pads (each pad is a 100 µm square). 

The resistivity of the electroplated copper layers is 2.0 ± 

0.1 µΩ cm, measured by the four-point probe technique 

for thicknesses between 1 and 8 µm. 

The CMP dishing and erosion is limited to about 0.2 µm, 

which can be considered an acceptable value for a 5 µm 

thick structure. 

Figure 4. FIB cross-section view of a double 

metal layer stacked structure. 

Figures 5a and 5b show the measured and equivalent 

circuit results for a 2.7 nH octagonal inductor with an 

external diameter of 400 µm, 2.5 turns, 30-µm track width 

and 10 µm of track spacing. This inductor was optimized 


161 

to work in a 2.45-GHz voltage controlled oscillator circuit 

(VCO). This device was fabricated on top of a highresistivity 

4-inch silicon wafer (8 kΩ cm). The Cu / low κ 

process associated with the high-resistivity substrate are 

capable of providing quality factors in excess of 10 over a 

wide bandwidth (1 to 6 GHz). 

In general, measured results have peak quality factors 

and self-resonant frequencies 15 – 30 % below the ones 

predicted using ASITIC field solver for the inductors in 

the 1 – 10 nH range fabricated using this technology. We 

believe that this discrepancy is due on the one hand to an 

overestimation in the low frequency inductance value and 

on the other hand to the inaccurate modeling of the 

parasitics in frequencies beyond the ones for that tool were 

calibrated to be used (around 1–3 GHz) [10]. Typical 

simulations using slow electromagnetic analysis to 

provide more precise results take many hours of 

computation and frequently present convergence 

problems, suggesting that, for the predictive modeling of 

inductors using low-loss substrates and thick metal layers, 

a more advanced electromagnetic simulation tool is 

probably needed. 

Table 1 shows the extracted equivalent circuit model for 

the measurements. The results were obtained by a nonlinear 

least-squares fit using the frequency range below the 

self-resonant frequency. The quality of the fit is sufficient 

for SPICE-like circuit simulations using the device. 

The use of high-resistivity substrates reflects especially 

in the substrate losses (modeled by RSUB1 and RSUB2 resistances). Typically, the same spiral on top of a lowresistivity 

substrate would present equivalent resistance 

values in the 20 – 200 Ω range. The use of the highresistivity 

substrates permits an improvement of a factor 

from 5 to 20 in this parameter. 


We have designed and fabricated inductors with 

experimental peak quality factors around 20 and quality 

factors in excess of 10 over a wide operating frequency 

range (1 – 6 GHz). Self-resonant frequency of about 

10 GHz is also demonstrated, making a same inductor 

device usable in multi-band circuits, which is in advance 

compared to state-of-the-art. The developed process using 

low-resistive thick copper / polyimide and performed on 

top of high-resistivity substrates delivers performances 

that cannot be achieved using standard aluminum / SiO 2 

RF-IC technologies on top of low-resistivity substrates. 

The fabrication process is compatible with standard above 

IC interconnects and presents low thermal budget, making 

it useful for direct co-integration with CMOS circuits. 

Broadband equivalent circuit model suitable for SPICElike 

simulation below the self-resonant frequency has been 

extracted by fitting the measured performances.

Inductance (nH) 

20 

10 

-10 

-20 


0 

Ldc=2.7nH 

Measurement 

Fitted model 

0 2 4 6 8 10 12 14 

Frequency (GHz) 

Figure 5a. Measured and equivalent circuit 

effective inductance for the 2.7 nH octagonal 

inductor (eq. 1). 

Quality Factor 

20 

15 

10 

5 

0 

-5 

-10 

Measured 

Fitted 

0 2 4 6 8 10 12 14 

Frequency (GHz) 

Figure 5b. Measured and simulated quality factor 

results for the 2.7 nH inductor (eq. 2). 

LS = 2.7 nH 

RS = 1.3 Ω 

CP = 18 fF 

CINS1 = CINS2 = 160 fF 

RSUB1 = RSUB2 = 580 Ω 

CSUB1 = CSUB2 =132 fF 

Peak quality factor: 18.9 @ 2.50 GHz 

Self-resonant frequency: 10.2 GHz 

Table 1. Equivalent π-circuit model parameters 

for the 2.7 nH inductor (figure 2), calculated peak 

quality factor and self-resonant frequency (eq. 3). 

162 

Acknowledgments 

This work has been supported by the IST Wide-RF EU 

project (IST-2001-33286) and by the Swiss OFES project 

01.0308. Many thanks are due to the EPFL-CMI staff for 

the technical and clean room facilities support. 

4. REFERENCES 

[1] Steinbrüchel and B. L. Chin. Copper interconnect 

technology. SPIE Press, Washington, 2001. 

[2] T.H. Lee and A. Hajimiri, Oscillator phase noise: a 

tutorial”, IEEE Journal of Solid-State Circuits, vol. 

35, no. 3, pp. 326-336, 2000. 

[3] P. Yue and S. S. Wong, Physical modeling of spiral 

inductors on silicon, IEEE Transactions on Electron 

Devices, vol. 47, n. 3, pp. 560-568, 2000. 

[4] C. P. Yue and S. S. Wong, "On-chip spiral inductors 

with patterned ground shields for Si-based RF IC's", 

IEEE Journal of Solid-state Circuits, vol. 33, n. 5, 

1998, pp. 743-752. 

[5] J.N. Burghartz, A.E. Ruehli, K.A. Jenkins, M. 

Soyuer, D. Nguyen-Ngoc, Novel substrate contact 

structure for high-Q silicon-integrated spiral 

inductors, Proc. of the International Electron Devices 

Meeting, pp. 55-58, 1997. 

[6] I.J. Bahl, “High-performance inductors”, IEEE Trans. 

on Microwave Theory and Techniques, vol. 49, n. 4, 

2001, pp. 654-664. 

[7] A.C. Reyes, S.M. El-Ghazaly, S. Dorn, M. Dydyk, 

D.K. Schroder, and H. Patterson, “High resistivity Si 

as a microwave substrate”, Proc. of the 46th 

Electronic Components and Technology Conference, 

May 1996, pp. 382 -391. 

[8] J.M. López-Villegas et al, “Study of integrated RF 

passive components performed using CMOS and Si 

micromachining technologies”, J. Micromech. 

Microeng, vol. 7, n. 3, Sept. 1997, pp. 162-164. 

[9] M. B. Pisani, C. Hibert, D. Bouvet, P. Beaud and A. 

M. Ionescu, Cooper/polyimide fabrication process for 

above RF IC integration of high quality factor 

inductors, Microelectronic Engineering, vol. 73-74, 

pp. 474-479, 2004 

[10] A.M. Niknejad and R.G. Meyer, Analysis, Design 

and Optimization of Spiral Inductors and 

Transformers for Si RF IC’s, IEEE Journal of Solid- 

State Circuits, vol. 36, no. 10, 1998. 

[11] W.B. Kuhn and N.M. Ibrahim, Analysis of current 

crowding effects in multiturn spiral inductors, IEEE 

Transactions on Microwave Theory and Techniques, 

vol. 49, no. 1, pp. 31-38, Jan. 2001.


DESIGN OF ENHANCED MULTI-BIT 

DISTRIBUTED MEMS VARIABLE TRUE-TIME 

DELAY LINES 

ABSTRACT 

This paper shows how periodic structure theory can be 

used to precisely model and design conventional 

distributed MEMS variable true-time delay lines, so as to 

deduce an improved topology for multi-bit operation. 

Results for the new configuration are then presented 

along with its conventional counterpart performances, 

highlighting the advantage of the new configuration in 

terms of mismatch and delay distortion. 


This paper presents new contributions to distributed 

MEMS transmission lines (DMTL) working on the 

principle of MEMS capacitors loading a coplanar 

waveguide [1]. The performance of such DMTL in terms 

of differential delay over losses and stability were 

significantly improved by increasing the loading 

capacitance ratio by replacing the loading analog 

capacitors by digital ones [2]. However, this results in 

significant degradation in the matching properties for the 

DMTL, which is a very limiting factor for multi-bit digital 

DMTL. This mismatch is not only detrimental in terms of 

reflected energy but also results in distortion in the delay. 

The main reason for implementing a DMTL is to obtain a 

constant delay over a very wide bandwidth [3]. Therefore, 

it is not possible to use conventional, frequencydependant, 

matching techniques. Even if operated over a 

relatively narrow band, the matching circuits would have 

to be reconfigurable, and such complicated structures 

would introduce parasitics effect detrimental to the DMTL 

performances. Finally, a tapered match requires a length 

comparable with the wavelength. This solution is 

therefore too space consuming for MMIC applications and 

would also increase the overall insertion loss of the 

DMTL. 

We propose here a new topology for such multi-bit 

DMTL. Compared with the usual way to achieve multi-bit 

operation, namely by cascading similar line sections of 

different length, we show that interlacing bridges of 

different capacitance values (corresponding to the 

different bits) allows improving the matching properties of 

the DMTL, which also reduces the oscillations in the 

delay. 

J. Perruisseau-Carrier, R. Fritschi, A.K. Skrivervik 

Ecole Polytechnique Fédérale de Lausanne (EPFL) 

Station 11, 1015 Lausanne, Switzerland 

E-mail: julien.perruisseau@epfl.ch 

163 

The periodic structure approach so as the new interlaced 

bits topology are directly applicable to other type of 

periodic variable true-time delay lines (V-TTDL), such as 

[4], and could also be of use for other types of MEMS 

periodic structure (e.g., [5]). 

This paper is organized as follows. First, we briefly show 

how the periodic approach, along with a comprehensive 

circuit model, allows modeling precisely the conventional 

DMTL. An in-depth description of the method is available 

in [3]. The approach is then applied to show why the new 

topology for multi-bit DMTL is more performing in terms 

of matching. Finally, a comparison between the two types 

of DMTL is carried out. 

2. FINITE PERIODIC STRUCTURE 

A DMTL is a particular one-dimensional periodic 

structure whose unit cell consists in a MEMS shunt 

capacitor loading a coplanar waveguide (CPW). Such a 

periodic device can be modeled by cascading N identical 

two-port networks, each of those corresponding to a unit 

cell of the structure. If a cell in the structure is 

symmetrical and defined by its transmission matrix (hence 

the four ABCD parameters named here A cell=D cell, B cell 

and C cell), it can be shown that the transmission matrix of 

the complete structure is [3]: 

( Nγequd) Zequ ( Nγequd) ( Nγequd) ( Nγequd) ⎡ cosh sinh ⎤ 

N ⎢ ⎥ 

TPS= Tcell 

=⎢1 ⎥ (1) 

⎢ sinh cosh 

Z 

⎥ 

⎣ equ 

⎦ 

where γequ and Zequ are the periodic transmission lines 

equivalents of the periodic structure, defined in the case of 

symmetrical cells by: 

( ) 

cell 

cosh γ equd = Acell 

Zequ 

Ccell 

B 

=± (2),(3) 

The transmission matrix given by (1) is exactly equivalent 

to the transmission matrix of a continuous line of length 

Nd, with characteristics γ equ and Z equ, with the restriction 

that the voltages and currents are only defined at the 

connections of the periodic cells. As a result, conventional 

transmission line theory can be used for the design and 

analysis of DMTL, provided that the DMTL is described 

by its periodic structure equivalent parameters γ equ and 

Z equ. This calculation is exact on the basis of the circuit

model and does not require any assumption on the number 

of cells of the periodic structure [3]. 

For simplicity, only the symmetrical case was considered 

here. However, the new topology presented in section 4 is 

made of asymmetrical cells. In this case, a periodic 

structure model still applies and the equivalents (2),(3) are 

written in a more general way as: 

1 

cosh ( γ equd) = ( Acell + Dcell 

) 

(4) 

2 

Z 

equ 

=+ 

−2Bcell 

A − D ± A + D −4 


( ) 2 

cell cell cell cell 

(5) 

It is noticeable that in this case, the two solutions for Z equ, 

which correspond to the two different directions of 

propagation along the structure, do not only differ by their 

sign. 

3. CONVENTIONAL V-DMTL 

3.1 Modeling and design 

The comprehensive circuit model shown in Fig. 1, so as 

design methods of DMTL based on the periodic structure 

modeling are described by the authors in [3] and have 

been used here to model and design DMTL such as 

presented in [2]. 

Figure 1: Circuit model for a cell in a 

conventional DMTL 

3.2 Results 

Various DMTL have been built on the fabrication process 

presented in [3]. We present here the measurements for 

another digital design, compared with its circuit model 

results. The measured and simulated delays, insertion loss 

and matching results are presented in Fig. 2 and 3. A good 

agreement is observed and validates the model of Fig. 1. 

The parameters of the line are: differential delay ∆D = 

18ps, Bragg frequency f B = 80GHz and capacitance ratio 

C r = 2.3. The numerical values for the circuit model are 

CM = 27fF, C F = 29fF, N = 26 cells of d=302µm, R P = 1Ω, 

LP = 50pH, ∆L S = -2pH and ∆R S = 0.1Ω and 0.15Ω at 

20GHz, in the up and down states, respectively. 

4. INTERLACED BITS V-DMTL 

4.1 Concept and modeling 

When multi-bit operation is required for DMTL (N > 1 

bits), the usual approach is to cascade a number N of 

164 

Phase Delay [ps] 

|s 11 | [dB] 

110 

100 

90 

80 

20V 

70 

0 5 10 

f [GHz] 

15 20 

DMTL as presented in section 3, each of those providing a 

delay corresponding to a bit weight [2]. This structure is 

schematically depicted in the left of Fig. 4 in the case N = 

2 and will always be referred to as CB-DMTL for 

cascaded bits DMTL. On the right of the figure, we 

propose a new structure where the bridges actuated by the 

different bits are not cascaded, but interlaced. This 

structure will be referred to as the interlaced bits DMTL 

(IB-DMTL). Both structures are operated in four different 

states determined by the value of each control bit, named 

AB in the CB-DMTL case and CD in the IB-DMTL case 

(see Fig. 4). These different states will be referred to in 

this document using the bit values, i.e. 00, 01, 10 and 11. 

The bits ‘0’ and ‘1’ mean that the corresponding MEMS 

capacitors are in the ‘up’ and ‘down’ states, respectively. 

The evolution from CB to IB-DMTL does not simply 

consist in operating a single section of the CB-DMTL 

with ‘four-state MEMS capacitors’ since there are line 

sections between the two types of bridges C and D, in 

order to limit the distortion in the high frequencies (Bragg 

frequency). It is also noticeable that the IB-DMTL cannot 

be obtained straightforwardly from a CB-DMTL design 

but requires a dedicated design procedure to appropriately 

control the differential delays. 

In order to understand the main difference between both 

DMTL types, let us qualitatively study the equivalent 

characteristic impedances of the periodic structures. We 

first consider the case of the CB-DMTL. In order to 

0V 

Figure 2: Absolute phase delay (Plain line: 

measurement, dotted: circuit model) 

0 

-10 

-20 

-30 

20V 

0V 

0V 

20V 

-40 

0 5 10 

f[GHz] 

15 

-5 

20 

0 

-1 

-2 

-3 

-4 

|s 21 | [dB] 

Figure 3: Insertion loss and matching (Plain line: 

measurement, dotted: circuit model)

minimize the mismatch in the four states altogether, the 

equivalent characteristic impedance of each section in the 

state 0 (high impedance) are placed above the reference 

impedance Z ref. In the state 1, the impedance is decreased 

and should now be below Z ref. This process is illustrated 

by Fig. 5 and Fig. 6 and explained in detail in [3]. In the 

case of the IB-DMTL, there is only one periodic structure, 

but with four different characteristic impedances, which 

will be ‘placed’ by the design algorithm as schematically 

shown in the right of Fig. 6. The worst case in terms of 

matching in the CB-DMTL occurs when the states 01 or 

10 are operated since a significant equivalent impedance 

discontinuity occurs at the interface between both bit lines 

(Fig. 5, Fig. 6). This problem is solved by the IB-DMTL 

structure since there is no discontinuity in the line in terms 

of equivalent impedance, and that the impedance in the 

state 01 and 10 is close to the reference impedance (Fig. 6, 

right). 

4.2 Design 

The design of the IB-DMTL was done using a method 

similar to the one used for the CB-DMTL but was further 

developed so as to obtain quasi equals differential delays 

between the four states. The method was fully 

programmed in Matlab and provides all parameters of the 

DMTL, including the four capacitance values 

corresponding to the two types of bridge in each state. 

4.3 Results 

This section compares the performances of the two types 


Cascaded Bits (CB-DMTL) Interlaced Bits (IB-DMTL) 

Figure 4: Topologies and unit cell circuits : CB-DMTL (left) and IB-DMTL (right) 

Figure 5: Equivalent lines model for the CB-DMTL (left) and IB-DMTL (right) 

Figure 6: Illustration of the matching process for the CB-DMTL (left) and IB-DMTL (right) 

165 

of DMTL. For fair comparison, the designs were made 

using the same material, delay, and bandwidth. The results 

obtained from the model used for the design are verified 

by full-wave simulation with Ansoft HFSS v9.2. In Fig. 8 

and Fig. 9 are respectively plotted the absolute delay and 

input return loss obtained. It is first observed that the 

circuit model and the full-wave simulation are in very 

good agreement. 

As can be seen in Fig. 9 and Table 1, the CB-DMTL and 

IB-DMTL exhibit approximately the same input return 

loss in states 00 and 11 as there is no mismatch at the 

transition between the two bit sections in the CB-DMTL. 

However, in the states 01 and 10, an important mismatch 

occurs in the cascaded type, since two lines of impedances 

Figure 7: 3D view of the designed IB-DMTL. 

The small fixed capacitor of one of the bridge is 

realized by the coupling through the silicon 

substrate alone.



85 

80 

75 

70 

85 

80 

44Ω and 56.4Ω are cascaded. This problem does not occur 

in the IB-DMTL case, where the states 01 and 10 

correspond to intermediate impedances (52.5 and 46.7Ω), 

hence a low input return loss. As mentioned previously, 

some oscillations in the delay are due to the mismatch and 

are therefore lower in the IB-DMTL case. 

Another important parameter for DMTL is the insertion 

loss and it is seen that both configurations exhibit 

approximately the same performance from this point of 

view. The reason is the predominance of ohmic losses 

over mismatch losses in the overall insertion losses. 


CB-DMTL 

IB-DMTL 

75 

70 

state 00 

state 01 

state 10 

state 11 

65 

4 8 12 

f [GHz] 

16 20 

Figure 8: Delays of the CB-DMTL and IB- 

DMTL (plain: HFSS simulation, dotted: lumped 

model). 

5. CONCLUSION 

We demonstrated the advantage of the IB-DMTL structure 

over its usual CB-DMTL counterpart from matching and 

delay distortion points of view, in a two bit operation. The 

cost of this improvement is an increased design 

complexity. 

6. REFERENCES 

[1] N. S. Barker and G. M. Rebeiz, "Optimization of 

distributed MEMS transmission lines phase shifters, 

U-band and W-band designs," IEEE Trans. 

Microwave Theory Tech., vol. 48, no. 11, pp. 1957- 

1966, Nov. 2000. 

[2] J. Hayden and G. Rebeiz, "Very low-loss distributed 

X-band and Ka-band MEMS phase shifters using 

166 

|s 11 | [dB] 

|s 11 | [dB] 

-5 

-10 

-15 

-20 

-25 

-5 

-10 

-15 

-20 

-25 

CB-DMTL 

IB-DMTL state 00 

state 01 

state 10 

state 11 

4 8 12 

f [GHz] 

16 20 

Figure 9: Input return loss of the CB-DMTL and 

IB-DMTL (plain: HFSS simulation, dotted: lumped 

model). 

Table 1: Comparison of the two types of DMTL in terms 

of the equivalent impedances in [Ω], the max. of |S 11| and 

the min. of |S 21|, in [dB]. 

CB-DMTL IB-DMTL 

Zequ,A Zequ,B S11max S21min Zequ S11max S21min 

00 56.4 56.4 -19 -0.7 56.7 -18 -0.8 

01 56.4 44 -12 -0.7 52.5 -25 -0.7 

10 44 56.4 -12 -0.8 46.7 -23 -0.7 

11 44 44 -17 -0.7 44.2 -19 -0.6 

metal-air-metal capacitors," IEEE Trans. Microwave 

Theory Tech., vol. 51, no. 1, pp. 309-314, Jan. 2003. 

[3] J. Perruisseau-Carrier, R. Fritschi, P. Crespo-Valero, 

and A. K. Skrivervik, "Modeling of periodic 

distributed MEMS, application to the design of 

variable true-time delay lines," IEEE Trans. 

Microwave Theory Tech., In Review, 2005. 

[4] A. S. Nagra and R. A. York, "Distributed analog 

phase shifters with low insertion loss," IEEE Trans. 

Microwave Theory Tech., vol. 47, no. 9, pp. 1705 - 

1711, Sept. 1999. 

[5] H.-T. Kim, J.-H. Park, S. Lee, S. Kim, J.-M. Kim, 

Y.-K. Kim, and Y. Kwon, "V-band 2-b and 4-b lowloss 

and low-voltage distributed MEMS digital phase 

shifter using metal-air-metal capacitors," IEEE 

Trans. Microwave Theory Tech., vol. 50, no. 12, pp. 

2918 - 2923, Dec. 2002.


INDUCTANCE CALCULATION OF 

THICK-METAL INDUCTORS 

A. Scuderi 1 , T. Biondi 2 , E. Ragonese 1 , G. Palmisano 1 

1 Università di Catania, Facoltà di Ingegneria, DIEES, Viale A. Doria 6, 95125 Catania, Italy 

2 STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy 

E-mail: ascuderi@diees.unict.it 

ABSTRACT 

In this paper, the analysis and modeling of thick-metal 

spiral inductors are addressed. The accuracy of a 2.5 D 

electromagnetic simulator is first validated by comparison 

with on-wafer experimental measurements. Simulation 

results are then employed to investigate the effect of metal 

thickening on inductor performance. The inductance 

decrease due to metal thickening is modeled by using a 

modified current-sheet expression. The proposed formula 

achieves higher accuracy compared to the original one 

revealing errors below 5% even for thickness-to-width 

ratio up to 2.5. 


During the last years, spiral inductors became key 

components in silicon-based technologies to achieve high 

integration levels and reduce fabrication costs. However, 

their quality may strongly affect the performance of most 

RF circuit blocks. Indeed, silicon integrated inductors 

suffer from both substrate and metal losses. To rise the 

quality factor, increasing the metal thickness and replacing 

aluminum with copper were profitably investigated. 

Despite several experimental results, only few works faced 

the impact of metal thickening on the design, optimization 

and modeling of spiral inductors [1]. Moreover, much 

interest was focused on the increase of quality factor 

overlooking the reduction of inductance. Although this 

phenomenon is taken into account in many expressions 

reported in literature [2]-[4], their validation was only 

limited to medium-thickness inductors with thicknessto-width 

ratios below 0.25. 

In this paper, the inductance decrease of thick-metal 

silicon integrated inductors is investigated. A closed-form 

expression for low-frequency inductance calculation is 

also proposed. The accuracy of ADS Momentum on the 

prediction of inductor performance is demonstrated by 

comparing electromagnetic (EM) simulations with 

measurements available from previous work [5]. The 

proposed equation for inductance calculation is validated 

in a wide range of geometrical parameters and thicknessto-width 

ratios by means of EM simulations. 

2. EM SIMULATIONS 

In order to investigate the effect of metal thickness on the 

low-frequency inductance of circular spirals, the improved 

capabilities of a commercial 2.5-D EM simulator, ADS 

167 

Momentum by Agilent Technologies, have been exploited. 

The accuracy achievable with Momentum and the 

simulator setup were properly validated by taking 

advantage of several integrated inductors made available 

by previous research [5]. The employed fabrication 

technology, whose detailed cross-section is shown in 

Fig. 1, allows only three Al-metal layers. The Metal 3 is a 

3-µm thick metal layer and is used for the spiral, while the 

Metal 2 and the Metal 1 are two thinner metal layers used 

for the underpass and the ground plane, respectively. A 

radial pattern of oxide trench was adopted to break 

induced current loops within the buried layer shielding the 

spiral from the underlying substrate. Buried layer contacts 

were placed at the edge of the ground plane at a distance 

of 50 µm from the spiral. 

Figure 1. Fabrication technology cross-section. 

Integrated inductors have turn number (n) from 1.5 to 5.5, 

metal width (w) from 6 to 20 µm, inner diameter (din) from 

50 to 150 µm, and inter-metal spacing (s) of 4 µm, which 

results in inductances ranging from 0.3 to 8.6 nH covering 

most of the values employed in the design of silicon RF 

ICs. The characterization was carried out by exploiting a 

5-step de-embedding technique. A micrograph of an 

integrated inductor is shown in Fig. 2. 

Fig. 3 depicts the setup employed for electromagnetic 

simulations including the ground plane, the underpass and 

the substrate layers underlying the spiral (not visible). In 

spite of the old version of Momentum, the simulator 

allows an expansion of the metal thickness to estimate 

inductance and quality factor more accurately. The 

soundness of Momentum simulations is demonstrated in 

Figs. 4 and 5 where simulation results and measurements 

of a 3.7-nH and 2-nH inductors are compared. The 

simulator predicts the low-frequency inductance and the 

self-resonance frequency with a relative error about 1 %

and 3 %, respectively. Indeed, the quality factor is 

estimated with a maximum relative error of 9 % 

demonstrating the simulator accuracy in the prediction of 

frequency dependence of series losses. 

G 

S S 

G 

Oxide 

trench 


Metal 3 

Metal 1 

Metal 2 

Buried layer contacts 

Figure 2. Micrograph of an integrated inductor. 

ground plane 

ground plane 

G 

G 

buried layer contacts 

underpass 

buried layer contacts 

Figure 3. Electromagnetic simulation setup. 

Figure 4. Simulated and measured inductance and 

quality factor of a 3.7-nH inductor (n = 3.5, 

w =6 µm, and d in = 150 µm). 

168 

Figure 5. Simulated and measured inductance and 

quality factor of a 2-nH inductor (n = 2.5, 

w =14 µm, and d in = 100 µm). 

For the purpose of this work, the validation of 

low-frequency inductance estimation has to be accurately 

verified. Although the inductance decreases owing to skin 

and proximity effects, excellent agreement is found 

especially at medium frequencies, where the current 

distribution inside the conductor satisfies the current sheet 

approximation (i.e., when the skin depth is small 

compared to the thickness and width of the conductor). 

Moreover, relative errors of low-frequency inductance for 

a large number of simulated and measured devices are 

reported in Fig. 6 as a function of inductance. Maximum 

and average errors of measurements with respect to 

electromagnetic simulations are 4.5% and less than 3%, 

respectively. This result demonstrates the simulator 

capability to estimate the inductance value for various 

widths, turn numbers, and diameters. 

Figure 6. Relative error between simulated and 

measured low-frequency inductance. 

Moreover, the accuracy of Momentum has been 

demonstrated in [6] for a thickness different from this 

work, since EM simulations were compared with on-wafer 

experimental measurements of 5-µm-thick inductors.

The simulator provides adequate accuracy and moderate 

complexity and simulation time with respect to full 3D 

electromagnetic tools. This is particularly time-saving 

when several inductors have to be simulated, as in this 

case. 

3. INDUCTANCE MODELING 

The coil inductance has been calculated from EM 

simulations of open-air spirals (i.e., separated by a 5-mm 

air cushion from the underlying ground plane). The 

investigated structures have turn number from 1.5 to 5.5, 

inner diameter from 50 µm to 150 µm, and metal width 

from 6 µm to 20 µm. The geometrical parameters of all 

investigated structures are detailed in Table I. For each 

structure, the metal thickness was varied from 3 µm to 

15 µm. This results in thickness-to-width ratios from 0.15 

to 2.5, which thoroughly exceeds the range commonly 

employed in the design of RF ICs. 

Table. I. Simulated inductors 

Name 

Turn 

number 

Metal width 

[µm] 

Inner diameter 

[µm] 

A 5.5 6 50 

B 4.5 6 100 

C 3.5 10 100 

D 3.5 14 50 

E 1.5 14 150 

F 4.5 14 150 

G 1.5 18 100 

H 2.5 20 150 

By applying the current sheet approximation [4], the 

inductance of spirals with finite-thickness conductor can 

be expressed by (1) 

2 

µ ⋅ n ⋅ d avg 1 ⎛ t ⎞ 

L = L0 

− α ⋅ 

⋅ ⋅ ln⎜1 

+ ⎟ , (1) 

2 n ⎝ w ⎠ 

where L0 is the inductance value that competes to a 

zero-thickness spiral, µ is the magnetic permeability of air, 

davg is the average diameter computed as (din + dout) / 2. 

The correction term α, equal to 1 in the original 

formulation of (1), has been introduced to provide more 

accurate inductance calculations for spirals with large 

values of n and t / w, as will be fully explained in the 

following. A closed-form expression to calculate L0 was 

already given in [4], and extended to sub-nH inductances 

in [7], hence only the thickness-dependent term of (1) will 

be dealt with in this paper. 

Figs. 7, 8 and 9 show the relative inductance decrease, 

calculated as 100 · (1 – L / L0), of three spirals with different 

geometrical layout parameters as a function of the 

thickness-to-width ratio. Data calculated using both the 

original (α = 1) and corrected version of (1) are also 


169 

Relative inductance decrease [%] 



24 

20 

16 

12 

8 

4 

0 

Momentum simulation 

Expression (1) 

Expression (1) corrected 

0.0 0.5 1.0 1.5 2.0 2.5 3.0 

Thickness-to-width ratio 

Figure 7. Relative inductance decrease as a 

function of the thickness-to-width ratio (type A). 

20 

16 

12 

8 

4 




0 

0.0 0.2 0.4 0.6 0.8 1.0 1.2 



function of the thickness-to-width ratio (type D). 

20 

16 

12 

8 

4 




0 

0.0 0.2 0.4 0.6 0.8 1.0 



function of the thickness-to-width ratio (type G).

eported. It can be observed that the original expression 

underestimates the inductance reduction due to the 

increased metal thickness in all considered cases, 

moreover the discrepancies between EM simulations and 

calculations become larger as the turn number increases. 

As an example, relative errors increase from 16% to more 

than 30% as the turn number raises from 1.5 to 5.5 even 

for thickness-to-width ratios smaller than 1. The 

formulation of (1) derives from the consideration that 

increasing the metal thickness only influences the 

self-inductance of the coil (proportional to n) while 

leaving unchanged the mutual inductance contributions 

(proportional to n 2 – n). However, questions might be 

raised on the validity of these assumptions in light of the 

above results. To improve the accuracy of (1) especially 

for large values of n the correction term α was introduced. 

By comparing analytical calculations with EM simulations 

of spirals with different geometrical parameters it emerged 

that the dependence of (1) on the turn number has to be 

slightly modified in order to take into proper account the 

influence of the metal thickness on the mutual inductance 

contributions. This can be accomplished using an 

expression of the form a·n b , with a and b as fitting 

parameters, which allows accurate inductance modeling 

still maintaining the physics-based nature of (1). The 

resulting expression of α is reported in (2) 

0. 

17 

α = 1. 

13⋅ 

n . (2) 

Figs. 7, 8 and 9 demonstrate that the introduction of α in 

(1) substantially reduces calculation errors with respect to 

the original expression. Indeed, the corrected formula is in 

close agreement with EM simulations providing errors 

smaller than 5% for turn number up to 5.5 and 

thickness-to-width ratio up to 2.5. 

Finally, Fig. 10 shows the simulated and calculated 

relative inductance decrease of all investigated spirals for 

t = 15 µm. Comparisons with EM simulations prove the 

excellent geometrical scalability of the modified 

expression and the improvement with respect to the 

original one. Indeed, maximum and average errors with 

respect to EM simulations are reduced from 37% to 9% 

and from 27% to 3%, respectively. 


4. CONCLUSION 

A modified current-sheet expression was proposed to 

model the inductance decrease due to metal thickening. It 

achieved higher accuracy and improved geometrical 

scalability compared to the original one. The proposed 

expression revealed excellent accuracy over a wide range 

of inductor geometries and thickness-to-width ratio. 

170 


30 

25 

20 

15 

10 

5 

0 

Momentum 



A B C D E F G H 

Figure 10. Relative inductance decrease of all investigated 

spirals for t = 15 µm. 

5. REFERENCES 

[1] Y.-S. Choi and J.-B. Yoon, “Experimental analysis of 

the effect of metal thickness on the quality factor in 

integrated spiral inductors for RF ICs,” IEEE 

Electron Device Lett., vol. 25, pp. 76-79, Feb. 2004. 

[2] S. Jenei, et al, “Physics-based closed-form 

inductance expression for compact modelling of 

integrated spiral inductors,” IEEE J. Solid-State 

Circuits, vol. 37, pp. 77-80, Jan. 2002. 

[3] C. P. Yue and S. S. Wong, “Physical modeling of 

spiral inductors on silicon,” IEEE Trans. Electron 

Devices, vol. 47, pp. 560-568, Mar. 2000. 

[4] S. S. Mohan, “The design, modeling and optimization 

of on-chip inductor and transformer circuits,” Ph.D. 

thesis, Stanford University, Dec. 1999. 

[5] A. Scuderi, T. Biondi, E. Ragonese and G. 

Palmisano, “A lumped scalable model for silicon 

integrated spiral inductors,” IEEE Trans. Circuits 

Syst. I, vol. 51, pp. 1203-1209, June 2004. 

[6] Y. Tretiakov, et al, “Improved modeling accuracy of 

thick metal passive SiGe/BiCMOS components for 

UWB using ADS Momentum,” in IEEE RFIC Symp. 

Digest, June 2004, pp. 461-464. 

[7] T. Biondi, A. Scuderi, E. Ragonese, and G. 

Palmisano, “Characterization and modeling of 

sub-nH integrated inductances,” in Proc. IEEE IMTC 

2004, May 2004, pp. 1998-2002.


CANTILEVER BASED MEMS FOR MULTIPLE MASS SENSING 

María Villarroya, Jaume Verd, Jordi Teva, Gabriel Abadal, Francesc Pérez*, Jaume 

Esteve*, Núria Barniol 

Departament d’Enginyeria Electrònica, Escola Tecnica Superior d’Enginyeria, 

Universitat Autónoma de Barcelona.Campus UAB.08193-Bellaterra (Barcelona) Spain 

E-mail: Maria.Villarroya@uab.es 

*Instituto de Microelectrónica de Barcelona.-Centro de Microelectrónica de Barcelona.. Consejo 

Superiro de Investigaciones Científicas.. Campus UAB.08193-Bellaterra (Barcelona) Spain 

ABSTRACT 

A cantilever based Micro Electro Mechanical System 

(MEMS) for mass detection is presented. The sensor for 

multiple detections is composed by several cantilevers in 

an array configuration integrated monolithically with 

CMOS. Cantilevers are excited electrostatically to its 

resonance frequency. The oscillation of the 

microcantilever is detected by a capacitive detection 

technique. Mass variation is detected by resonance 

frequency shifting. The mechanical transducers are 

fabricated after CMOS process on polysilicon, one of the 

CMOS layers. Optical lithography is used for the 

cantilevers definitions. Cantilevers of 50 µm length, 1.1 

µm wide and 600 nm thick have been defined. This 

sensor provides a mass sensitivity of 70 ag/Hz. 


The objective of this article is to present the fabrication 

and characterisation of a cantilever based mass sensor 

integrated on standard CMOS chip. To detect tinny mass 

(10 -17 -10 -19 g), sensors based on submicrometric-resonators 

are used[1,2],. 

Cantilever based sensor are optimal systems for chemical 

and biological sensing [3].The inclusion of several devices 

on the same sensor allows the possibility of differential 

measurements with higher resolution and the chance of 

several different sensing (with appropriate surface 

functionalization on the same device). 

The sensing transducer and the control system will be on 

the same silicon substrate, being one polysilicon layer of 

the CMOS technology used as the structural layer for the 

cantilevers fabrication. The oscillation of the cantilever 

will be measured by a capacitive detection technique 

171 

2. SENSOR CHARACTERISTICS 

2.1 Sensor working principle 

According to the dimensions of the cantilever (figure1) 

and the mechanical properties of polysilicon (assuming 

E=160 Gpa, ρ=2.33·103 Kg/m3), the spring constant (k) 

and the resonance frequency (fres) can be calculated by: 

Particularry for polisilycon: 

3 

10 w 

k = 4. 

0· 

10 t (N/m) 

3 

l 

(1) 

1 

f res = 

2π 

E w 

2 

ρ l 

w 

l 

(Hz) (2) 

3 

f res = 1. 

3· 

10 (Hz) (3) 

2 

The cantilever-driver transducer constitutes a mass sensor 

by measuring the small changes in resonance frequency 

produced by small changes in the cantilever mass [4]. The 

mass resolution (assuming that the extra mass is 

distributed along the cantilever) can be expressed as: 

δm 

= 

δf 

50. 

6 

k 

f 

(g·Hz -1 ) (4) 

3 

res 

Thus, a theoretical mass resolution of 7.2·10 -17 g Hz -1 can 

be obtained with a cantilever 50 µm long and 1.4 µm 

wide..


l 

driver cantilever 

s t 

w 

Figure 1 Definition of the dimensions of the cantilever-driver 

structure 

2.2 Excitation and Readout Circuitry 

The CMOS circuitry is implemented in a standard twinwell 

CMOS technology. It is a 5V, 2.5µm, 2-poly, 2-metal 

CMOS process suitable for mixed and analog/digital 

applications. 

The integrated circuitry consists on the readout circuitry 

and the multiplexing system (front-end circuitry). The use 

of on-chip circuitry allows the minimization of leakage 

currents through parasitic capacitances (i.e. bonding pads 

and external wires) that may dominate the dynamical 

capacitance of interest (cantilever-driver in this case) 

when the device is scaled in dimensions. 

Figure 2 Draw of the sensor schema, two circuits allow 

differential measurements, cantilevers are excited from the driver, 

and polarized directly to the same voltage than the substrate. 

The cantilevers are electrostatically excited by applying 

both AC and DC voltage; the readout is achieved from 

one driver. Figure 2 shows a schema of the used 

configuration. Different polarization voltage (DC) can be 

applied to each cantilever, excitation voltage (AC) is 

applied to the uneven position drivers, readout is 

performed through the even position drivers. To avoid the 

collapse of the cantilever with the substrate, the substrate 

172 

is polarized to the same voltage than the cantilevers 

through a polarization ring. 

The motional current, generated by the cantilever-driver 

interface [5] of each cantilever is detected by the readout 

circuit. In this work we have designed a transimpedance 

amplifier (I/V converter) based on an operational 

amplifier with a resistive feedback. With this circuit we 

obtain a gain higher than 1MΩ in the bandwidth required 

for our system [1]. 

2.3 Fabrication Process 

Main objective in the process is to maintain unchanged the 

electrical characteristics of the CMOS circuits. CMOS is 

performed standard and transducers are defined on a 

process after CMOS. Special areas connected to the circuit 

have been defined during CMOS. Figure 3 shows a cross 

section draw of the resonators fabrication area after 

CMOS. An aperture has been defined on the passivation 

layer to access to the polysilicon. Poly0 layer (one of the 

polysilicon layer on the technology) is used as structural 

layer. During CMOS process Poly 1 layer (second 

polysilicon layer of the technology) is used as protection 

layer of the fabrication area during CMOS. 

Figure 3 Schematic cross section of the region for the resonators 

fabrication after CMOS process: Poly1 (protection layer) has to 

be removed by RIE before fabrication process 

First step after CMOS process is to remove the protection 

layer by reactive ion etching (RIE) process. Next 

cantilevers/drivers structures are defined. Several 

technologies for cantilever fabrication have been used. By 

optical lithography mechanical transducers are defined on 

the whole wafer. Nanolithography techniques as electron 

beam lithography allow higher resolution with lower 

throughput [6]. Figure 4 shows an draw of the 

fabrication process using optical lithography. First 

image shows the fabrication area after CMOS, B) 

the polysilicon protection layer is removed by RIE. 

Photolithography is performance to define the 

transducers C, D, E). Cantilevers and drivers pattern 

are transferred to the substrate by RIE. F). With a 

new resist mask H) cantilevers are released by wet 

etching of the silicon oxide used as sacrificial layer, 

I).

A) Fabrication area after CMOS 

B) Poly1 (protection layer) RIE 

C) Resist deposition for UV lithography 

D) UV exposition for structures definiton 

E) Resist mask defined after developement 


F) Pattern transfer to PolyO by RIE 

G) Resist remove 

Silicon substrate 

Passivation layer 

Poly 1 

Figure 4. Schema of the fabrication process. 

H) Photolithography for cantilever release 

I) Structures after SIO isotropic etching. 

2 

Photoresist 

Poly 0 Metal 

Thick oxide 

Interlayer oxide 

Figure 5 shows an optical image of the results. A 

four cantilever array connected to two readout 

circuits. Cantilevers have been defined by optical 

lithography. 

Figure 5 Optical image of the sensor: cantilevers defined 

optically on the CMOS substrate with the excitation and readout 

circuitry. ´ 

Figure 6 shows in detail an image of the transducer, 

arrays of 4 cantilevers and 5 drivers have been 

defined. Cantilevers 1.1 µm wide, 50 µm length and 

600nm thick have been defined. 

2.4 Results 

MEMS systems integrating polysilicon cantilevers with 

CMOS have been fabricated (Figure 5, 6) successfully. 

173 

The cantilevers dimensions are 50 µm long, 1.1 µm width 

and 600 nm thick., giving a mass sensitivity of 70 ag/Hz. 

Figure 6 Optical image in detail of the transducer.Cantilevers 50 

µm long, 1.2 µm width and 600 nm thick have been defined. 

Simultaneous electrical characterization of the frequency 

response of two cantilevers (shown on figure 5,6) has been 

made. Results are presented on figure 7. Resonance 

frequency detected is 502 kHz for cantilever #1 and 510 

kHz for cantilever #2. The frequency difference between 

both cantilevers is due to small variations on the 

dimensions due to the technological process used. 

Figure 7 Frequency response of two cantilevers, 50um long, 1.2 

um width and 600 nm thick, in the same array. 

From a detailed analysis of the resonance frequency of 

one of the cantilever with the applied voltage, the intrinsic 

resonance frequency of the system can be determined. 

Figure 8 shows the dependence of the resonance 

frequency with the applied effective voltage. From the 

linear regression the natural resonance frequency is 519.5 

kHz. As the resonance frequency depends on the Young’s 

module according with equation (2) we can determine the 

Young’s Module, giving 127 GPa, according with the 

values referenced on the literature [6]

Figure 8 Dependence on the resonance frequency with the 

applied effective voltage. 


3. CONCLUSION 

A mass sensing system with high resolution has been 

presented. The implemented array system allows multiple 

detection, increasing the sensor versatility. The readout 

performance integrated monolithically with the 

micromechanical transducers forms an on chip system. 

As resonance of two cantilevers of the array can be 

detected simultaneously, differentials measurements, that 

increase the resolution of the systems are allowed. 

High mass resolution can be achieved in ambient 

conditions using optical lithography for the cantilevers 

definitions. One order of magnitude can be increased 

reducing the dimensions by using e-beam lithography. 

A limitation in the resolution of the cantilevers width is 

due to the polysilicon grains, the use of crystalline silicon 

would improve the resolution. This possibility has been 

also developed during the PhD. 

4. REFERENCES 

[1] K. L. Ekinci,et al. “Ultimate limits to inertial mass 

sensing based upon nanoelectromechanical 

systems”. Applied Physics Letters, Vol. 84, N 22, pp 

4469-4471. (2004) 

[2] J. Verd et al. “Design, fabrication and 

characterization of a sub-microelectromechanical 

resonator with monolithically integrated CMOS 

readout circuit.” IEEE Journal of 

174 

Microelectromechanical Systems, Vol. 14, N 3. 

(2005) 

[3] N.V. Lavrik et al. “Cantilever transducers as a 

platform for chemical and biological sensors” 

Review of Scientific Instruments. Vol. 75, n.7, pp 

2229-2253.(2004) 

[4] G. Abadal et al. “Electromechanical model of a 

resonating nano-cantilever based sensor for high 

resolution and high sensitivity mass detection” 

Nanotechnology. Vol 12, pp 100-104. (2001). 

[5] J. Verd et al., “CMOS circuitry for on-chip read-out 

of a resonating nanometer-scale cantilever”, in 

DCIS´2002 Conference Proceedings, pp. 207-212 

(2002) 

[6] Baltes et al. “CMOS-MEMS” Wiley-VCH. 

(November 2004).

A NOVEL TECHNIQUE FOR COUPLING 

THREE DIMENSIONAL MESH ADAPTATION WITH 

AN A POSTERIORI ERROR ESTIMATOR 


R. Heinzl △ ,M.Spevak ◦ ,P.Schwaha △ ,T.Grasser △ 

△ Christian Doppler Laboratory for TCAD in Microelectronics 

at the Institute for Microelectronics 

◦ Institute for Microelectronics, Technical University Vienna, 

Gußhausstraße 27-29/E360, A-1040 Vienna, Austria 

E-mail: Heinzl@iue.tuwien.ac.at 

ABSTRACT 

We present a novel error estimation driven threedimensional 

unstructured mesh adaptation technique 

based on a posteriori error estimation techniques 

with upper and lower error bounds. In contrast 

to other work [1, 2] we present this approach 

in three dimensions using unstructured meshing 

techniques to potentiate an automatically adaptation 

of three-dimensional unstructured meshes 

without any user interaction. The motivation for 

this approach, the applicability and usability is presented 

with real-world examples. 


Most TCAD (Technology Computer Aided Design) 

problems can be formulated with partial differential 

equations and solved by numerical methods, usually 

finite difference, finite element and finite volume 

methods. They are used to model disparate 

phenomena such as dopant diffusion, mechanical 

deformation, heat transfer, fluid flow, electromagnetic 

wave propagation, and quantum effects. An 

essential step in these methods is to find a proper 

tessellation of a continuous domain with discrete 

elements, in our case tetrahedra. 

This transition from the continous domain to a 

discretized domain will inherently produce errors 

in the computed results, no matter how sophisticated 

or how appropriate a mathematical model 

is. This approximation error can be enormous, and 

can completely invalidate numerical predictions if 

we have no estimated or quantitative measurement 

of these errors. The general subject is referred to 

as a posteriori error estimation. It is an essential 

step to observe and bound the approximation error 

and to have a mesh adaptation strategy to guar- 

175 

antee the accuracy of the solution within a given 

range. In contrast to two dimensions where mesh 

generation and adaptation techniques are mostly 

based on hand crafted meshes or grids, it is almost 

impossible to design grids or meshes in three dimensions. 

On that account it is very important 

to generate and adapt meshes in three-dimensions 

automatically. 

2. MESH GENERATION AND 

ADAPTATION 

The first step in solving equations numerically is 

the discretization of the underlying computational 

domain. A widely used approach has been to divide 

the domain into a structured assembly of quadrilateral 

cells, with the topological information being 

apparent from the fact that each interior vertex 

is surrounded by exactly the same number of 

cells. This kind of discretization is called structured 

grid or simply grid. The major disadvantage 

of this approach is, that the discretization of 

highly non-planar elements produces a large number 

of points in the simulation domain. As a consequence 

the subsequent simulation and calculation 

steps are slowed down requiring a lot of computational 

resources. 

The alternative approach is to divide the computational 

domain into an unstructured assembly of 

cells. The notable feature of an unstructured mesh 

is that the number of cells surrounding a typical interior 

vertex of the mesh is not necessarily constant. 

This kind of discretization is called unstructured 

mesh or simply mesh. The major disadvantage of 

this approach is that the element generation process 

is one of the most complicated procedures in 

the field of simulation. However the reduction in 

simulation time and the requirements on computa-

tional resources can be significant. 

Based on the complex three-dimensional mesh generation 

process and the impracticality of using 

uniform refinement strategies most of the TCAD 

simulations are based on structured grids. But 

with the shift to real and complex input structures 

the grid approach with the involved refinement 

steps is no longer manageable. Here the unstructured 

mesh generation techniques come into 

play. In two dimensions most of the grid or mesh 

design procedure and adaptation steps are done 

by hand. With the step from two-dimensional to 

three-dimensional mesh generation and adaptation 

a hand crafted design and adaptation is impossible. 

First, the user interaction and visualization 

in three-dimensions is very difficult. Secondly the 

user can not be aware where the adaptation should 

be done. On this account three-dimensional mesh 

generation and adaptation must be coupled with 

error estimation techniques to ensure an automatic 

adjustment for a given problem without user interaction. 

A difficulty in the field of mesh adaptation is that 

to this date the understanding of the relationship 

between the quality of mesh elements, numerical 

accuracy, and stiffness matrix condition remains incomplete, 

even for the simplest cases. Experience 

and mathematical results have shown that isotropic 

elements usually lead to good results while degenerated 

elements will negatively affect the computation. 

Therefore we derive an abstract quality criterion 

for elements which have to be refined so that 

automatic remeshing can be easily accomplished by 

locally removing tetrahedra patches and inserting 

points derived from the error estimator. Our novel 

technique of calculating an abstract quality criterion 

to control the mesh adaptation or remeshing 

step separates the mathematical error estimation 

step from the geometrical meshing step and can 

therefore be implemented with different error estimation 

models. Also the software components can 

be easily upgraded. In the field of unstructured 

mesh modification the following techniques are possible: 

- H-method 

This method uses a geometrical parameter h 

for refinement (i.e. the height of a tetrahedron). 

- P-method 

This method varies the degree p in the approximation 

(i.e. quadratic ansatz functions within 

finite elements) while keeping the geometrical 

size h unchanged. 


176 

- HP-method 

This method combines the p-method with the 

h-method. 

- Adaptive remeshing method 

This method extracts a patch of marked elements 

which are accordingly remeshed. 

For our technique we focus mainly on the adaptive 

remeshing method (some kind of advancing front 

method [3]) because of the maximum degree of freedom 

within mesh adaptation. 

3. ERROR ESTIMATION 

The numerical expression of a discretized problem 

results in a discrete distribution of quantities and 

ansatz functions of a certain function class (e.g. 

piecewise affine functions) to describe the behavior 

of the quantities. Apart from the quality of 

the underlying mesh the quality of the simulation 

essentially depends on the selection of the ansatz 

functions. Using piecewise affine or constant ansatz 

functions like finite volumes or finite elements we 

always obtain results with a certain error. In terms 

of function spaces we carry out a projection of 

the complete space of functions to the subspace 

of piecewise affine or constant functions. Usually 

the euclidian norm is used in order to measure the 

distance between two functions. 

� 

� +∞� 

�2dx �f − g�2 = f(x) − g(x) (1) 

−∞ 

3.1 Residual based error estimation 

On each triangle the solution function is interpolated 

piecewise (Figure 1) affinely so as to receive a 

globally continuous function. This function fulfills 

the Laplace equation in the interior of the triangle 

whereas the discontinuity of the interpolated 

solution function at the boundaries leads to an error 

which can be estimated locally by the following 

formula [4]: 

� � 

ηk = hk 

E∈EK∩Eint 

� JE,n (uh) � 2 E + 

� 

E∈EK 

� JE,t (uh) � 2 � 

E 

(2) 

where EK denotes the edges of the triangle and Eint 

is the set of the interior edges. The local discon- 

tinuity of the gradient of the interpolated function 

at an edge is � JE, whereJE,n is the normal com- 

ponent and JE,t is the tangential component. The 

geometry factor hK denotes a characteristic length

Figure 1: (left) Two-dimensional representation of the 

error estimator. The normal component of the error 

changes at the facet. (right) Discrete solution function 

uh and the interpolation function uh as function over 

the mesh triangle 

of the triangle such as the mean edge length or 

the circumference radius. An interpretation of the 

behavior of the error estimator is given in the following. 

A gradient in the potential causes a flux, 

which is free of sources in the case of the Laplace 

equation. If the flux is discontinuous through a 

facet of a tetrahedron there has to include source 

density on the facet. The Laplace equation states, 

however, that the source density vanishes. Therefore 

the estimated error is zero if the potential behaves 

smoothly when crossing a facet. As we use 

piecewise affine interpolation the function is continous 

and therefore the jump of the tangential field 

strength has to vanish. For this reason only the 

normal components of the field strength are relevant. 

3.2 ZZ error estimation 

The ZZ error estimator [5] measures how much the 

numerical solution uh differs from a smoothed numerical 

solution uh (Figure 1). For some types of 

differential equations such as the Laplace equation 

the ZZ estimator has been shown to have upper and 

lower bounds [5]. For the interpolation function of 

the discrete numeric solution uh we use polynomial 

functions of degree one in each tetrahedron. The 

distance between the interpolated piecewise affine 

function and the piecewise constant function can 

be determined by the evaluation of the norm (1) 

and yields, 

ηk = � 


i 

U 2 i 

− � 

UiUj 

i�=j 

uh 

uh 

(3) 

where the Ui are the result values in the vertices of 

the tetrahedron. 

3.3 Evaluation of the error estimation 

A quality statement regarding the calculation can 

be given counting the simplices within a certain error 

interval of error values. The range of errors 

(from zero to the maximum error) is divided into 

equidistant error classes, i.e. ten classes. With 

177 

this separation different adaptation strategies can 

be used: minimum number of elements, error in 

element, ormaximum number of elements. Here 

we use the maximum number of elements strategy, 

which is bound to 30% in each refinement step, and 

the error in element strategy, only to sort the elements. 

4. RESULTS 

In the following the results of the error estimation 

and mesh adaptation techniques are shown. 

We use two different examples to demonstrate 

the behavior of our novel technique of coupling 

the error estimation and mesh adaptation steps 

through an abstract interface. First, we use a 

non-planar capacitor structure and calculate the 

potential distribution between the contacts. Here 

we use the residual error estimation technique only 

to show the shift of the quality of the elements 

within each error class. The second example deals 

with a realistic interconnect line with tapered line 

elements (lines with angular side walls) and a 

pyramid element for the via, which connects the 

two lines. Here we compare the residual error 

and the ZZ error estimation technique. For the 

non-planar capacitor we give a comparison of the 

initial error and the error value after one remeshing 

step: 

Initial meshing Remeshing 

Tetrahedra 2,145 8,774 

Minimum error 0.02 0.001 

Maximum error 25.0 19.4 

The next diagram shows the distribution of 

error values. The number of tetrahedra is 

plotted on the y-axis while the x-axis shows 

the error classes. The light gray boxes show 

the refined error values whereas the dark 

grey boxes show the initial error values: 

400 

300 

200 

100 

0 

4,636 

0 1 2 3 4 5 6 7 8 

As can be seen, the error values for the elements 

are shifted to the left side indicating that the local 

error values drop due to our refinement technique. 

Figure 2 depicts the error values without any refinement, 

whereas Figure 3 shows the distribution

Figure 2: Initial local error values without refinement 

Figure 3: Local error values after one refinement step 

of error values after one adaptation step (zero 

stands for a lower error, and one denotes a higher 

error). As we have seen in the error value diagrams 

the local error values are shifted to lower values. 

To show the applicability and usability for a 

realistic example we solve the Laplace equation 

within an interconnect structure and show the 

successfully application of our technique. In 

Figure 4 we depict the structure, the contacts and 

the potential distribution. Figure 5 presents a 

three-dimensional visualization (not a cut through 

the structure) of the relative error based on the 

residual error estimation technique within each 

adaptation step. Compared to the residual error 

estimator, Figure 6 presents the adaptation steps 

based on the ZZ error estimation technique. The 

Figure 4: Initial interconnect structure (top) and potential 

distribution (bottom) 

following table gives a comparison of the number 

of tetrahedra after each adaptation step within the 

two different error estimation techniques: 

Initial step Step 1 Step 2 

RS: Tetrahedra 1,720 2,052 2,334 

ZZ: Tetrahedra 1,720 2,075 2,290 


178 

Figure 5: Residual based error estimator, zoomed into 

the important via: first three adaptation steps 

Figure 6: ZZ error estimator, zoomed into the important 

via: first three adaptation steps 

5. CONCLUSION 

Using the advantages of mesh refinement in combination 

with a posteriori error estimation leads to an 

enormous increase of simulation result quality. The 

benefits of adaptive mesh refinement allow us to locally 

improve the mesh quality without increasing 

the number of mesh points dramatically. For this 

reason the resolution of the critical simulation domain 

is much higher and the relevant processes can 

be better simulated whereas the regions of lower 

interest do not require much simulation time. In 

combination with a posteriori error estimation a 

measure was found which triggers the refinement 

and indicates if the quality of the solution is resolved 

adequately. 

6. REFERENCES 

[1] J.T. Oden. A Posteriori Error Estimation, Verification 

and Validation in Computational Solid Mechanics. 

ASME, USACM Standards, 2002. 

[2] S. Prudhomme, J.T. Oden, T. Westermann, and 

M. E. Botkin J.Bass. Practical Methods for a 

Posteriori Error Estimationin Engineering Applications. 

International Journal for Numerical Methods 

in Engineering, 2003. 

[3] P. Fleischmann. Enhanced Advancing Front Delaunay 

Meshing in TCAD. International Conference 

on the Simulation of Semiconductor Processes and 

Devices (SISPAD), Kobe; 09-04-2002 - 09-06-2002, 

2002. 

[4] S. Nicaise. A Posteriori Error Estimations of Some 

Cell-Centered Finite Volume Methods. Université 

de Valenciennes et du Hainaut Cambrésis, MACS, 

ISTV, Valenciennes Cedex 9, France, 2004. 

[5] O.C. Zienkiewicz and J.Z. Zhu. A Simple Error Estimator 

and Adaptive Procedure for Practical Engineering 

Analysis. Int. J. Numer. Meth. Engrg. 24 

(1987) 337–357. MR 87m:73055, 1987.


EFFICIENT ERROR CORRECTION SOLUTIONS 

FOR OFDM-BASED WIRELESS VIDEO 

Mauro Lattuada, Renzo Posega, Marco Mattavelli, Daniel Mlynek 

Ecole Polytechnique Fédérale de Lausanne (EPFL), Laboratoire de Traitement des Signaux (LTS3), 

Batiment ELB, Station 11, CH-1015 Lausanne, Switzerland 

E-mail: mauro.lattuada@epfl.ch 

ABSTRACT 

This paper describes a new error correction scheme for 

flexible and robust high-throughput real time video 

transmission systems able to cope with difficult high 

mobility channels. The scheme is based on combining 

OFDM transmission with Turbo Coding and deep time 

interleaving. Simulations of different channel models and 

field test has shown that the provided solution provides 

relevant improvement versus DVB-T based solutions. 


The objective of this work is to study wireless digital 

video transmission system solutions achieving at the same 

time flexibility and robustness for high mobile 

applications. The OFDM modulation, for its intrinsic 

robustness to multipath fading has shown to be the best 

modulation choice for wireless digital video transmission. 

A simple evolution of nowadays well-established DVB-T 

[1] or ISDB-T [2] standard does not enable the 

development of an appropriate system for mobile 

applications. Several problems arise when trying to use 

transmission channels placed in higher frequency bands. 

The major problems are due to increased Doppler and 

phase noise impairments that can completely corrupt the 

performances of current receivers designed for less critical 

DVB-T mobility. New highly mobile applications require 

the development of appropriate OFDM processing 

architectures. Moreover, DVB-T standard modes are well 

suited for fixed bandwidth transmission to be compatible 

with existent analog broadcasting and cannot be easily 

modified to enable transmission into variable bandwidth 

channels. The available channel bandwidth in wireless 

digital video application can be very different. The most 

important goal of this work is the investigation of the 

possible improvements achievable by the Forward Error 

Correction (FEC) schemes combined with deep 

interleaving techniques applied to OFDM modulation in 

presence of deep fading impairments of the transmission 

channel. The objective is to achieve sufficient robustness 

for enabling a QoS for real time video contributions. 

While the digital television standards use a concatenated 

error correction scheme based on convolutional inner 

coder, in this work the investigated solution is based on a 

turbo inner coder. These codes offer theoretically better 

performances than convolutional codes, but the 

complexity and the computational requirements are 

179 

higher. A concatenated turbo-block codes scheme solution 

has been investigated with the purpose of taking 

advantages of the improved error correction capabilities 

for reduced complexity portable applications. The 

concatenated scheme solution obtains very low BER and 

avoids error floors at low bit error rates. 

The second element of the error correction scheme studied 

in this work is the channel interleaver used to average the 

channel fading in time and frequency. This mechanism is 

conceived to be adapted to the modulated bandwidth and 

is optimized for high throughput real time video. The 

proposed system architecture has been finally been 

implemented in FPGA. The application field of the 

proposed system is in the wireless transmission for digital 

television production like in the case of Digital News 

Gathering or the sport events production. Figure 1 shows a 

typical application of such system in the case of a bicycle 

race. 

Figure 1: Bicycle race example. 

2. DVB-T 

The DVB-T modulation scheme was developed to 

guarantee transmission error ratios between 10 -9 and 10 -12 . 

The DVB-T Forward Error Correction (FEC) system has 

been developed to work with fixed length MPEG2-TS 

(Transport Stream) packets. After a proper randomization 

to ensure the adequate binary transitions, the 188 bytes 

packets are Reed-Solomon (204,188) coded. This outer 

coder adds 16 bytes and has a maximum correction 

capability of 8 bytes. After this, the outer interleaving, 

also called Forney convolution interleaving, is performed 

to scatter the errors at the reception side and so to make 

the outer coding more effective by shuffling the data bytes 

over 12 packets. The inner coder is a 1/2 rate 

convolutional code (G 1=171 oct; G 2=133 oct) and performs

different puncturing patterns to obtain different coding 

robustness (R = 1/2; 2/3; 3/4; 5/6; 7/8). The inner 

interleaver consists in a bit-wise interleaving followed by 

a symbol interleaving. Both the bit-wise interleaver and 

the carrier interleaver processes are block-based and the 

block length depends on the OFDM mode (2K/8K carriers 

modes). The bit-wise interleaver, depending on the carrier 

modulation mode (QPSK, 16QAM, 64QAM) distributes 

the stream over different carriers to avoid selective fading 

corrupting consecutive message bits. The carrier 

interleaver then generates a permutation between carriers 

to spread in frequency the carriers over an OFDM symbol. 

Figure 2: Standard DVB-T transmitter block diagram. 


3. FEC and System design 

3.1 Turbo based concatenated FEC 

The Quasi Error Free performances (BER=10 -12 ) and the 

acceptable implementation complexity are contradictory 

requirements with a pure turbo code based error correction 

scheme. Turbo codes can provide such performances with 

a high number of iterations and block length and this 

impact directly with the memory and the processing 

power needed for real-time decoding. The solution 

developed and investigated in this work is to concatenate 

the turbo coder with a (204,188) Reed-Solomon outer 

code to correct the residual errors in the stream. The 

concatenated RS outer coder avoids error floors at low bit 

error rates and increase the working range of the system 

with a rapid transition to the QEF condition. This scheme 

is similar to the proposed FEC for the DVB-S2 [3] where 

LDPC codes are concatenated with a BCH outer coder. 

The chosen inner coder is a CRSC (Circular Recursive 

Systematic Convolutional) turbo code [4] with code rate 

of R=1/3, 2/5, 1/2, 2/3, 3/4. 

Table 1: Outer interleaver parameters. 

Branches (B) 12 

FIFO depth 

b = 0 ÷ (B -1) 

Delay 

(Number of packets) 

17 ⋅ b 

12 

Total memory (bytes) 2244 

The outer interleaver for the concatenated error correction 

scheme adopted is a convolutional interleaver based on TS 

packets. The statistics of the errors can vary with the 

channel characteristics so the convolutional interleaver 

180 

has to perform good averaging over many TS packets to 

allow the outer decoder to be effective. At the reception 

side the bit-stream from the turbo decoder is firstly 

converted in byte-stream and the correct alignment is 

retrieved looking for the synchronization byte of the TS 

header. Table 1 reports the outer interleaver parameters. 

3.2 Time and Frequency Interleaving 

The phenomenon of multipath fading, operating to the 

OFDM modulated signals, groups the errors in burst and 

decreases the efficiency of the error correction. When an 

OFDM signal undergoes a multipath fading process some 

frequency ranges are highly attenuated thus several 

adjacent carriers are corrupted by additive noise. At the 

same way, shadow fading corrupts several consecutive 

OFDM symbols. Two possible strategies can be applied in 

the case of deep fading for OFDM symbols. The first is 

the frequency interleaving inside each OFDM symbol and 

the second, called time interleaving, among the OFDM 

symbol sequence. 

The frequency interleaver takes the data at the output of 

the inner coder and has to interleave the bit stream to 

avoid consecutive bits to be mapped on the same carrier. 

This process can be divided in a bit-wise interleaver which 

interleaves consecutive bits into different mapped carriers 

and a carrier interleaver which generate a pseudo-random 

sequence for the carrier mapping. The two processes are 

block based and can be adapted to the number of 

modulated useful carriers of the OFDM symbol. 

The time interleaver receives the modulated carriers data 

(2, 4 or 6 bit each data carrier) from the bit interleaver. 

The task of the time interleaver is to spread errors coming 

from shadow fading across several OFDM symbols to 

allow the channel coding mechanism to rebuild the 

corrupted data. The benefits of such system are 

proportional to the memory depth because of the greater 

averaging period. The time interleaver needs to work on a 

continuous data stream and treats a huge quantity of data. 

The interleaving technique applied must manage large 

memory and needs to access data by bursts. The structure 

of the interleaver is shown in Figure 3. 

The main characteristic of this kind of interleaver is its 

inherent time-continuity. One faulty OFDM symbol is 

spread over B consecutive OFDM symbols and a group of 

length E of faulty OFDM symbols is spread over (B+E) 

symbols. The advantage of the convolutional interleaver is 

that it spreads time-consecutive errors evenly over the 

symbols. For our application the time interleaver works 

with blocks of 16 carriers called atoms. This simplifies the 

packaging of the data and improves the transfer bandwidth 

during the writing and reading process. Each OFDM 

symbol is divided into groups of carriers to vary the 

transmitted bandwidth. Each symbol is composed of 

maximum of Ng = 16 groups composed of 96 useful 

carriers. The time interleaver works on variable length 

symbols having a number of atoms Na equal to: 

Na = Ng ⋅ 96/16 = Ng ⋅ 6 (3.1)

The interleaving is done only among OFDM symbols so 

the number of branches needs to be B ≥ Na; B needs also 

to be a multiple of Na to keep the correct atom position. 

B = p ⋅ Na p = 1, 2 … (3.2) 


Figure 3: Time inteleaver. 

Depending on the interleaving depth (n ⋅ Na) and the 

number of atoms, the FIFO sizes M b has to be chosen as: 

Mb = n ⋅ b ⋅ Na b = 1, 2…, (B-1) (3.3) 

The delay will be equal to the number of symbol to store 

in the memory and equal to: 

D = n ⋅ p ⋅ Na = n ⋅ B (3.4) 

3.3 System design 

Figure 4: System block diagram. 

The new developed system is flexible, and is able to adapt 

the modulation parameters depending on the application, 

the field conditions and the available frequencies. The 

spectrum is organized in blocks of carriers to achieve a 

variable bandwidth. Each symbol is organized in N g=16 

groups of 96 useful carriers and 12 pilot carriers for 

channel estimation and 1 signalization carrier. The pilot 

carriers are scattered inside the OFDM symbol to obtain a 

better frequency and time channel estimation and each 

block contains two fixed pilots. The time and frequency 

interleavers act only on the useful carriers of the OFDM 

symbol. This implies that the synchronization mechanism 

can not benefit of the time-symbol interleaving so it needs 

to support long time fading before falling into an unlocked 

status. Table 2 summarizes the main system parameters. 

4. Performances 

A complete system simulator has been developed to test 

the system performances. This C++ test environment has 

been used to validate the modulation and demodulation 

algorithms and to provide the VHDL test vector for the 

FPGA implementation. 

181 

4.1 Simulations results 

Table 3 shows the performances of the concatenated FEC 

compared to DVB-T. The table shows the required E b/No 

for BER =2 ⋅10 -4 after inner coder and QEF after RS for 

the DVB-T standard. 

Table 2: System parameters. 

Useful channel 

bandwidth (Bw) 

0.5-25 MHz 

System frequency (fs) 12.5 MHz (Bw = 0.5-10.6 MHz) 

25 MHz (Bw = 1-22,2 MHz) 

Adjustable Steps (∆Bw) 0.66 MHz @ 12.5MHz 

1.31 MHz @ 25MHz 

FFT size 2K 

Maximum number of 

modulated carriers (N) 


useful carriers (Nu) 

Inter-carrier spacing 

(df) 


pilot carriers 

Useful OFDM symbol 

duration (Tu) 

Guard interval 

duration 

1745 

1536 

6,1 kHz @ 12.5MHz 

12.2 kHz @ 25MHz 

193 

163.84 µs @ 12.5MHz 

81 µs @ 25MHz 

1/4, 1/8, 1/16 

Constellation QPSK, 16QAM, 64QAM 

Inner encoder Turbo CRSC 

Inner encoding rate (R) 1/3, 2/5, 1/2, 2/3, 3/4 

Inner interleaving Time and frequency 

Maximum time 

interleaver depth (Ti) 

5.4 sec QPSK 

2,7 sec 16QAM 

1.3 sec 64QAM 

Outer interleaving Convolutional on 12 packets 

Outer encoding RS (204,188) 

Useful bitrate 4,63 ÷ 37.9 Mbits @ 12.5 MHz 

9.26 ÷ 75,8 Mbits @ 25 MHz 

Table 3: Performances comparison for BER = 10 -4 at the 

output of the inner coder. 

Code DVB-T (CC) Turbo 

Rate Eb/No (dB) Eb/No (dB) 

Gaussian 1/3 0.9 

2/5 1.2 

1/2 3.35 1.35 

Ricean 1/3 1.3 

2/5 1.6 

1/2 3.95 2.1 

Rayleigh 1/3 2.1 

2/5 2.8 

1/2 5.75 3.95 

The gain obtained by using turbo codes results of about 

2dB for the Gaussian channel, 1.85 dB for the Ricean 

channel and 1.8 dB for the Rayleigh channel. Figure 5

shows the BER evolution at the output of the turbo 

decoder for a small signal loss. The figure reports the 

evolution of the BER at the output of the inner coder for a 

signal loss of 100 symbols (19.4 ms) in the case of inner 

code R=1/3, QPSK modulation, for 1.1 dB Eb/No with 

Gaussian channel and time interleaving depth of 1920 

symbols (384 ms). 

BER 

10 -4 

10 -5 

10 

0 240 480 720 960 1200 1440 1680 1920 2160 2400 2640 2880 3120 3360 

-6 

SYMBOLS 

Figure 5: BER evolution at the output of the turbo 

decoder for a single failure point of 100 symbols and a 

time interleaver depth of 1920 symbols. 

The graph clearly shows that the after turbo decoder the 

QEF threshold of BER = 2⋅10 -4 is not exceeded thus the 

deep fading event has been overcome without residual 

errors. 

4.2 FPGA implementation 

The modulator and the demodulator have been 

implemented on a Xilinx FPGAs platform. The modulator 

design results in a total equivalent gate count of 2.4M 

gates and works at 100 MHz. The demodulator is 

implemented on two FPGA's resulting in a total equivalent 

gate count of 10 M gates working at 50 Mhz. The first 

FPGA receives the ADC data, control the AGC's and 

implements the channel estimation and compensation, the 

FFT and the demapping of the data carriers. The bit 

metrics are then output to the FEC section implemented 

on the second FPGA. This FPGA implements the time 

interleaver and controls a 256 Mbit SDRAM working at 

100MHz. 

4.3 On field and implementation results 

The system performances have been compared with 

8MHz bandwidth standard DVB-T demodulator. The 

transmitter works on 2.3 GHz band with 10 dBm emitted 

power. For QPSK modulation with GI=1/16 and R=1/2 

the obtained performances are shown in Table 4. These 

results show the minimum power required at the input of 

the demodulator to obtain an error free image at the 

receiver. The implemented system has also been tested 

with a ground-plane transmission during some tests 

sessions. 


182 

Video IN 

Transmitter 

Fixed 

Attenuation 

Variable 

Attenuator 

Multimode Receiver 

Consumer 

DVB-T 

demodulator 

Video OUT 

50 dB 0 90 dB 

Enhanched 

OFDM 

Demodulator 

Figure 6: Implemented system test bench. 

Table 4: Implemented system performances 

DVB-T -97 dBm 

Enhanced ODFM 

16 Iterations 

25 ms Time interleaver 

-99 dBm 

During these tests the transmission system has been 

compared in real working condition with a limited power 

(1 W) in a very difficult environment (forest road). These 

tests show that a time interleaver between 100 and 800 ms 

improves the robustness of the link and allows the receiver 

to obtain a high quality image compared to the standard 

DVB-T transmission. 

5. CONCLUSION 

This work shows that a robust error correction system for 

high quality video mobile terminals based on turbo coding 

and time interleaving can improve the mobile 

performances of OFDM systems. The robustness of the 

system resides in a wide error spreading associated to a 

strong error correction system capable to cancel the 

impairments of the channel. The turbo based concatenated 

error correction demonstrate to be a good solution for 

QEF performances in mobile channels. The simulations 

show that the time interleaver is a very effective tool to 

successfully overcome shadow fading events. The 

experimental performances of the systems during field test 

confirm that the proposed error correction techniques can 

be really used to improve the performances of DVB-T in 

highly mobile applications. 

6. REFERENCES 

[1] Digital Video Broadcasting: Framing Structure, 

channel coding and modulation for digital terrestrial 

television (DVB-T). ETSI EN 300 744 v1.4.1(2001- 

01) 

[2] Terrestrial Integrated Services Digital Broadcasting 

(ISDB-T) Specifications for channel coding, Framing 

structure and modulation, ARIB, September1998. 

[3] Digital Video Broadcasting (DVB-S2); Second 

generation framing structure, channel coding and 

modulation systems for Broadcasting, Interactive 

Services, News Gathering and other broadband 

satellite applications. Draft ETSI EN 302 307 V1.1.1 

(2004-06) 

[4] D. Gnaedig, E. Boutillon, V. C. Gaudet, M. Jézéquel, 

P. G. Gulak, "On Multiple Slice Turbo Codes", in 

Proc. International Symposium on Turbo Codes and 

Related Topics, Brest, pp. 343-346, Sept. 2003


ALGORITHMIC/ARCHITECTURAL DESIGN FOR 

H.264/MPEG-4 AVC LOW-POWER VIDEO CODEC 

Massimiliano Melani, Luca Fanucci, Sergio Saponara 

Department of Information Engineering, University of Pisa, Via Caruso, 56122, Pisa, Italy 

E-mail: massimiliano.melani@iet.unipi.it 

ABSTRACT 

With reference to the new H.264/AVC video codec 

standard, this paper presents novel algorithmic and 

architectural solutions for the implementation of contextaware 

coprocessors in real-time, low-power embedded 

systems. The focus is on the motion estimation task which 

is the traditional bottleneck of video coding systems in 

terms of computational and memory costs. When 

implementing the proposed VLSI architecture in CMOS 

technology the same performance of the conventional 

Full-Search approach is achieved for a wide range of bitrates, 

while remarkably reducing computational burden 

and power consumption. 


ITU-T and ISO-IEC have recently released a new video 

coding standard, the H.264/MPEG-4 AVC. It achieves the 

same visual quality of previous standards with bit-rate 

reductions up to 50% [1], thus representing the enabling 

technology for high quality video communication over 

wireline (e.g. xDSL) and wireless (e.g. UMTS, WLAN) 

networks. Like previous schemes, H.264/AVC is based on 

a hybrid motion compensated and transform coding 

model, adopting multi-reference frames and variable block 

sizes. Additional features, particularly in the motion 

estimation (ME) task, improve the coding efficiency at the 

expenses of an increased implementation cost: over than 

60% of the whole encoder complexity, representing the 

bottleneck of the entire codec. Thus, the design of lowpower 

ME engines, supporting multi reference frames and 

variable block sizes, is a key issue for H.264/AVCcompliant 

battery-powered video terminals. To this aim 

we propose to add a low complexity context aware 

controller to a conventional Full Search (FS) ME engine. 

By proper configuring search parameters, the proposed 

controller avoids unnecessary computations and memory 

costs. This way implementation complexity is reduced by 

a factor up to 25 depending on the input signal, while 

keeping unaltered performance in terms of ME accuracy. 

Hereafter Section 2 reviews state-of-art algorithms and 

VLSI architectures for ME. Section 3 describes the 

proposed algorithmic solution and its relevant architectural 

implementation. Section 4 shows the achieved results in 

terms of coding efficiency and implementation complexity 

when applying the context-aware controller to both FS and 

Fast ME searching engines. Conclusions are drawn in 

Section 5. 

183 

2. ME ALGORITHMS AND VLSI 

ARCHITECTURES 

A straightforward technique for performing the ME is the 

FS: as sketched in Fig. 1, the current frame of a video 

sequence is divided into non-overlapping blocks (current 

blocks) and, for each of them, a block (reference block) in 

one or more previous processed frames is searched for the 

best matching within a search window with maximum 

horizontal and vertical displacements of p pixels. The 

matching algorithm consists in computing a cost function, 

usually the SAD (Sum of Absolute Differences), for all the 

(2·p+1) 2 possible positions of the reference blocks within 

the search window. If a(i,j) and b(i,j) are the pixels of the 

current and reference blocks and m, n are the coordinates 

of Motion Vector (MV) (i.e. position of reference block in 

the search area), the SAD for a VxH-pixel block type is: 

V 1 H 1 − − 

SAD( 

m, 

n) 

= ∑∑ a( 

i, 

j) 

− b( 

i + m, 

j + n) 

, (-p ≤ m, n ≤ p) 

i= 

0 j= 

0 

Figure 1. Full Search motion estimation 

In previous H.263/MPEG-4 video coding standards only 1 

reference frame and 16x16-pixel blocks were used for 

ME. In the emerging H.264/AVC standard the motion 

estimator considers the current frame and multiple 

reference frames and produces, as output, the minimum 

SADs (SADmin) and the relevant MVs for each 16x16pixel 

block and its sub-partitions, down to 4x4 pixel 

blocks. The extension of ME to variable block sizes and 

multiple reference frames, together with new coding 

features (CABAC entropy coding, intra spatial prediction, 

integer transform, in-loop deblocking filter) is at the basis 

of a doubled coding efficiency of H.264/AVC vs. its 

ancestors, but is also responsible of an increased 

complexity up to a factor 10 for the encoder [1,6]. As

concerns real-time implementation of video coding 

standards, ME is traditionally the bottleneck of 

H.26x/MPEGx coders and requires a dedicated hardware 

engine. As an example implementing a FS ME for a 30 Hz 

CIF video (352x288 pixels), with M=5 reference frames 

and a search range of ±p=16 pixels, requires the 

examination of M⋅(2p+1) 2 =5445 locations for each image 

block, i.e. more than 16x10 9 /sec absolute differences and 

data accesses at pixel level (8-bit data). The high 

computational and memory requirement and the 

consequent high power consumption of the FS approach 

depend quadratically on the search size, and linearly on 

the number of reference frames, but are independent from 

the scene content. Processing slow-motion or low-quality 

scenes requires the same high implementation cost of 

high-quality and/or high-dynamic videos. Other ME 

techniques have been proposed in the literature, in order to 

decrease complexity of the search: Three-Step-Search 

(TSS), Four-Step-Search, 2D Log-Search [7,8,9]. Their 

leading idea is to reduce the number of reference blocks 

processed for each current block, but without exploiting 

the statistics of the input data; usually a local minimum is 

obtained, instead of determining the global one over the 

search range. Hence the computational cost reduction vs. 

FS is achieved at the expenses of a reduced estimation 

quality. The class of predictive algorithms [7,10] exploits 

the spatial and temporal correlation of typical MV fields. 

For applications from tens to hundreds of Kbps the same 

high coding efficiency of the FS can be achieved with 

computational load reductions but they are affected by two 

problems: (i) the higher is the bit-rate of the considered 

application the worse is the algorithm performance; (ii) the 

regularity of the FS data flow is broken thus causing a 

poor data reuse. Several VLSI architectures have been 

proposed in the literature to implement FS ME consisting 

of 3 main units [7,9,11]: (i) an array of processing 

elements realizing at pixel level the basic SAD operation; 

(ii) a local memory to exploit data reuse thus reducing the 

accesses to large background frame memories; (iii) an I/O 

control unit. Such architectures are not efficient in terms 

of power consumption since the search engine is always 

working at maximum effort, i.e. using maximum search 

displacement and number of reference frames, also in case 

of slow-motion or low-quality videos. 

3. PROPOSED ME COPROCESSOR 

To address the above issues this paper proposes a ME 

technique that exploits input signal variations to 

automatically configure the search area size and the 

reference frames number of a FS block-matching engine. 

According to the scheme in Fig. 2 we propose to add a 

low-complexity control unit, the Context Aware 

Controller [2,3], to a FS engine made up of a Search 

Engine plus an I/O interface and a local memory. While 

the search engine is working, the adaptive controller 

extracts from the search engine partial results information 

on the input signal statistics using them to configure the 

search area size and the number of reference frames. 


184 

I/0 

Control 

Ext_ctrl_I/O 

Search 

Engine 

Current 

Pixels 

Reference 

Pixels 

SAD 

MV 

Search size & 

frame number 

Local Memory 

Data_I/O 

Context 

Aware 

Controller 

Figure 2. Architecture of the self-adaptive ME 

The leading ideas for the design of such controller are: (i) 

exploiting the spatial and temporal correlation that 

characterizes the MV field of real-world sequences; (ii) 

using the minimum SADs (SADmin) and the relevant 

MVs values as indicators of the motion prediction 

accuracy. In case of interframe coding, a high SADmin 

value for the processed block point out a high prediction 

error and that the used set of search parameters (search 

range, number of reference frames) should be extended. A 

low value of SADmin instead indicates that used search 

parameters allow for good motion estimation and hence 

search range and number of reference frames can be kept 

unaltered or reduced to save computational/memory costs. 

Therefore, by comparing the SADmin related to a certain 

block with proper thresholds the optimal search area range 

and number of reference frames for the successive blocks, 

for each 16x16-pixel block and its subpartitions, can be 

determined. The analysis domain is divided in 3 zones 

determined comparing the SADmin of a certain 16x16pixel 

block with 2 thresholds T 1 and T 2. The search 

window size for the successive 16x16-pixel block and its 

subpartitions is differently determined (by using the MVs 

of its spatio-temporal neighbouring blocks), according to 

the resulting zone. If T 1

multiple reference frames are not really useful. On the 

contrary in case of sequences with a high grade of 

dynamism only 30% of optimal MVs refer to the first 

frame, in this case multiple reference frames leads an 

effective profit. As consequence, we improved the 

proposed basic control, briefly discussed above, 

introducing a cost function to verify if, for all the blocks in 

the current frame under estimation, it is worth using 

multiple reference frames or not. The basic idea is to 

compare the maximum SADmin of the previous encoded 

frame with a proper threshold T 3; if the maximum 

SADmin results lower than T 3, only 1 reference frame will 

be considered for all the blocks in the current frame 

otherwise 5 reference frames. In the latter case, when 

estimating the motion of each block the 5 search windows 

in the 5 reference frames have the same size (for more 

details see [2]). It is worth noting that the values for 

thresholds T 1, T 2, T 3 have been empirically derived by 

computer simulations of typical videos with a wide range 

of different grades of dynamism and image formats 

searching a good trade-off between the performance of the 

resulting motion estimator and the computational overhead 

introduced by the decision law. The proposed technique 

has been implemented both as a software running on a 

general-purpose µProcessor (PentiumIV) and as dedicated 

VLSI macrocell. The VLSI architecture of the motion 

estimator depicted in Fig. 2 has been implemented using a 

semi-custom design flow based on reusable VHDL 

description and logic synthesis with Synopsys in 0.18 µm 

standard-cells CMOS technology. The final motion 

estimator cell is made up of a context-aware controller, 

implementing the decision laws briefly described above, 

which configures the search parameters of a conventional 

FS engine based on the architecture presented in [12]. The 

reduction of the adaptive search size and reference frames 

number obtained in the final motion estimator permits to 

lighten the computational load and to decrease memory 

accesses required to the dedicated search engine. This 

reduction has been exploited, by clock gating, to lower the 

power needed to elaborate a video sequence since, in 

CMOS VLSI circuits, the power consumption primary 

derives by switching activity which depends linearly on 

the computational load and memory accesses. 


4. PERFORMANCE AND 

COMPLEXITY RESULTS 

4.1 ME Performance 

With respect to conventional ME solutions, and to 

alternative solutions proposed in literature [4], the 

efficiency measured as reduced processing time in case of 

software implementation ranges from a factor 2.2 to 25, 

depending on the input signal and on the encoder 

configuration. The compression performance is the same 

of the H.264/MPEG-4 AVC scheme using FS. Fig. 3 

shows the time (sec) spent for the ME task for sequences 

with different formats and grades of dynamism: 

Mother&Daughter QCIF (M&D), Foreman QCIF (FOR), 

Mobile&Calendar SIF (M&C) and Stefan CIF (SF) all at 

185 

30Hz when encoding 300 frames for QP=24, 1 reference 

frame and a maximum search range ±p=16. The results are 

obtained keeping the coding efficiency (bit-rates achieved) 

roughly the same over a wide range of bit-rates for equal 

PSNR values. We observe that our algorithm features a 

speed increase ranging from a factor 2.9 up to 7 vs. the FS 

and from 1.1 up to 1.9 vs. [4]. Repeating the above 

analysis other sequences leads to similar results. 

ME time (sec) 

300 

250 

200 

150 

100 

50 

0 

H.264_FS-1fr 

H.264_OUR 

H.264_[4] 

1 2 3 4 

sequences 

Figure 3. ME time using different motion 

estimators for 1)M&D 2)FOR 3)M&C 4)SF 

Fig. 4 compares the PSNR vs. bit-rate performances of the 

JM6.1C standard model [1] using for ME our technique 

(H.264_OUR in Figs. 3,4), a FS with 5 reference frames 

(H.264_FS-5fr) and a FS with 1 reference frame 

(H.264_FS-1fr). In Fig. 4 our ME and the FS-5fr behave 

similarly featuring, for all bit-rates, a PSNR 2 dB higher 

than the FS-1fr. The input test video is Mobile & Calendar 

CIF. Similar results are achieved with other test videos. 

PSNR (dB) 

43 

40 

37 

34 

31 

28 

25 

H.264_FS-1fr 

H.264_FS-5fr 

H.264_OUR 

0 2000 4000 6000 

bit-rate (Kbps) 

Figure 4. Coding performance using different 

motion estimators (Mobile & Calendar CIF) 

4.2 CMOS synthesis results 

The complexity of the synthesized macrocell amounts to 

roughly 109 Kgates plus 37 Kbits of SRAM and it allows 

real-time of main video formats. With reference to Fig. 2 

the overhead of the context-aware controller is limited in 

terms of circuit complexity (3.5 Kgates and 13 Kbits of 

SRAM) and is negligible in terms of timing since the 

controller and the search engine works concurrently. The 

power consumption of the whole motion estimator has 

been extracted from gate level simulations using as input 

stimuli the sequences already adopted during the 

algorithmic development. In case of 30 Hz CIF videos 

with a max search range ±p=16 pixels and 5 reference

frames real-time processing is achieved with a clock 

frequency of about 68 MHz The power consumption 

without the context-aware controller amounts to roughly 

0.2 W. This value is practically independent from the 

input signal since a fixed search displacement ±p=16 and 

5 reference frames are used for both high-dynamic video 

scenes and slow-motion ones. With the use of the contextaware 

control we can achieve a remarkable power saving 

for the whole motion estimator through clock gating. 

Indeed, depending on the considered input signal, the 

average search size ranges from 3.5 to 8.5 instead of being 

fixed to 16 while the average number of reference frames 

ranges from 1.2 to 4.6 instead of 5. As consequence the 

adaptive processing approach leads to a power 

consumption reduction from 60 % to 95 % depending on 

the input signal. The lower the video sequence dynamism, 

the higher the power consumption reduction. 

4.3 Extension to Fast ME techniques 

The proposed technique has been also applied to fast ME 

engines [5] in JM9.0C standard model; in this case we can 

achieve roughly the same coding efficiency (measured as 

bit-rate spent for a fixed PSNR) and a complexity 

reduction vs. [5] by a factor at least 2. Since [5] already 

obtains a speed factor up to 20 vs. the FS the whole speed 

up increase combining our context-aware control with Fast 

ME is higher than 40 vs. FS. 

Coding 

time saving 

Bit rate 

increase 


Table 1. Comparison between our and [5] 

M&C FOR M&D 

69,5% 72,3% 69,2% 

8% 5,40% 4,60% 

5. CONCLUSION 

The paper presents a power-optimized motion estimator, 

compliant with the new H.264/MPEG-4 AVC video 

standard. For bit-rate applications ranging from few Kbps 

to several Mbps, our ME achieves the same compression 

efficiency as the FS (working with multiple reference 

frames, variable block sizes and fixed search size) but with 

a noticeable complexity reduction since unnecessary 

computations and memory accesses can be avoided. The 

increased efficiency is exploited both for (i) processing 

time reduction (up to a factor 25) in case of software 

implementation; (ii) power consumption reduction (from 

60% to 95%) in case of CMOS hardware implementation. 

The context-aware control technique has been also applied 

to recently proposed fast ME techniques allowing for a 

complexity reduction higher than a factor of two with 

roughly the same coding efficiency. The whole speed up 

increase combining our context-aware control with Fast 

ME is higher than 40 vs. FS. 

186 

6. ACKNOWLEDGMENT 

The work has been supported by the PRIN2003 and FIRB 

PRIMO projects by MIUR. Discussions with M. Casula, 

University of Pisa, are gratefully acknowledged. 

7. REFERENCES 

[1] T. Wiegand, G. Sullivan, G. Bjntegaard, A. Luthra, 

Overview of the H.264/AVC video coding standard, 

IEEE, TCSVT, 13 (7): 560-576, 2003. 

[2] S .Saponara, M. Melani, L. Fanucci, P. Terreni, 

Adaptive algorithm for fast motion estimation in 

H.264/MPEG-4 AVC, EUSIPCO04, Vienna, 269-272 

[3] S. Saponara, M. Melani, L. Fanucci, P. Terreni, 

Controlling Motion Estimation Search Parameters 

for a Power-optimized Video Architecture in 

H.264/AVC, IWSES 2004, Poznan, 275-278. 

[4] W. Song, M Hong, Adaptive search range decision 

algorithm for fast motion estimation, Proc. of SPIE, 

VCIP04. vol. 5308, pp. 1073-1081, 2004. 

[5] Z. Chen, J. Xu, Y. He, Efficient Fast ME Predictions 

and Early-termination Strategy Based on H.264 

Statistical Characters, ICICS-PCM03, Singapore. 

[6] J. Ostermann, J. Bormans, P. List, D. Marpe, M. 

Narroschke, F. Pereira, T. Stockhammer, T. Wedi, 

Video coding with H.264/AVC: tools, performance 

and complexity, IEEE Cir. and Syst. Magazine, 4 (1): 

7-28, 2004 

[7] P. Kuhn, Algorithms, complexity analysis and VLSI 

architectures for MPEG-4 motion estimation, Kluwer 

Academic Publisher, 1999 

[8] M. Takahashi et al., A 60-MHz 240-mW MPEG-4 

videophone LSI with 16-Mb embedded DRAM, IEEE 

J. Solid State Circuits 35 (11): 1713–1721, 2000 

[9] M. Harrand et al., A single-chip CIF 30 Hz H.261, 

H.263, H.263+ video encoder/decoder with 

embedded display controller, IEEE JSSC 34 (11): 

1627–1633, 1999 

[10] A. Chimienti, L. Fanucci, R. Locatelli, S. Saponara. 

VLSI architecture for a low-power video codec 

system, Microelectronics Journal, 33 (5): 417-427, 

2002 

[11] L. Fanucci, S. Saponara, L. Bertini, A parametric 

VLSI architecture for video motion estimation, 

Integration The VLSI Journal, 31 (1): 79-100, 2001 

[12] Y.-W. Huang, T.-C. Wang, B. Hsieh, L.-G. Chen, 

Hardware architecture design for variable block size 

motion estimation in MPEG-4 AVC/JVT/ITU-T 

H.264, Proc. IEEE ISCAS03 , pp. 796-799, Bangkok, 

2003


ALGORITHM FOR THE AUTOMATIC 

VERIFICATION OF COMPLEX MIXED-SIGNAL 

ICS REGARDING ESD-STRESS 

H. Morgenstern (1) , G. Groos (2) , H. Köhne (1) , M. Stecher (3) , W.John (1) , H. Reichl (1) 

(1) Fraunhofer IZM, Gustav-Meyer Allee 25, 13355 Berlin, Germany 

(2) Universität der Bundeswehr, Werner-Heisenberg Weg 39, 85577 Neubiberg, Germany 

(3) Infineon Technologies, AI AP TD BCD, Balanstr. 73, 81541 Munich, Germany 

ABSTRACT 

In this publication, an algorithm is described which automates 

the verification of a complex integrated circuit (IC) 

with regard to the behaviour under transient high current 

impulses (e.g. ESD). In order to reduce the complexity of 

the circuit for a later transient simulation with high current 

simulation models, the electric state of the circuit under 

stress is analysed in a simplified way enabling the efficient 

automated analysis of the total IC. A manual extraction 

of the relevant circuit parts for such a transient analysis 

can thus be avoided. The algorithm is embedded in a 

commercial design framework for IC-design and uses the 

data structures already existing. 


Due to the complexity of today’s integrated circuits, the 

development costs and permanently shortened product 

cycles, a verification of the functionality by circuit simulation 

is essential. Both for digital and mixed-signal ICs, 

simulations of the circuit operation are carried out as early 

as possible in the design cycle, e.g. using hardware description 

languages like VHDL, VHDL-AMS or SystemC 

[1]. But in order to reproduce the behaviour of analogous 

circuit parts or the impact of parasitic resistances, capacitances 

or inductances, it is necessary to integrate analogous 

simulations (e.g. SPICE-based) into the design flow. 

Due to clarity and work sharing, designs are nowadays 

split up into blocks and processed within a hierarchical 

design process. The functionality of each block is at first 

checked individually, and then the simulation of the whole 

IC consists of a combination of analogous, digital and 

behaviour models. Yet, the transient, analogous simulation 

of the whole IC is often no longer possible with a justifiable 

time expenditure due to the complexity of today’s 

circuits [2]. The usual manual verification or simplification 

of the circuit diagram is extremely time consuming 

and error-prone. Moreover, it presupposes a high expertise 

not only with regard to the circuit in all details but also to 

possible parasitic effects of the used technology. In the 

ESD-case, the verification of the whole circuit is especially 

important as – due to complex supply nets, circuit 

blocks of different voltage classes and application specific 

I/O- or ESD-structures – couplings and transient current 

paths can come up, which are not covered via single block 

simulations [3]. A further issue when simulating a circuit 

187 

subject to ESD-impulses is that special simulation models 

are necessary which allow the modelling of the physical 

behaviour when such an incident occurs. These models are 

considerably more complex than standard models and 

thus, they increase the simulation time and the probability 

of convergence problems. 

However, in order to be able to predict the behaviour of 

the whole IC in the case of an ESD impulse already in an 

early design phase, different approaches exist. In [3], an 

algorithm is presented for the special case of CDM- 

(Charged Device Model) stress which partitions the whole 

circuit and models each block as RC-network. Between 

these blocks, the current paths are extracted during a 

CDM-impulse via simulation. In contrast to this, the current 

paths in [5] are characterized via an analysis of the 

resistance of all possible paths and after that, the possibility 

of each path is calculated. In [4], the ESD critical devices 

inside the pad frame are simulated with different 

characteristics for snapback and breakdown, taking all 

possible permutations into account. In [2], a two-step approach 

of a Full-Chip analysis is demonstrated, where the 

whole netlist is reduced in a first step and a simulation of 

the reduced netlist is carried out subsequently. A reduction 

algorithm analyses critical voltages in each possible 

path and subsequently decides whether this path shall be 

included in the reduced circuit plan or not. Due to the 

variety of possible paths, the applicability of this procedure 

is highly constrained for cases in which a supply net 

is involved. 

In this publication, a procedure is presented which also 

carries out a reduction of the whole circuit, in order to 

subsequently allow a more precise analysis. But in comparison 

to [2], the reduction algorithm presented here is 

more efficient in finding the relevant paths and it considers 

not only fixed voltage conditions, but additionally the 

static and transient circuit states in a certain approximation; 

in this way it extracts less superfluous paths and is 

able to distinguish between potentially damaged and otherwise 

involved devices. 

2. Approach to Circuit Reduction 

In order to carry out a transient simulation of the IC during 

ESD-stress, it is necessary to reduce the netlist to 

those parts which decisively determine the behaviour of 

the circuit in the relevant case. A differentiation is made

etween “endangered” and “involved” circuit elements. 

During the stress, endangered devices may experience a 

physical damaging and have to be part of the reduced 

circuit diagram in any case. On the basis of these devices, 

the critical current paths, i.e. the ones conducting the largest 

current through the endangered devices, are extracted. 

In addition to these paths, further devices can carry a significant 

current and thus, they are decisively responsible 

for the behaviour of the whole circuit. These elements are 

also included into the reduced circuit diagram. 

To provide this, it is indispensable to consider the circuit 

states of the transistors in an efficient way in order to reflect 

the distribution of the impulse and the influence of 

parasitic capacitances and resistances for the worst case. 

Figure 1. Approximation of ESD-impulse by a 

ramp function 

The rise times of an ESD current pulse range from 10ps 

during CDM-impulses to 10ns during HBM-impulses [8]. 

Those current pulses are transformed by the protection 

device at the pin under test to a voltage pulse with a certain 

rise time (t r) and maximum voltage (V max). These high 

voltages and voltage slopes lead to currents and voltages 

(ohmic and capacitive) inside the circuit which damage 

devices or have impact on the circuit state of transistors. 

Because the worst case can be expected when both the 

voltage and its slope is maximal, the transient waveform 

of the impulse is approximated as a ramp function with 

the same rise time and maximum voltage (Figure 1) and 

the end of the rising edge regarded as that worst case, 

where the current path extraction is carried out. 

Req = tr ___ 

C 

Error criteria 

Accuracy criteria 


Netlist Input impulse 

Simplified 

simulation 

(DC-simulation) 

Current path 

extraction 

Reduced 

netlist 

Transient 

simulation 

Ramp function 

Boundary nodes 

Figure 2. Verification flow for netlist reduction 

In order to arrange this process time efficiently, a modified 

direct current simulation (DC-simulation) of the 

whole circuit diagram is carried out (Figure 2). 

188 

To model the capacitive behaviour of devices in a DCsimulation, 

the internal capacitances are replaced by 

equivalent resistances as follows: In a DC-simulation, 

these resistances should carry the same current as the internal 

model capacitances in a transient analysis at the end 

of the voltage ramp (worst case). That current follows 

from Equation (1) using the approximation of the impulse 

by a ramp function. The resistance (R eq) which carries the 

same current at constant voltage V max as the capacity with 

the equivalent ramp can be calculated by equation (2). 

dv( 

t) 

i( 

t) 

= C ⋅ 

dt 

R 

eq 

V 

I 

= max 

i 

tr 

= 

C 

V 

C ⋅ 

t 

= 

max 

r 

(1) 

Thus, a DC simulation applying Vmax and using those 

equivalent resistances is an approximation of the worst 

case during the ESD impulse. 

The modification of the simulation models can take place 

in a semi-automatically process. Here, parallel to an already 

existing model library, a so called DC-library is 

produced in which the DC-models are archived. After 

these models were embedded into the netlist, the DCsimulation 

of the DC-netlist can be carried out and the 

result file can be analysed with the help of device specific 

current- and voltage criteria. This process (current path 

extraction) analyses the paths of the highest currents starting 

from the damaged devices. 

Subsequently, the devices which are decisive for the behaviour 

of the whole circuit are extracted via different 

accuracy criteria and are included in a reduced netlist. 

Then, this netlist serves as a starting basis for a transient 

simulation. 

The whole simulation process (Figure 2) can be controlled 

and automated by a script language such as described in 

[6]. This makes it possible to access the internal data 

structures of a design framework for IC-design [7]. 

3. Realization and Verification of the 

Modeling Approach 

In order to detect over voltages and thus to deduce possible 

damages of the circuit elements, the simulation models 

are extended by anti-serial Zener diodes (Figure 3). As 

soon as the voltage across one diode exceeds the breakdown 

voltage, a current flows in this branch and the device 

is marked as endangered within the algorithm for the 

current path extraction. 

The complex sub circuits of the transistor models were not 

changed. Esp. the internal capacitances, which have no 

effect during a DC simulation, were not removed, but the 

equivalent resistances were just added in parallel (see 

Figure 3). If needed, further simplification can take place 

here. 

(2)

Figure 3. Extended DMOS simulation model 

Due to the substitution of capacitances by their equivalent 

resistances, the behaviour of the circuit is modelled within 

a certain approximation. As an example, in a simple RC 

serial circuit the current flow can be described by the differential 

equation (3) (voltage ramp with V max and t r), 

resulting in the current transient from equation (4). 


di( 

t) 

i( 

t) 

V 

= − + 

dt R ⋅C 

R ⋅t 

V ⎛ max ⋅C 

i( t) 

= ⎜ 

1− 

e 

tr 

⎝ 

max 

t 

− 

RC 

If the capacitance is substituted by the equivalent resistance, 

a difference is yielded which depends on the ratio 

of R to C respective R eq. In Figure 4, the current flows of 

the RC- and RR eq- serial connection as well as the relative 

deviation are shown as a function of the ratio R eq /R. The 

qualitative characteristics are well reproduced by the approximation. 

The maximum error occurs when R and R eq 

differ by a factor of 1.5 and 2.5 and is acceptable for a 

worst case consideration, as will be shown below. 

Figure 4. Current flow through RC- and RReq series 

connection and relative deviation. 

In order to verify this approach and to validate the approximation, 

transient and DC simulations were carried 

out with the same schematics, increasing the complexity 

r 

⎞ 

⎟ 

⎠ 

(3) 

(4) 

189 

of the analyzed circuits step by step (see also chapter 4 

and 5). In a first investigation simple networks of capacitances 

and resistances where analyzed. The difference 

between transient and DC-simulation was in the range of 

0.1-0.4 percent. The behaviour of a few transistors with 

respect to capacitive voltage divider was studied by means 

of an example circuit (Figure 5). At the supply net V DD, an 

impulse with a maximum voltage of 40V and a rise time 

of 1ns is applied. The capacitive coupling of transistor T3, 

T2 and the resulting gate-source damage of T6 are well 

modelled during the DC-simulation. 

Figure 5. Example circuit for test of DC-models 

4. Example of Use 

To verify the behaviour of the algorithm under real conditions, 

DC-simulations and transient simulations are carried 

out and compared to each other. The first example is a 

driver stage of a communication controller, which consists 

of bipolar, low-voltage and high-voltage devices. The total 

device count is 139. 

The correlation between transient and DC-simulation results 

is shown in Figure 6. A good correlation may be 

observed for currents larger than 1% of the maximum 

current, showing the applicability of the approximation for 

a worst case analysis. 

Figure 6. Correlation between transient and DCsimulation 

currents (normalized)

5. Comparison of Computing Time 

The approach presented in this publication assumes that a 

DC-simulation (@V max) takes less time than a transient 

analysis (ramp function t r@V max). To verify this assumption 

with different circuit sizes, the circuit presented in 

Paragraph 4 is repeatedly connected in parallel up to 200 

times. The resulting circuits are simulated transiently using 

a linear ramp and by a DC simulation in the operating 

point V=V max using the equivalent models described 

above. After this, the computing times are evaluated. 

Simulation Time [s] 

1000000 

100000 

10000 

1000 

100 


10 

70% 

60% 

50% 

40% 

30% 

20% 

10% 

1 

0% 

100 1000 10000 100000 

Device Count 

Transient Simulation DC Simulation Time Saving 

Figure 7: Computing time as a function of device 

count 

For the DC simulation a manual source stepping method is 

used to improve convergence, i.e. the DC-voltage is increased 

in three steps up to the maximum voltage Vmax and the result of the previous simulation acts as initial 

solution for the next analysis. During the transient simulation, 

the initial solution as well as the solution of all other 

time steps is found within a few iterations because of the 

small voltage variations between the time steps. 

Figure 7 shows time savings of 35% to 60% for the DC 

analysis compared to a transient simulation. This is not 

very large, but it has to be taken into account, that the DC 

models were not further simplified, but are rather more 

complex due to the added resistances so that the device 

count is 1.5 times higher for the DC-models than for the 

transient simulations models. Further work has to be done 

in the field of the simplification of the DC-Simulation 

models in order to enlarge the advantage in the computing 

time. 

6. Summary and Outlook 

In this publication, an algorithm is presented which is 

capable to analyze the behaviour of a complex mixedsignal 

IC in the case of an ESD-event during the early 

design phase. 

In a two-stage approach an equivalent DC-simulation is 

used to model the circuit behaviour at the end of the pulse 

Time Saving [%] 

190 

rise time (which is considered as the worst case), to identify 

endangered devices and to extract critical paths and a 

reduced schematic. In a next step this information can be 

used to carry out a more detailed (transient) analysis. It is 

shown that the deviations resulting from the used approximations 

are small enough for a worst-case analysis. 

Further investigations are necessary to increase the time 

efficiency of the simulation models and the automation 

level of the entire analysis flow. Furthermore, parasitic 

capacitances and resistances should be included after a 

parasitic extraction of the layout is done. 

With the current state of the tool it is possible to find endangered 

devices by a total IC analysis. Furthermore, the 

involved current paths, which can run in a complicated 

way across several parasitic paths and through different 

blocks and hierarchical levels, were identified and visualised 

inside the CAD environment. 

In this way the reliability of the ESD analysis is increased 

enormously and future redesigns can be reduced. 

7. References 

[1] P. Rahinkar, P. Patersin, L. Singh, „System-ona-chip 

Verification“, Kluwer Academic Publishers 

2002 

[2] M. Baird, R. Ida, “VerifyESD: A Tool for Efficient 

Circuit Level ESD Simulation of Mixed- 

Signal ICs”, EOS/ESD Symp. 2000, pp 465-469 

[3] J. Lee, K. W. Kim, S. M. S. Kang, „VeriCDF: A 

new Verification Methodology for Charged Device 

Failures“, 39th Design Automation Conference 

2002 

[4] M. Streibl, F. Zängl, K. Esmark, „High Abstraction 

Level Permutational ESD Concept Analysis“, 

EOS/ESD Symp. 2003 

[5] P. Ngan, R. Gramacy, C. K. Wong, “Automatic 

Layout Based Verification of Electrostatic Discharge 

Paths”, EOS/ESD Symp. 2001, pp. 96- 

101 

[6] Cadence Design Systems, “SKILL Language 

Reference”, June 2000 

[7] Cadence Design Systems, “Cadence Design 

Framework II”, June 2000 

[8] A. Amerasekera, C. Duvvury, „ESD in Silicon 

Integrated Circuits“, J. Wiley & Sons 2002 

The reported R+D work in this paper is carried out in the 

frame of the MEDEAplus/Eureka project A509 MESDIE. 

This particular research is supported by the BMBF 

(Bundesministerium fuer Bildung und Forschung) of the 

Federal Republic of Germany under grant 01M3061H. 

The responsibility for this publication is held by the authors 

only.


HALOTIS – HIGH ACCURATE LOGIC TIMING 

SIMULATOR 

P. Ruiz-de-Clavijo, M.J. Bellido, J. Juan. 

Dpto. Tecnología Electrónica – Universidad de Sevilla – Spain 

Instituto de Microelectrónica de Sevilla – CNM - Spain 

E-mail: paulino@dte.us.es 

ABSTRACT 

This paper present a novel logic-timing simulator that 

includes the Degradation Delay Model (DDM) called 

HALOTIS. DDM obtains high accuracy in glitches 

treatment and it has been included in HALOTIS 

simulation engine. Also, it is possible to estimate 

switching activity using it, and the results show a high 

accuracy in simulations when these are compared to 

HSPICE. 

1.MOTIVATION 

One of the key points in modern CMOS VLSI system 

design is power consumption. On one hand, limited 

power consumption is a major design constraint in 

portable and battery powered devices, while, on the 

other hand, common desktop processor consumptions are 

reaching values of hundreds of watts, which may 

seriously compromise reliability and cooling capabilities. 

Therefore, accurate power analysis has become an 

integral part of the design verification tasks. 

Very accurate power estimations may be obtained 

through circuit-level electrical simulation using SPICElike 

tools. These, however, are only applicable to small 

circuits or critical units due to the high CPU time and 

computational resources required by circuit-level 

simulation. Most practical power estimations need to be 

done at higher level of abstraction: logic-level or higher. 

This work is about a logic-level simulation tool that 

incorporates accurate power estimation capabilities. 

Logic-level simulation like vss [1], modelsim [2] or 

verilog-xl [3] may be used to obtain power estimations 

through the analysis of the switching activity. Most of 

the power consumed in digital CMOS circuits is 

dynamic power (due to signal switching) which can be 

obtained from the operation of logic-level simulators. 

Total power (or current) consumption is then evaluated 

by using a current model for the switching signals. The 

accuracy of the estimation thus obtained will largely 

depend on the ability of the logic-level simulator to 

provide the correct switching activity. However, it is 

well known that current logic-level simulators largely 

overestimate the switching activity 30% or more is often 

observed- [4] because of a poor treatment of the 

generation and propagation of “glitches” or marginal 

pulses that are otherwise filtered in reality. The ultimate 

reason to this lack of accuracy is the dynamic nature of 

glitch propagation, which is not taken into account in 

traditional logic-level behavioural models. This may 

become a major issue as logic-level power estimations 

191 

become popular and are used to drive low-power logic 

synthesis. 

In the past few years, our research group has developed 

logic-level behavioural models which explicitly 

incorporates the treatment of glitches through the socalled 

Delay Degradation Model (DDM) [5]. The main 

objective of this work is to develop a logic-level 

simulator called HALOTIS (High Accurate LOgic 

TIming Simulator), [6] that implements the DDM and is 

then able to obtain accurate estimations of the switching 

activity and current consumption (thus power) at the 

logic level, overcoming the common logic-level 

simulator limitations. To do that, HALOTIS includes 

and advanced current model for logic transitions and a 

novel logic-simulation algorithm. Besides, HALOTIS is 

a fast and very accurate timing simulator. 

In the next section we present the current model. 

Section three summarizes some results, which are 

shortly discussed in section four. 

2.HALOTIS: HIGH ACCURACY 

LOGIC-TIMING SIMULATOR 

The main objective of this work is to build a logic-level 

simulation tool called HALOTIS. The main aspects we 

consider in HALOTIS developing can be summarized as 

follow: 

• The simulation engine includes the DDM proposed in 

previous papers [5]. This means a very high accuracy in 

simulation of glitches. Also, the new algorithm for the 

inertial effect [7] greatly improves the accuracy with 

respect to the traditional approach. 

• Includes an algorithm to caculate switching activity. 

The switching activity is used in other design tools to 

use low power design technics as for example Power 

Compiler [1]. At the present moment we are studying 

the SAIF [1] format specification to achieve that these 

results can be used in other optimization tools. 

• An algorithm to get the current waveform. The basic 

idea consists in to use a triangular waveform for the 

current. This triangle is characterized by the Imax, tmax 

(maximum current and the time), the begining and the 

end of triangle. To calculte Imax and tmax we are studying 

differents models that exists in literature [8, 9]. A 

preliminar current waveform results has been 

presented in [10].

As we can see, we are developing a logic level simulation 

tool aimed to get accuracy estimation of power and 

current consumption. 

3.THE DEGRADATION DELAY 

MODEL 

Typical models for logic simulation only consider the 

inertial effect to deal with very narrow pulses. These 

models show discontinuous behavior for very similar 

input conditions. Unlike the actual behavior, this 

discontinuity is due to the fact that depending on its 

width, an input pulse may be in a normal propagation or 

a filtering (non-propagation) region. Nevertheless, the 

change in the behavior of a true gate is not abrupt, rather 

continuous and gradual. In fact, two limit cases appear in 

real behavior: one for wide pulses that are propagated 

normally and another for very narrow pulses that are 

eliminated, but there is a pulse-width range between 

them in which pulses are neither eliminated nor 

propagated normally. Inside this range, the output pulse 

width is smaller than the corresponding input pulse 

width. In such a case, the pulse is considered to be 

degraded. 

We showed in [5] that the delay decreases exponentially 

as pulses are shortened. Full degradation effect insights 

were studied for the case of CMOS gates and a delay 

model that took into account the exponential behavior of 

the degradation effect was also presented. Now, we 

summarize some conclusions: only two parameters for 

each type of transition, � and T 0 , are needed to model 

the degradation effect, resulting in the following 

formula: 


t p =t �1−e p0 −� T −T 0 

� 

� � 

(1) 

where t p0 is the normal propagation delay, that can be 

calculated using a conventional delay model [11], T is 

the time elapsed since the last output transition in the 

gate's output took place, which measures the internal 

state of the gate, and � and T 0 are the degradation 

parameters which depend on the output load ( C L ), the 

supply voltage ( V DD ), the input transition time ( �in ) 

and the position of the input that is changing state ( I ). 

It has been obtained in [15] that this dependence can be 

expressed as: 

� ×V = A �B ×C 

x DD xi xi l (2) 

T 0 x =� 1 

2 − C xi 

V DD � 

� in 

where "x" stands for "r" or "f" depending on the sense 

of the output transition (rise or fall respectively). 

4.CURRENT MODEL 

(3) 

Global current calculation is obtained by summing up 

the current driven by each circuit cell individually from 

the power supply. For a given cell we assume that the 

current only circulates during the logic switching of the 

cell's output. Fig. 1 shows the currents involved in a 

192 

CMOS inverter structure when a raising output 

transition takes place. The main currents taken from 

V DD during the inverter's switching process are I CL and 

I SC . I CL is the current that charges the inverter output 

node, and I SC is the short-circuit current which goes 

directly from V cc to GND while the NMOS part is still 

conducting. When we deal with raising output 

transitions, the total current driven from the power 

supply is the sum of I CL and I SC . For falling output 

transitions, the capacity C L is discharged, and the only 

component taken from the power supply is I SC . 

The actual current curve in the gate, as obtained with 

HSPICE electrical simulator [3], is shown in Fig. 2-b. 

Our model proposes to fit the actual current curve by a 

triangle-shaped, two-pieces linear curve. The triangle 

approximation can be seen in Fig. 2-a. 

Figure 1. CMOS Inverter currents during logic 

switching. 

(a) (b) 

Figure 2. Inverter switching curves. (a) Triangle 

current model. (b) HSPICE simulation 

This approach is similar to that proposed by other 

authors [12,13], but using a simpler characterization 

method. The triangular shape is defined by three points: 

the triangle starting point instant ( T b ), the current 

maximum value and the instant when it takes place ( 

T max , I max ), and the instant time where the triangle 

ends ( T e ). 

These points can be approximated as follows: T b is the 

instant when the input transition starts and the point T e 

is the instant when the output transition ends, which are 

both known. To calculate I max and T max we use the

model proposed in [8]. In that work, the authors obtain 

the following equations: 

I max =� 


2 

K ×W ×V ×�C �C � 

p p DD L SC 


T max = �C L �C SC �V DD 

I max 

(4) 

(5) 

where K p and W p are respectively the 

transconductance factor and width of the PMOS 

transistor, V DD is the supply voltage, C SC is the 

short-circuit capacitance as defined in [8] and � in is the 

transition time of the input. 

On the other hand, for falling output transitions we only 

have to consider the short-circuit current I SC , so that: 

I max =� 

2 

K ×W ×V ×C 

n n DD SC 

In this case, T max is the time when input transition 

crosses the inverter input 


(6) 

threshold. 

The proposed model allows the calculation of an 

approximated, triangle-shaped current curve for every 

output transition of a cell, only based on cell parameters 

and timing data provided during logic simulation. 

5.RESULTS 

We have already got a first version of HALOTIS [6, 10] 

and we have got the first results that now are going to 

summarize. In Fig. 4, 5 and 6, we shows the output 

waveform of a 4x4 multiplier circuit (Fig. 3) obtained 

with HSPICE, VERILOG and HALOTIS respectively. 

The results shows that, effectively, in VERILOG 

simulation there are many glitches that in HALOTIS and 

HSPICE there is not. 

Figure 3. 4x4 multiplier circuit. 

193 

On the other hand, with this version of HALOTIS is 

possible to calculate switching activity (SA) of circuits. 

So, in Table 1 we shows the results of SA for two 

different input sequences of the circuit of Fig.1a 

obtained with HSPICE, HALOTTIS and VERILOG. The 

results are very significant in sense that VERILOG give 

large overstimations of the switching activity (even 

above 60%) while HALOTIS is within 5% respect to 

HSPICE. 

This results shows that HALOTIS could be a very 

interesting tool to be used when would be necessary to 

obtain accurate data about the dynamic behaviour 

(timing and power) of a design. 

Figure 4. Out waveforms of HSPICE simulation 

Figure 5.Out waveforms of VERILOG 

simulation.

Figure 6. Out waveforms of HALOTIS-DDM 

simulation. 

Table. 1. Transitions count for sequences A and B. 

Seq HSPIC 

E 


HALOTIS 

(%error) 

VERILOG 

(%error) 

A 416 408 (2%) 697 (68%) 

B 584 608 (4%) 857 (47%) 

6.REFERENCES 

[1] http://www.synopsys.com 

[2] http://www.mentorgraphics.com 

[3] http://www.cadence.com 

[4] Baena, C. and Juan, J. and Bellido, M. J. and Ruizde-Clavijo, 

P. and Jimenez, C. J. and Valencia, M., 

Measurement of the switching activity of CMOS 

digital circuits at the gate level, Proc. 12th 

International Workshop on Power and Timing 

Modeling, Optimization and Simulation (PATMOS), 

pp. 353-362., September 2002, Seville – Spain. 

[5] Bellido-Díaz, M. J. and Juan-Chico, J. and Acosta, 

A. J. and Valencia, M. and Huertas, J. L., Logical 

modelling of delay degradation effect in static 

CMOS gates, IEE Proc. Circuits Devices and 

Systems, no. 2, Vol. 147, pp. 107-117, April 2000. 

[6] Ruiz-de-Clavijo, P. and Juan, J. and Bellido, M. J. 

and Acosta, A. J. and Valencia, M., HALOTIS: 

High Accuracy LOgic TIming Simulator with 

Inertial and Degradation Delay Model, Proc. 

Design, Automation and Test in Europe (DATE) 

Conference and Exhibition, Munich - Germany, 

March 2001. 

[7] J. Juan-Chico, M. J.and Bellido, A. J. Acosta, and 

M. Valencia, Inertial effect handling method for 

CMOS digital IC simulation IEE Electronics 

Letters, Vol. 35, pp. 2028–2030, 1999. 

[8] P.Maurine, R. Poirier, N. Azémard, D. Auverne, 

Switching current modeling in CMOS inverter for 

194 

speed and power estimation, Proc. 16th Conference 

on Design of Circuits and Integrated Systems 

(DCIS), pp. 618-622, Porto - Portugal, Nov. 2001. 

[9] L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, 

Analytical transient response and propagation delay 

evaluation of the CMOS inverter for short-channel 

devices, IEEE Journal of Solid-State Circuits, vol. 

33, pp. 302–306, February 1998. 

[10] P. Ruiz-de Clavijo, J. Juan, M. J. Bellido, A. 

Millán, and D. Guerrero, Efficient and fast current 

curve estimation of CMOS digital circuits at the 

logic level, Proc. 12th International Workshop on 

Power and Timing Modeling, Optimization and 

Simulation (PATMOS), pp. 400–408, Springer, Sep. 

2002. 

[11] Daga, J. M. and Auvergne, D., A comprehensive 

delay macro modeling for submicrometer CMOS 

logics, IEEE Journal of Solid-State Circuits, Vol. 

34 – 1, 1999 

[12] Bogliolo, A. and Benini, L. and De Micheli, 

Giovanni and Riccò, B., Gate-level power and 

current simulation of CMOS integrated circuits, 

IEEE Trans. on very large scale of integration 

(VLSI) systems, Vol. 5 no. 5, pp. 473-488, Dec 

1999. 

[13] Nikolaidis, S. and Chatzigeorgiou, A., Analytical 

estimation of propagation delay and short-circuit 

power dissipation in CMOS gates., International 

journal of circuit theory and applications, Vol. 27, 

pp. 375-392, 1999


TEST PATTERN FOR MICROWAVE 

DIELECTRIC PROPERTIES OF SrBi2Ta2O9 

Nicola Delmonte 1 , Bernard Enrico Watts 2 , Lorenzo Rosa 1 , Giovanni Chiorboli 1 , 

Paolo Cova 1 , Roberto Menozzi 1 

1 Dipartimento di Ingegneria dell’Informazione, University of Parma 

Parco Area delle Scienze 181/A, I-43100 Parma, ITALY 

2 IMEM/CNR, Viale delle Scienze 37/A, I-43100 Parma, ITALY 

E-mail: delmonte@ee.unipr.it 

ABSTRACT 

A test structure employing a one-step lithography process 

has been built for measuring the complex impedance of 

ferroelectric capacitors at microwaves. The measurements 

are compared to the results of a finite element analysis 

with the aim of developing an electrical model of the test 

structure in which parasitic elements appear. These 

elements can be experimentally measured and partially 

de-embedded. 

The purpose of this paper is the characterization of 

strontium-bismuth tantalate (SBT) capacitors for 

microwave ICs or SoCs. 


Ferroelectric technology integrated with the 

complementary metal-oxide-semiconductor (CMOS) 

process has been proposed for some types of non-volatile 

memory and analog microwave circuits (e.g. resonators 

and filters). In recent years, several ferroelectric thin films 

have been studied at microwave frequencies; lead 

zirconate titanate (PZT) and barium-strontium titanate 

(BST) have been widely investigated. One interesting 

ferroelectric is the SrBi2Ta2O9 (strontium-bismuth 

tantalate), which has been studied because of its lower 

dielectric fatigue when used with Pt electrodes [1, 2]. 

However, the microwave dielectric properties of 

strontium-bismuth tantalate (SBT) have not yet been 

investigated as widely [3, 4]. The purpose of these studies 

is the microwave characterization of the dielectric 

properties of an SBT thin film. 

The dielectric properties of SBT make it a good material 

for the production of FERAM memories. Microwave 

characterizations may show other properties that could 

make it a good candidate for capacitors to be employed 

also in microwave circuits. 

In this experiment, a study of high frequency dielectric 

properties of an SBT thin film has been performed and an 

equivalent circuit model has been used to correct the 

measurements. 

195 

2. EXPERIMENTAL TECHNIQUE 

2.1 SBT deposition and top metal layer 

patterning 

Ferroelectric SrBi 2Ta 2O 9 (SBT) thin films were deposited 

onto a Pt(190 nm)/TiN(20nm)/SiO 2(100 nm)/Si-undoped 

substrate using a metal organic decomposition (MOD) 

preparation technique, adapted from a method described 

by Joshi et al. [5]. The starting materials used were: 

strontium acetate Sr(CH 3COO) 20.5H 2O; bismuth 2ethylhexanoate 

Bi(C 4H 9CH(C 2H 5)COO) 3; tantalum 

ethoxide Ta(CH 3CH 2O) 5; stabilising additives, 

methoxiethanol CH 3OCH 2CH 2OH and diethanolamine 

NH(CH 3CH 2O) 2; glacial acetic acid as the solvent. The 

precursor solution was prepared according to the method 

described by Watts et al. [1] and was syringed through a 

0.2 µm filter on a 15x15 mm substrate and spun at 3000 

rpm for 60 s. The baking step was done on a hot plate at 

350 °C between spins. Finally, the SBT was crystallised at 

750 °C in flowing oxygen for 1 h. A total of 3 layers were 

deposited. After baking and crystallization, the SBT film 

was 70 nm thick. The thickness is estimated from a 

previous experiment. 

Si 

top view 

cross sectional view 

top-ground 

Au 

SBT 

Pt 

TiN 

SiO2 

Figure 1. Top and cross sectional view of the test 

structure (not to scale).

In order to measure the dielectric properties of the SBT 

layer, the simple shape of a circular patch capacitor was 

adopted, since it is a rather convenient method and can be 

made using a one-step lithography process [6]. To realize 

this shape we evaporated a 100 nm Au film on the SBT 

layer (Fig. 1). The Au patterns were defined by the lift-off 

technique, to match a 150 µm pitch coplanar G-S-G 

microprobe used for the measurements. A matrix of metalinsulator-metal 

(M-I-M) capacitors has been patterned 

with two different diameters, 50 and 100 µm, to de-embed 

the capacitance due to the top-ground metallization from 

the results provided by the vector network analyzer 

(VNA). 

Cd 

Figure 2. Lumped element equivalent circuit of 

the test structure. 

The circuit in Fig. 2 can electrically model the measured 

impedance. In this model, RcA and RcB are the contact 

resistances between the S probe tip and the circular patch, 

and between the G probe tips and the top-ground 

respectively, Cd and Ctg are the capacitances of the circular 

patch and the top ground respectively, while Rd and Rtg are 

resistances representing the dielectric losses of the two 

capacitors. Rs is the resistance of the Pt ring that connects 

the bottom electrode of the circular capacitor with the 

bottom electrode of the top-ground capacitor. Finally, Cp is the lateral parasitic capacitance that appears between the 

top two electrodes of the circular patch and the topground, 

while Rp is the lateral parasitic resistance between 

the same electrodes. This resistance is due to the SBT ring 

between the two desired capacitors of the test structure. 

If the capacitance Cp is low enough and the resistance Rp is large enough, the electrical model can be simplified as 

shown in Fig. 3, where Rt represents the series of RcA, Rs and RcB. Figure 3. Simplified lumped element equivalent 

circuit of the test structure. 

The impedance of this model is: 


Ctg 

RcA 

RcB 

A Rs 

B 

A 

Rd 

Cd 

Rp 

Cp 

Rtg 

Ctg 

Rt B 

Rd 

Rtg 

196 

Z 

AB 

R 

R 

d 

tg 

= Rt 

+ 

+ 

2 2 

2 

1+ 

ω R C 1+ 

ω R C 

d 

⎛ 2 

⎜ ω R 

− dC 

i 

d 

⎜ 2 2 

⎝ 

1+ 

ω RdC 

2 

d 

2 

d 

2 

tg 

2 

ω RtgCtg 

+ 

2 2 

1+ 

ω R C 

When C tg >> C d and R tg

To model the SBT layer we used the complex dielectric 

constant computed from data measured by the VNA using 

the methods described by Ma et al. [6] and Dube et al. [7]. 

3. RESULTS AND DISCUSSION 

3.1 Measurements 

The electric properties of dielectric material are described 

by the real part of the dielectric constant ε' and the loss 

tangent tanδ, which can be evaluated from C d and R d. 

Hence, it is necessary to de-embed the resistance R t and 

the impedance of the top ground from the results given by 

the VNA Anritsu 37347C VNA in the range 40 MHz ÷ 20 

GHz. 

Figure 5. Effect of de-embedding correction on loss 

tangent. 

First, the resistance Rt has been extracted according to [8], 

then the impedance due to the top ground (Ctg//Rtg) is deembedded 

by comparing the resulting impedances of two 

M-I-M capacitors of different areas. The results are 

reported in Fig. 5, with reference to the loss tangent. The 

same results were obtained by considering the top ground 

as a short circuit in the electrical model shown in Fig. 3. 

With this second method, after the Rt de-embedding the 

real part of the dielectric constant can be calculated from 

the measured susceptance Bm, by using the formula 

reported in Eq. 3: 

Bm 

⋅ t 

ε 'r 

= 

, (3) 

2π 

⋅ f ⋅ Ad 

⋅ ε 0 

where t is the dielectric thickness, A d is the electrodes area 

of the capacitor under testing and ε 0 is the vacuum 

dielectric constant. 

In addition to the real part of the dielectric constant, to 

give a complete description of the dielectric properties, it 

is necessary to evaluate the complex part of the dielectric 

constant ε’’ or, equivalently, it is possible to compute the 

loss tangent by using Eq. 4: 

Re 

⎧ ⎫ 

{ } ⎨ 

1 

ε '' 

Re Y 

⎬ 

m ⎩ Z m 

tanδ 

= = = 

⎭ 

, (4) 

ε ' Im{ 

Ym} 

Im 

⎧ ⎫ 

⎨ 

1 

⎬ 

⎩ Z m ⎭ 


197 

where Y m (Z m) is the admittance (impedance) measured 

after de-embedding R t. 

According to the model in Fig. 3, if the top-ground 

capacitor acts as a short-circuit, after the de-embedding R t, 

the measured susceptance, B m, versus frequency must 

follow a linear behaviour. We can estimate the frequency 

limit of the model from where the measured value of B m 

does not match the theoretical behaviour. When the VNA 

calibration step and the contacting between the probe tips 

and the electrodes of the test structure are done with care, 

the frequency limit is higher. For the structures measured, 

we observed a frequency limit up to about 10 GHz. tanδ 

becomes negative above this frequency, confirming the 

limit of the adopted model. Figures 6 and 7 show the 

results obtained for the real part of dielectric constant and 

the loss tangent with a zero voltage DC bias applied to the 

capacitors. 

Figure 6. Real part of dielectric constant as a 

function of frequency. 

Figure 7. Loss tangent as a function of frequency. 

Under this condition, starting from a value of about 43 at 

40 MHz, the dielectric constant decreases slightly with 

frequency down to a value of about 36 at 10 GHz. The 

loss tangent is always lower than 0.07. At higher 

frequencies the loss tangent is around zero.

3.2 Finite element analysis 

The numerical analysis was limited to the electrical field 

with low levels of current flowing in the plane, hence, 

inductive effects are negligible. The inward AC current 

density at the circular patch electrode was varied until the 

evaluated capacitance of the structure was equal to one 

obtained by the VNA for the 50 µm diameter patches 

(about 10 pF). When these capacitances are matched, the 

magnitude of the lateral parasitic impedance of C p in 

parallel to R p can be estimated. The results are shown in 

Fig. 8, where the magnitude of the impedance C p//R p is 

plotted for frequencies from 1 GHz to 20 GHz. 

Figure 8. Magnitude of the impedance C p//R P 

plotted versus frequency. 

Above 5 GHz the lateral parasitic impedance is less than 

10 MΩ and reaches about 3 MΩ at 20 GHz. 

A similar calculation shows that the resistance R s does not 

varies with frequency. The computed value to R s is 0.25 

Ω, similar to the obtained for R t by experimental 

measurements (≈0.6 Ω). 

The finite element analysis confirms that the top-ground 

capacitor acts as a short-circuit. 


4. CONCLUSION 

Results of the microwave characterization show that an 

SBT thin film produced using MOD technique has a low 

loss tangent in the in the 40 MHz ÷ 10 GHz range. The 

dielectric constant is shown to be around 40, lower than 

the expected value of 70 measured in previous 

experiments at low frequencies. 

The measurement technique adopted needs samples with 

simple top metal patterning that can be made with a one 

step lithography process. 

An improved model that takes a wider range of parasitics 

into account is proposed. The model is based on a finite 

element analysis of the structure. This analysis has shown 

that the approximations made for the computations of 

dielectric constant and loss tangent versus frequency are 

good and suggests taking into account the lateral parasitic 

element presented here. 

198 

5. REFERENCES 

[1] B.E. Watts, F. Leccabue, S. Guerri, M. Severi, M. 

Fanciulli, S. Ferrari, G. Tallarida, C. Morandi, “A 

comparison of Ti/Pt and TiN/Pt electrodes used with 

ferroelectric SrBi 2Ta 2O 9 films”, Thin Solid Films, 

vol. 406, pp. 23-29, 2002. 

[2] K. Amanuma, T. Hase, Y. Miyasaka, “Preparation 

and ferroelectric properties of SrBi 2Ta 2O 9 thin 

films”, Applied Physics Letters, vol. 66, pp. 221-223, 

1995. 

[3] Y. Wu, M.J. Forbess, S. Seraji, S.J. Limmer, T.P. 

Chou, G. Cao, “Impedance study of SrBi 2Ta 2O 9 and 

SrBi 2(Ta 0.9V 0.1)O 9 ferroelectrics”, Material Science 

and Engineering, vol. B86, pp. 70-78, 2001. 

[4] K. Kotani, M. Misra, I. Kawayama, M. Tonouchi, 

“Time- domain Terahertz Spectroscopy of Strontium 

Bismuth Tantalate Thin Films”, Materials Research. 

Society Symposium Proceedings, vol. 784, 2004. 

[5] P. C. Joshi, S. O. Ryu, X. Zhang, and S. B. Desu, 

“Properties of SrBi 2Ta 2O 9 ferroelectric thin films 

prepared by a modified metalorganic solution 

deposition technique”, Applied Physics Letters, vol. 

70, pp. 1080-1082, 1997. 

[6] Z. Ma, A.J. Becker, P. Polakos, H. Huggins, J. 

Pastalan, H. Wu, K. Watts, Y.H. Wong, P. 

Mankiewich, “RF Measurement Technique for 

Characterizing Thin Dielectric Films”, IEEE 

Transactions on Electron Devices, vol. 45, no. 8, 

August 1998. 

[7] D.C. Dube, J. Baborowski, P. Muralt, N. Setter, “The 

effect of bottom electrode on the performance of thin 

film based capacitors in the gigahertz region”, 

Applied Physics Letters, vol. 74, pp. 3546-3548, 

1999. 

[8] T.G. Kim, J. Oh, Y. Kim, T. Moon, K. Sun Hong, B. 

Park, “Crystallinity Dependence of Microwave 

Dielectric Properties in (Ba,Sr)TiO 3 Thin Films”, 

Japan. Journal of Applied Physics, vol. 42, pp. 1315- 

1319, 2003. 

[9] L.F. Chen, C.K. Ong, C.P. Neo, V.V. Varadan, V.K. 

Varadan, “Microwave Electronics: Measurements 

and Materials Characterization”, John Wiley & 

Sons, pp. 383-412, 2004. 

[10] M.J. Lancaster, J. Powell, A. Porch, “Thin-film 

ferroelectric microwave devices”, Supercond. Sci. 

Technol., vol. 11, pp. 1323-1334, 1998. 

[11] Y. Kim, J. Oh, T.G. Kim, B. Park, “Influence of the 

Microstructures on the Dielectric Properties of 

ZrTiO 4 Thin Films at Microwave-Frequency Range”, 

Japan. Journal of Applied Physics, vol. 40, pp. 4599- 

4603, 2001.


Design and Fabrication of a New System For 

Vibration Energy Harvesting 

Ghislain Despesse 1 , Thomas Jager 1 , Jean-Jacques Chaillout 1 , Jean-Michel Léger 1 

Skandar Basrour 2 

1 CEA/DRT – LETI/DCIS, 17 rue des Martyrs, 38054 Grenoble Cedex 09, France 

2 TIMA, 46 avenue Félix Viallet, 38031 Grenoble Cedex, France 

E-mail: despesse@cea.fr 

ABSTRACT 

Global simulations, designs and characterisations of a 

broadband vibration energy scavenging system are here 

reported. High damping electrostatic conversion 

structures have been investigated: Mathematica analytical 

models have been performed and confronted with 

ANSYS simulations. A scavenging electronics has also 

been developed: taking in account ohmic, capacitive and 

inductive losses, the global conversion efficiency has 

been calculated. Finally, a macro and a micro resonant 

structure tuned to 50 Hz have been realized. A scavenged 

power of 1 mW is already available on the macro 

structure under a vibration amplitude of 90 µm at 50 Hz. 

The corresponding global conversion efficiency is about 

60 % which is in good agreement with mechanical and 

electrical simulations. 


Advances in low power electronics and microsystems 

design open up the possibility to power small wireless 

sensor nodes thanks to energy scavenging techniques. 

Depending on the system environment, many different 

types of energy sources can be used: thermal, radiative, 

mechanical or chemical. Among these sources we had to 

choose one whose conversion system is adapted to size 

reduction. We finally decided to focus on mechanical 

surrounding vibrations.. As shown on Figure 1 and Figure 

2 and by other recent studies [1], surrounding mechanical 

vibration frequencies are mainly and widely distributed 

below 100 Hz. 

20 40 60 80 

Figure 1. Acceleration spectrum on a car 

Hz 

m.s A(f) 

0.25 

0.2 

0.15 

0.1 

0.05 

-2 

20 40 60 80 

Figure 2. Acceleration spectrum on a metallic stair 

Hz 

m.s 

0.3 

0.25 

0.2 

0.15 

0.1 

0.05 

-2 

A(f) 

199 

To convert most of these vibrations into electrical power it 

has been chosen to investigate conversion structures based 

on electrostatic transduction with high electrical damping. 

Many advantages are provided by the electrostatic 

conversion: it is easy to integrate and its power density is 

increased by the size reduction. Moreover, high electrical 

dampings are easily achievable through this transduction 

principle. Thus, and contrary to most of existing systems 

[1-3], our structures will be able to recover power over a 

large spectrum below 100 Hz. 

2. CONVERSION STRUCTURES 

2.1 Choice of the conversion system 

In a first step the mechanical behavior of the conversion 

structure has been approximated through a linear viscous 

damping model [4]. In function of the input acceleration 

A, its pulsation ω, the moving mass m, the resonant 

pulsation ωn of the structure and the mechanical and 

electrical damping ζm and ζe, the maximum mechanical 

scavenged power P is given by: 

P = 

⎛ 

⎜ 

⎜2 

⎝ 

( ζ + ζ ) 

e 

2 

mA ζ 3⎛ 

⎞ 

e ω 

ω ⎜ 

⎟ n 

ω n ⎝ ω n ⎠ 

2 

2 

ω ⎞ ⎛ ⎞ 

⎜ ⎛ ω ⎞ 

+ 1− 

⎟ 

⎟ 

⎜ ⎜ 

⎟ 

m 

ω ⎠ 

⎟ 

n ⎝ ⎝ ω n ⎠ ⎠ 

2 

We can easily see that the scavenged power is directly 

proportional to the moving mass and to the square of the 

input acceleration. An operation with a high electrical 

damping has been chosen to maximize the scavenged 

power for a wide number of applications (i.e. over a large 

frequency band) neglecting the mechanical damping 

compared to the electrical one. 

For all types of existing electrostatic microstructures (outof-plane 

gap closing, in-plane overlap or in-plane gap 

closing [2]) and their operating cycles (voltageconstrained 

or charge-constrained cycle [3]), the electrical 

damping is due to the electrostatic force Fe appearing 

between two mechanical parts (the moving mass and fixed 

electrodes) set at different potentials. For a high damping 

configuration, the electrostatic force has to counterbalance 

almost entirely the mechanical spring force Fm=kz, which 

is proportional to the relative displacement z and to the 

mechanical structure stiffness k. In agreement with the 

2 

(1)

electrostatic force characteristics presented in Table 1 in 

function of the conversion structure and its operation 

cycle, the most convenient configuration seems to be an 

in-plane gap closing structure with a charge constrained 

cycle. For this configuration, the electrostatic force Fe is 

also proportional to the relative displacement and can be 

expressed as Fe=kez where ke is defined as the electrical 

stiffness. 

Structure Q constrained V constrained 

Out-of-plane Fe constant Fe ~ 1/z 

In-plane 

Fe ~ 1/z2 Fe constant 

overlap 

In-plane gap 

closing Fe ~ z F e ~ 1/z 2 

Table 1. Electrostatic force variation for different 

system configurations 

A high electrical damping is finally achieved by choosing 

an electrical stiffness close to the mechanical one. 

2.2 Modeling and simulations 

Assuming an in-plane gap closing conversion structure 

operating in a charge cycle, Mathematica analytical 

models have been performed to determine the mechanical 

and electrical parameters that maximize the scavenged 

power for a wide number of applications. Based on former 

experimental vibration measurements, the recoverable 

power and the vibration amplitude have been estimated in 

function of the resonant frequency for high electrical 

damping configurations (i.e. ke/k close to 1). These 

calculations are summarized on Figure 3 for ke/k =0.67. 

20 40 60 80 

µm 

Displacement 

300 

250 

Metallic stairs 

200 

Drill 

150 

100 

Car engine 

50 Car driving 

100 

20 40 60 80 100 

fr(Hz) 

Figure 3. Recoverable power (a) and vibration 

amplitude (b) for a 1 g moving mass in function of 

the resonant frequency for ke/k=0.67 

fr(Hz) 

P(µW) Recoverable power 

30 Car driving Car engine 

25 

20 Drill Metallic stairs 

15 

10 

5 

Combining displacement (2 µW) constraints a 50 Hz resonant frequency 

has finally been chosen for our structures. 

As shown by Equation (1) the scavenged power is 

proportional to the moving mass: to scavenge a significant 

power it has thus been decided to increase the moving 


200 

mass of our future silicon microstructure by sticking an 

additional tungsten mass on the moving part. In order to 

early validate the scavenging electronics principles it has 

also been decided to realize an intermediate macro 

prototype in bulk tungsten alloy. 

Complementary FEA (Finite Element Analysis) 

simulations with ANSYS® have also been performed to 

validate our mechanical designs. 

Finally, the scavenged mechanical power was estimated 

for both prototypes thanks to global simulations whose 

results are reported in Table 2 along with main prototypes 

characteristics. 

Bulk tungsten Silicon 

Characteristics 

macrostructure microstructure 

Size 18 cm 2 x1 cm 81 mm 2 x0.4 mm 

Moving mass 104 g 2 g 

Cmin/Cmax 900 / 3590 pF 14 / 147 pF 

Resonant 

50 Hz 50 Hz 

frequency 

Maximum 

116 µm 95 µm 

displacement 

Maximum 

scavenged power 

6 mW 70 µW 

Table 2. Characteristics and calculated 

performances of the prototypes 

2.3 Realizations 

The macroscopic conversion structure has been realized in 

bulk tungsten thanks to electrical discharge machining 

(EDM). This technique is a good compromise to test and 

validate the electronics principle. The structure is 

presented on Figure 4. 

Figure 4. Bulk tungsten prototype 

The second prototype is a silicon one whose realization 

process is based on Deep Reactive Ion Etching techniques 

as presented on Figure 5: 

Step 1 

Step 2 

Step 3 

Figure 5. Flowchart for the silicon prototype 

Flowchart description: 

� Step 1: Etching of the back face silicon cavity

� Step 2: Wafer bonding and Aluminium metallization 

� Step 3: DRIE Etching and structure release 

Many advantages can be achieved with size reduction: a 

higher capacity range and a higher quality factor with a 

smaller system size. On the Figure 6 is presented the final 

structure. 

Figure 6. Silicon prototype 

The measured resonant frequency of the tungsten 

prototype is a little lower than 50 Hz and the effective 

maximum vibration amplitude of its moving mass is 

limited to 90 µm. This is due to limitations inherent to the 

EDM combined with the inaccuracies of the final 

assembling of moving and fixed elements. 

Instead of the 6 mW of scavenged power initially expected 

with a 116 µm maximum displacement at 50 Hz, the 

maximum expected power at 50 Hz is then reduced to 1.76 

mW. 

3. CONVERSION AND 

MANAGEMENT ELECTRONICS 

As the variable capacitance structure is driven by 

mechanical vibrations, it oscillates between a maximum 

capacitance Cmax and a minimum capacitance Cmin. The 

maximum capacitance is variable and depends on the 

displacement amplitude and Cmin is fixed by the initial 

equilibrium position of the structure. For a charge 

constrained operating cycle a given charge is injected 

under a initial Vmin voltage on the structure when the 

maximum of capacitance is reached. An electrostatic force 

appears and absorbs a part of the mechanical movement 

until the structure reaches its equilibrium position. The 

injected charge is then recovered under a higher Vmax 

voltage. The maximum recoverable energy per cycle is 

given by: 

1 

E = VminVmax 

( Cmax 

− Cmin 

) (2) 

2 

To observe the influence of the effective movement 

amplitude on the capacitance and the voltage variations, 

the response to a decreasing sinusoidal movement has 

been simulated for an arbitrary structure size. Results are 

presented on Figure 7. 

z(t) 


moving part 

fixed part 

201 

0.01 0.02 0.03 0.04 t(s) 

-10 

-20 

10 

µm 

20 

Relative displacement 

0.01 0.02 0.03 0.04 t(s) 

150 

100 

50 

pF 

Variable capacity's value 

0.01 0.02 0.03 0.04 t(s) 

3 

2 

1 

nC Variable capacity's charge 

0.01 0.02 0.03 0.04 t(s) 

V 

120 

80 

40 

Variable capacity's voltage 

Figure 7. Charge-constrained cycle operation 

As the vibration amplitude decreases, the difference 

between the charge and discharge energy decreases, as 

does the converted energy. 

An efficient detection of maximum and minimum of 

capacitance is needed to work properly. A driving circuit 

between the storage unit and the variable capacitance is 

also required for the charge and the discharge. 

3.1 Detection of capacitance extrema 

The capacitance extrema detection can be achieved by 

injecting a known high frequency current in the variable 

capacitance: the capacitance can be measured by filtering 

or/and by using a synchronous detection. Unfortunately 

the power consumption of circuits based on this operating 

principle is too high. Instead of measuring the capacitance 

value we therefore focused on the measurement of the 

capacitance voltage derivative. However this solution 

works only if there is always a residual charge on the 

variable capacitance: instead of entirely discharging the 

capacitance at every cycle, the discharge will not be totally 

completed. 

With this residual charge on the variable capacitance, a 

first extremum of the capacitance voltage is achieved 

when the capacitance is maximum. An additional effective 

charge is then loaded on the capacitance. When the 

capacitance becomes minimal, the voltage is maximum 

and reaches a second extremum: the capacitance is almost 

entirely discharged and a new conversion cycle starts. 

3.2 Power management 

Controlled by the detection stage, the charge and the 

discharge of the variable capacitance are achieved through 

a Flyback structure presented on Figure 8: 

Lp Ls E C 

Kp 

Ks 

Figure 8. Flyback power structure 

Vc

This structure has many advantages. The first one is that 

the storage unit side could be easily integrated (voltage 

lower than 5 V). Only one transistor (Ks) is still subjected 

to high voltage: the leakage current losses and the parasite 

capacitance losses are limited. 

The second one is that the number of turns on each side of 

the magnetic circuit can be adjusted to have the same 

switch-on time for both Kp and Ks transistors. 

The third advantage is that the transistors commands are 

referenced to the same ground potential. 

To charge the variable capacitance, the transistor Kp is 

switched on long enough for the magnetic circuit to be 

loaded with the requested energy. This energy is then 

transferred in the variable capacitance when Kp and Ks are 

respectively switched off and on: Ks is kept on until the 

magnetic circuit is entirely discharged in the variable 

capacitance. 

To discharge the variable capacitance, Ks is first switched 

on to transfer the capacitance energy in the magnetic 

circuit. Then, Kp and Ks are respectively switched on and 

off and the energy is transferred from the magnet circuit 

into the storage unit. 

Apart from the charge and the discharge, Kp and Ks are 

kept open. 

Experimental measurements of this charge and discharge 

cycles on the bulk tungsten macrostructure are reported on 

the Figure 9. These measurements are in good agreement 

with simulations. 

150 

100 

50 

-4 4 8 

Vc(V) 

Vc 

300 

250 

200 

150 

100 

50 

Figure 9. Charge and discharge cycle for a 30 Hz 

sinusoidal mechanical excitation. 

Experimental charge and discharge times have been 

measured in the µs range: as expected they are negligible 

compared with the mechanical cycle period (in the ms 

range). 

3.3 Power balance and conversion efficiency 

All parasitic losses associated to the magnetic circuit and 

the transistors have been taken in account to estimate the 

power balance of the global system presented in Figure 10 

for the tungsten prototype. 

These parasitic elements have been measured and then 

implemented in modeling to simulate the loss repartition. 

Once these elements taken into account, simulations are in 


Simulation 

t (µs) 

Vc(t) 

300 

250 

200 

150 

100 

50 

Vc 

2.5 5 7.5 10 12 .5 

4 8 12 

Measurement 

t(ms) 

t (µs) 

202 

good agreement with measurements. The power balance is 

almost proportional to the mechanical frequency and is 

strongly linked to the relative displacement amplitude. For 

the tungsten prototype, the power balance becomes 

positive for vibration amplitudes higher than 60 µm. 

As presented on Figure 10 for a vibration amplitude of 90 

µm at 50 Hz, the global scavenged power is about 1052 

µW with an absorbed mechanical power of about 1760 

µW. The global efficiency is thus close to 60 %. 

Self maintenance power 

1.9 mW 

Mechanical energy 

1.8 mW Transduction 3.4 3mW 

1.9 mW 1.7 mW 

mW 1mW 

Scavenged 

-170 µW -78 µW -460 µW power 

Charge losses Transduction losses Discharge losses 

Figure 10. Power balance for the tungsten 

prototype (50 Hz; vibration amplitude of 90 µm) 

With size-reduction we can expect an higher conversion 

efficiency due to a better mechanical accuracy and a 

higher quality factor in the silicon prototype realization. 

4. CONCLUSION 

Global simulations have been performed on a high 

damping electrostatic system for vibration energy 

scavenging. A macrostructure in bulk tungsten and a 

silicon microstructure have been designed along with the 

associated management electronics. In agreement with 

simulations, 1mW of scavenged power is already 

delivered by the tungsten prototype with a global 

conversion efficiency of 60 % submitted to a sinusoidal 

vibration amplitude of 90 µm at 50 Hz. In situ 

measurements have also been performed and up to 250 

µW have been scavenged on a car engine. First conversion 

results with the silicon microstructure are expected soon 

and shall be about a few ten µW. 

5. REFERENCES 

[1] S. Roundy, P. K. Wright, and J. Rabaey, "A study of 

low level vibrations as a power source for wireless 

sensor nodes", Computer Communications, vol. 26, 

1131-1144, 2003. 

[2] S. Roundy, P. K. Wright and K. S. J. Pister, "Micro- 

Electrostatic Vibration-to-Electricity Converters", 

Proceedings of IMECE2002, 1-10, 2002. 

[3] S. Meninger, "A Low Power Controller for a MEMS 

Based Energy Converter", Master of Science at the 

Massachusetts Institute of Technology, 1999. 

[4] C. B. Williams and R.B Yates, "Analysis of a microelectric 

generator for microsystems", Proceedings of 

the Transducers 95/Eurosensors IX, 369-372, 1995.


NONLINEAR VIBRATIONS OF A MEMS 

TRANSLATIONAL DEVICE 

Elisabetta Leo, Francesco Braghin, Ferruccio Resta. 

ABSTRACT 

When significantly displacing a proof mass, the nonlinear 

hardening characteristic of the supporting beams becomes 

visible. Thus, the resonance peak of the structure is no 

longer vertical but bends towards the higher frequencies. 

This property is useful to easily synchronise sense and 

drive resonances thus increasing the sensibility of the 

MEMS device. Through a test structure designed to 

investigate the high deformation range of the supporting 

beams, its nonlinear vibrations were investigated both 

experimentally and numerically. 


The typical structure of a tuning-fork MEMS gyroscope 

consists of a proof mass supported by polysilicon beams. 

The proof mass is set into vibration along the drive 

direction through the comb-drive capacitor. In presence of 

an angular speed (ωz) perpendicular to the drive direction. 

Coriolis acceleration determines a force along the out-ofplane 

direction (sense direction) having the same 

frequency as the driving force and proportional both to the 

speed of the proof mass along the drive axis and to the 

angular rate. 

To increase the sensitivity of the gyroscope (i.e. to obtain 

higher displacement along the sense direction) the 

eigenfrequencies along drive and sense directions should 

be equal to the driving frequency [1] and a low damping 

ratio (low pressure level) should be aimed for. However, 

low damping means narrow resonance peaks. Small 

variations in the eigenfrequencies (e.g. due to small errors 

in the production process) would therefore lead to a very 

small sensitivity. Complex control logic have thus to be 

implemented. Otherwise, to achieve high sensitivity even 

in presence of production errors, it is necessary to relax 

the constrain that the two resonance peaks have the same 

frequencies. 

The solution proposed in this paper relies on the nonlinear 

characteristics of the device. A test structure (Figure 1) to 

achieve high displacements and thus to experimentally 

study the non-linear behaviour of MEMS was designed 

and produced with the support of STMicroelectronics. It 

consists of a proof mass suspended through four beams 

and forced by twenty comb-drives along the x-axis (drive 

direction). 

Polytechnic of Milan, Mechanical Department, 

Via La Masa 34 Milan, Italy 

E-mail: elisabetta.leo@polimi.it 

203 

Sense direction (y-axis) 

Drive direction (x-axis) 

Figure 1. Layout of the test structure to access the 

nonlinear behaviour of supporting beams 

2. NUMERICAL MODEL 

Since only the first eigenfrequency of the system is of 

interest, a lumped parameter model of the test structure 

has been developed. Moreover, due to the fact that the test 

structure was designed to access the nonlinear behaviour 

of MEMS devices and is not a fully working MEMS 

gyroscope, only the motion equation along the drive 

direction is of interest: 

m ⋅�� x + c ⋅x � + k(x) = f ⋅sin(ω 

t) 

drive drive 

where ‘x’ is the displacement of the test structure along 

the drive direction, ‘m’ is the proof mass, ‘k’ and ‘c’ are 

respectively the stiffness and the damping coefficients 

along the drive axis and the right-hand term of the 

equation is the actuation force. 

In order to correctly determine the non-linear stiffness 

“k(x)” of the supporting beams, a FEA model has been 

used. Due to the symmetry of the test structure the proof 

mass is bounded to translate along the x-direction. Thus, 

the boundary condition of the FEA model of a single 

supporting beam are an encastre at one beam end and a 

sliding-block constraint at the other end. Two different 

FEA models were used to study the influence of element 

types: one “beam model” and one “shell model”. In the 

“beam model” 260 beam elements were used while in the 

“shell model” the supporting beam is discretized through 

1800 shell elements. For both models, the beam cross 

section is supposed to be rectangular and constant over the 

beam length. The simulated characteristic curve (force vs. 

displacement) of a single supporting beam is shown in 

Figure 2. As expected, the two models give almost the 

same results. Moreover, a hardening behaviour is clearly

visible. To speed-up the dynamic simulation necessary to 

access the nonlinear behavior of the test structure, an 

analytical description of this characteristic curve would be 

very useful. Thus, the simulated characteristic curve of a 

single supporting beam was approximate through a cubic 

relation: 

3 

F=k(x) ≅ Kx+K x 

1 3 

F being the applied force at the free end of the beam, x 

being the displacement at the same end and K1 and K3 the 

linear and cubic stiffness constants respectively. The curve 

approximation is carried out using a nonlinear curvefitting 

algorithm.Figure 3 shows the results of the 

approximation procedure: the fitted characteristic curve 

and the simulated one are almost overlapped. 

Figure 2. Hardening characteristic curve of a 

single supporting beam obtained through FEM 

analysis 

Figure 3. Comparison between simulated and 

approximated hardening characteristic curve. 

Using this cubic approximation of the supporting beams’ 

characteristic, the differential equation that governs the 

motion along the drive axis becomes: 


2 

b 1 b 3 drive drive 

m⋅�� x+c⋅x+N � kx+N k x = f sin(ω t) 

where ‘Nb’ is the number of beams that support the proof 

mass. While the parameter ‘m’ is easy to determine , the 

value of the damping coefficient is dependent on the 

working pressure of the device. Ambient pressure level is 

considered.. 

The following simplifying assumptions were made: 

• the stiffness effects due to the compressibility of the 

fluid can be neglected with respect to the stiffness 

introduced by the supporting beams; 

204 

• the structural damping of polysilicon can be neglected 

with respect to the viscous damping due to the air 

surrounding the structure (being of an order of 

magnitude smaller). 

To model the viscous damping, Couette flow and squeeze 

film damping [2] are used: 

c = cflow + csqueeze 

Approximating air as a Newtonian fluid, flow and squeeze 

film damping are equal to: 

A 

c flow = -µ 

y 

0 

2N ⋅l⋅h c squeeze = µ 

y 

comb 

µ being the viscosity constant of air at ambient 

temperature and pressure, A being the area of the 

overlapped plates, y 0 being the distance between the 

parallel surfaces, N being the number of comb fingers, l 

being the length of these fingers, h being the thickness of 

the structure (and therefore of the fingers) and y comb being 

the distance between two fingers. As already said, the test 

structure is set into vibration through a series of comb 

drives to achieve a high actuation forces and therefore 

high displacements. To avoid having a driving force with 

multiple frequencies, the pulsating component of the 

voltage applied to the two stators of the comb drive has 

opposite sign. Thus, the driving force is equal to 

⎛ h ⎞ 

F () t = 2N⎜ε ⎟VDC 

VACsin( ωdt) 

= 

⎝ ycomb 

⎠ 

= f sin t 

( ω ) 

drive drive 

where ε is the dielectric constant of air, VDC and VAC are 

the amplitudes of the applied constant and pulsating 

voltages respectively and ωdrive is the drive frequency. 

The equation of motion along drive direction can therefore 

be rewritten as: 

3 

m⋅ �� x+ c⋅ x� + k1x+ k3x = 

⎛ h ⎞ 

= 2N⎜ε ⎟VDC 

VAC sin ωdrivet 

⎝ ycomb 

⎠ 

( ) 

This non-linear, constant parameter, second order 

differential equation is known as Duffing equation. Even 

though simple, there isn’t any analytical solution. Thus, to 

solve it two ways are possible: a semi-analytical approach 

or a numerical approach. The semi-analytical approach is 

based on Galerkin-Urabe’s method [3] and allows to 

determine only regime solutions (both stable and unstable 

solutions) in a very fast and efficient way; the numerical 

approach (e.g. Runge-Kutta’s method),instead, allows to 

determine both the transient response and the stable 

regime solution but requires a much higher computational 

effort 

2.1 Semi-analytical method

The semi-analytical method used to solve the non-linear 

equation of motion of the test structure along drive 

direction is the Galerkin-Urabe method.The basic idea 

behind this method is that, although non linear, when a 

system is forced by a sinusoidal actuation force the system 

will have a periodic regime response. Thus, the regime 

response can be written as a Fourier series: 

xt () = a1cos( ω1t) + b1sin( ω1t) 

+ 

+ a2cos( ω2t) + b2sin( ω2t) 

+ ... 

where the frequencies ‘ωi’ are multiples (super - 

harmonics) or fractions (sub - harmonics) of the frequency 

ωdrive of the actuation force. Due to the cubic non-linearity 

introduced by the supporting beams, it can be shown that 

the system’s response is a function of only odd 

frequencies Thus the system’s response x(t) is equal to: 

⎛ωdrive ⎞ ⎛ωdrive ⎞ 

xt () = ... + a1/3 cos⎜ t⎟+ b1/3sin⎜ t⎟+ 

⎝ 3 ⎠ ⎝ 3 ⎠ 

+ acos( ωdrivet) + bsin( ωdrivet) 

+ 

+ a3cos( 3ωdrivet) + b3sin( 3 ωdrivet) 

+ ... = 

p 

⎛ ⎛ωdrive ⎞ ⎛ωdrive⎞⎞ ≅ ∑⎜ 

a1/(2i+ 1) cos⎜ t⎟+ b1/(2i+ 1) sin⎜ 

t⎟⎟+ 

i= 

1 ⎝ ⎝2i+ 1 ⎠ ⎝2i+ 1 ⎠⎠ 

m 

∑( 

a(2 j + 1) ( ( j+ ) ωdrivet) + b(2 j + 1) ( ( j+ ) ωdrivet) 

) 

+ cos 2 1 sin 2 1 

j = 0 

‘p’ being the number of sub-harmonics and ‘m’ being the 

number of sub-harmonics considered. By increasing ‘p’ 

and/or ‘m’ the approximate system’s response tends to the 

exact one. Substituting into Duffing’s equation, a system 

of 2(p+m+1) non-linear algebric equations is obtained. 

Solving this system of non-linear equations through, for 

example, Newton-Raphson method, the unknown 

coefficients a i and b i are determined. Figure 4 shows the 

system’s regime response in the frequency domain 

obtained with 0 sub-harmonics (‘p=0’) and 5 superharmonics 

(‘m=5’). This response is determined by 

applying a driving force having a frequency that changes 

with discrete steps of 50Hz from 1kHz to 6kHz and 

recording the system’s response at equal frequency (a 1 and 

b 1 coefficients). 

Figure 4. Non linear frequency response function 

of the test structure obtained with the semianalytical 

method (0 sub-harmonics and 5 superharmonics). 


205 

2.2 Numerical method 

It’s important to consider that the integration step as well 

as the order of the integration method introduce 

perturbations in the function to be integrated. Increasing 

the order or decreasing the step reduces the perturbation. 

The first consequence is that, as already pointed out, the 

numerical integration methods cannot determine unstable 

branches of the system’s response. Furthermore, when 

stable and unstable branches of the system’s response get 

close to each other, the jump phenomenon may occur 

earlier or later as a function of the size of the integration 

step or of the order of the integration method. To improve 

accuracy, either higher order integration methods or very 

small integration step are required. Thus, high 

computational time is usually necessary to obtain the 

system’s regime response with good approximation. 

Several different integration methods were tested (variable 

step integration methods, variable order integration 

methods, non stiff and stiff integration methods) in order 

to access the best compromise between computational 

time and accuracy. 

The system’s regime response shown in Figure 5 are 

obtained by using the same integration method (RK 2/3) 

but different integration step (10µs and 5µs). It can be 

noticed that the identified jump-down frequency is higher 

with a smaller step size. However, as expected, the 

required computational time is about three times higher 

[m] 

x 10-6 

3.5 

3 

2.5 

2 

1.5 

1 

0.5 

RK23c step: 10e-6 

RK23c step: 5e-6 

0 

1000 1500 2000 2500 3000 3500 4000 4500 

[Hz] 

Figure 5. Nonlinear frequency response function 

of the test structure obtained with the numerical 

method (Runge-Kutta 2 nd – 3 rd order method). 

3. COMPARISON BETWEEN 

NUMERICAL AND EXPERIMENTAL 

RESULTS 

To validate the numerical model, the test structure was 

produced and its velocity along drive direction was 

measured through a laser Doppler Vibrometer. To obtain 

the displacement, the velocity of the proof mass is divided 

by the actuation frequency. 

Figure 6 and Figure 7 show the system’s regime response 

of the test structure in terms of magnitude of the frequency 

response function. Stars indicate the simulated system’s 

response achieved through the semi-analytical method 

while squares and circles show the measured displacement 

values at increasing and decreasing actuation frequency 

respectively. The difference between the two figures is the 

actuation force: Figure 6 refers to an actuation force of 

1.35µN while Figure 7 refers to a force of 2.7µN.

Both the figures show that the model is able to correctly 

predict the nonlinear systems response: the jump-up and 

jump-down frequencies are correctly estimated as well as 

the increase/decrease of the systems vibrations amplitude 

with actuation frequency. 

Figure 6. Regime response of the test structure: 

numerical results (star marker) and experimental 

results (square and circle marker). Force: 1.35µN. 

Figure 7. Regime response of the test structure: 

numerical results (star marker) and experimental 

results (square and circle marker). Force: 2.7µN. 


4. CONCLUSION 

The nonlinearity introduced by the supporting beams of a 

test structure has been investigated both numerically 

(using two different methodologies, a semi-analytical and 

a numerical approach) and experimentally. Even though a 

very simple lumped parameter model was used, a good 

agreement between experimental and numerical results 

was obtained. Thus, a powerful tool to predict even the 

nonlinear structural dynamic behaviour of translational 

gyroscopes has been setup that will allow to design better 

and more reliable devices. 

5. REFERENCES 

[1] Sitaraman I., Yong Z., Tamal M., Analytical Modelling 

of Cross-Axis Coupling in Micromechanical Springs, 

Carnegie Mellon University, Pittsburgh 

[2] Hosaka H., Itao K., Kuroda S., Damping 

Characteristics of Beam-Shaped Micro-Oscillators, 

Sensors and Actuators A, Vol. 49, 1995, pp.: 87-95 

[3] Miralles J.P., Jiménez Olivo P.J. Peirò D.G., A Fast 

Galerkin Method to Obtain the Periodic Solutions of a 

206 

Nonlinear Oscillator, Applied Mathematics and 

Computation, Vol. 86, 1997, pp.: 261-282


DESIGN AND SIMULATION OF RF MEMS 

SWITCHES FOR HIGH SWITCHING SPEED AND 

MODERATE VOLTAGE OPERATION 

Shimul Chandra Saha, Tajeshwar Singh, Trond Sæther 

Department of Electronics and Telecommunications, Norwegian University of Science and 

Technology (NTNU), 7491 Trondheim, Norway 

E-mail: shimul.saha@iet.ntnu.no 

ABSTRACT 

In this paper we present the design and simulations 

of an RF MEMS switch with regard to its switching 

speed and pull-down voltage. The switch is required 

to fulfill the requirements of high speed and a 

moderate pull down voltage for the switching of 

CMUT (Capacitive Micromachined Ultrasonic 

Transducer) elements used for ultrasound imaging 


The objective of this paper is to present the design of 

a high speed RF MEMS switch. MEMS are 

nowadays becoming increasingly popular in RF 

applications due to their attractive advantages such 

as high isolation and low insertion loss. Depending 

on the switch type (DC contact or capacitive), the 

MEMS switches can show very good RF 

performance from DC to several tens of GHz. 

However, there are two sides for this coin too; there 

are also some disadvantages of the RF MEMS 

switches, as compared to their solid-state 

counterparts, which include high pull-down voltage 

and slow switching speed. In this paper it is shown 

that by a careful design, a compact switch with a 

moderate applied voltage can be optimized for the 

switching speed (

process. Preliminary simulations for switching time 

& pull-down voltage were done with Mathematica ® . 

The pull-down voltage Vp and switching time ts of 

the bridge are given by [1][3]: 

8⋅k⋅g 

3 

Vp 

= 

(1) 

27 ⋅ε⋅W ⋅w 

Vp 

ts 

= 

ω ⋅v 


0 

S 

0 

27 

2 

Figure 1: The capacitive bridge 

(2) 

The actuation voltage Vs is selected slightly higher 

than the pull-down voltage calculated in (1), to 

increase the switching speed. The proposed switch is 

shown in Fig. 1. 

The dimensions of the beam 

are 250µ m× 40µ m× 1.5µ 

m, 

the bottom electrode 

is 200µ m× 40µ 

m, 

and initial gap g0 = 1µ 

m . From the 

simulations in Mathematica ® , a pull-down voltage of 

12V is obtained. Hence, with an actuation voltage of 

15V, which is of the order of the present state-ofthe-art 

(10-15V), pull down time of ts≈2.9µ sis 

obtained, which is around 10 times lower than 

reported results [2]. Final device simulations were 

done in Coventorware ® . The switching time and 

actuation voltage is shown on the Table 1. For 

comparison, the Gold beam is also simulated and as 

we can clearly see that the switching time is more 

than 2.5 orders better for Al than for Au for the same 

actuation voltage. The switching time (transient) and 

pull down voltage simulations are shown in Figure 2 

and Figure 3 respectively. 

Table 1: The switching time for the switch with Q≈1 

Material Pull down 

voltage 

(V) 

Actuation 

voltage(V) 

Switching 

time (µs) 

Aluminum 11 12 4.90 




Gold 12 15 7.55 

208 

Figure 2: Switching time simulations for Al beam with 

10µs pulse delay and Q≈1 

Figure 3: Pull down voltages for Al and Au beams. 

3.1 The damping and the Quality factor 

The damping (dominantly squeeze film damping) 

plays an important role in the switching time of 

MEMS switches (Equation 3). Within small gap 

heights, as in MEMS devices, the gaseous medium 

acts like a viscous liquid. During switch actuation 

when the beam moves down, the gaseous medium 

present within the gap must be pushed out and the 

molecules undergo several collisions between the 

beam and electrode [3]. The viscosity of the medium 

and in turn the quality factor can be controlled by 

reducing the pressure of the switch medium through 

packaging. The equations (4-7) for effective 

viscosity are shown below [3]. 

2 

d z dz 

m + b + kz = 

2 

dt dt 

λ 

a 

K n 

µ 

e 

0 λ 0 

a 

F total 

(3) 

p 

= (4) 

p 

λ 

g 

= (5) 

= 

µ 

1 . 159 

1 + 9 . 638 K n 

Where λa is the mean free path at pressure p a . g is 

the gap height and n K is the Knudsen number. Kn is 

a measure of viscosity of the gas under MEMS 

(6)

eam. µ e is the effective viscosity, a function of the 

Knudsen number. A high Knudsen number means 

low effective viscosity and the gas experiences few 

collisions and the flow is not viscous anymore. So 

by reducing the pressure of the medium (vacuum) 

the viscosity can be reduced and the switching speed 

increased. 

The effective damping coefficient can also be 

reduced by having perforations in the moving plate. 

The equations for damping without, and with 

perforations on the beam are given in Equation (7) 

and Equation (8) respectively [3, 4]. 

2 

3 µ A 

b = (7) 

2π 

g 

b h 

3 

0 

2 

2 

12 µ A p p ln( p ) 

= 

( − − − 

3 

N π g 2 8 4 


0 

3 

) 

8 

(8) 

Here, N is the number of holes; p is the fraction of 

open area in the plate. From Equation (8) it can be 

seen that by having perforations in the membrane, 

the damping coefficient can be reduced significantly. 

This option widely used because even by having the 

perforations, the upstate capacitance is not affected 

because the fringing fields ‘fill’ the empty space. 

The beam was simulated with different values of 

Quality Factor ‘Q’ (Equation 9) which depends on 

damping i.e. mainly gas damping and modal 

damping ‘D’ (D=a⋅M+b⋅K, where ‘M’ is the mass of 

the beam and ‘K’ is the beam spring constant, ‘a’ 

and ‘b’ depend on the damping medium and the 

beam structure). Q was varied from 0.05 to 10 and 

for different actuation voltage. 

Q 

= 

ω 0 

k 

b 

Thus, Q can be easily controlled by adjusting the 

damping coefficient which in turn decides the 

switching speed. As the gap height is low, the 

obtained Q is very low ≈0.05 under normal 

condition (atmospheric pressure, no perforations). 

Figure 9 shows the 3-D view of a beam with 80 

holes (4×4 µm 2 ) for which Q≈1 was easily obtained 

at normal pressure. The same value of Q can be 

obtained without perforations by reducing the 

pressure equal to ≈1/30 th of the atmospheric 

pressure. For further increasing the Q, both options 

can be combined (perforations and low pressure), a 

Q≈5 was thus obtained with perforations and at 1/7 th 

atmospheric pressure. Figures 4 and 5 show the 

switching time for actuation voltages 15V and 25V 

respectively, for different Q. It can thus be seen that 

(9) 

209 

at very low Q (high viscosity), the switching time is 

very large. Note from Figure 4 that very high Q also 

leads to a higher settling (release) time. 

Figure 4: The switching and release time for V a =15 V for 

different values of Q. 

Figure 5: The switching time for actuation voltage 25 V 

for different Q. 

At a higher Q the switching (pull down) time improves but 

increasing Q beyond 1 or 2 does not reduce the switching 

time much as compared to the reducing medium viscosity. 

So Q≈1-2 may be a fair choice for high speed switching. It 

can also be seen that at substantially higher Q≈10 and 

actuation voltage of 25V, the switching time is 1.25µs, 

which is very fast compared to the present technology [2, 

3]. 

3.2 The residual stress consideration 

One of the main concerns in the Fixed-Fixed beams 

is the residual stress. It can result in changes in the 

pull down voltage and in extreme cases render the 

structure useless. The residual stress usually arises 

form the process conditions and can be minimised 

by controlling the process parameters. It is possible 

to see the effect of residual stress on the switching 

time. When residual stress increases, it adds to the 

spring constant, thus the resonant frequency 

increases (ω0=k/m) which reduces the switching 

time. Figure 6 shows the comparative study of 

resonant frequency with residual stress for our beam. 

As seen, when the residual stress increases, the 

resonant frequency increases, which reduces the 

switching time. Thus care must be taken that the

esidual stress does not exceed the limits because if 

the pull down voltage exceeds the desired actuation 

voltage then the beam cannot be switched. 

Resonant frequency 

1,10E+06 

1,05E+06 

1,00E+06 

9,50E+05 

9,00E+05 

8,50E+05 

8,00E+05 

7,50E+05 

7,00E+05 

6,50E+05 

6,00E+05 

0,00E+ 5,00E+ 1,00E+ 

00 06 07 


1,50E+ 2,00E+ 2,50E+ 

07 07 07 

Residual stress 

3,00E+ 3,50E+ 

07 07 

Figure 6: The resonant frequency vs. residual stress. 

3.3 Different beam lengths 

The effect of varying the beam length is 

investigated. For longer beams, the spring constant k 

decreases thus the resonant frequency and the 

actuation voltage are both reduced. This has a mixed 

effect on the switching time. Figure 7 shows the 

switching times for different beam length. 

Figure 7: The switching time for actuation voltage 20 V 

for different length and Q≈1. 

We choose an actuation voltage of 20V as the pull 

down voltage for the 200µm switch is more >15V. 

From Figure 7 it can be seen that from 200µm to 

250µm there is a considerable improvement in the 

switching time but from 250µm to 280µm the 

switching time does not improve much. So it is not 

worth increasing the beam length further, to 

maintain the compactness. 

3.4 The S-parameters 

The simulation for the S- parameters is shown in 

Figure 8. The switch transmits the signal (ON state) 

while in upstate and the signal is capacitively 

grounded (OFF state) when the beam is in the 

downstate. It can be seen that we get an insertion 

loss less than 1dB in upstate position and have more 

than 15 dB isolation in the down state position for 

typical operating frequency range (>10 GHz) for a 

capacitive switch and more than 25 dB at higher 

210 

frequency. The isolation can be improved by using 

high dielectric constant materials as shown below. 

Figure 8: The isolation and the insertion loss in dB. 


We have shown the design of an RF MEMS switch 

with a high switching speed at moderate actuation 

voltage. Switching speed increases with actuation 

voltage but we have a limitation on the maximum 

actuation voltage. Damping affects the switching 

speed and can be controlled by perforations on the 

beam and by regulating the medium and pressure. 

Detailed effect of Q and damping was shown in 

section 3.1. The switches will be fabricated in the 

SINTEF, MiNaLab, Oslo. 

Figure 9: A 3-D view of the beam with perforation. 

5. ACKNOWLEDGEMENT 

Authors are grateful to Norwegian Research Council 

for sponsoring the work through SMiDA project (No 

159559/130). 

6. REFERENCES 

[1] J.B. Mauldavin, Nonlinear Electro-Mechanical 

Modeling of MEMS Switches, IEEE MTT-S Digest, 

2001. 

[2] D.Peroulis, Electromechanical Considerations in 

Developing Low-Voltage RF MEMS Switches. IEEE 

Transactions on MTT, Vol.51, No. 1 January 2003. 

[3] G.M. Rebeiz, RF MEMS Theory, Design and 

Technology, 1 st ed. New York: Wiley, 2003, Ch 3,5. 

[4] J. Bergqvist, A Silicon Condenser Microphone with a 

highly perforated backplate, In international 

conference on Solid-State Sensor and Actuators 

Digest, New York, 1991, pp 266-269.


MATERIAL CHARACTERISATION AND 

PROCESS DEVELOPMENT FOR MINIATURISED 

WIRELESS SENSOR NETWORK MODULE 

Bivragh Majeed, Jean-Baptiste Van Sinte Jans, Indrajit Paul, John Barton 

Sean C O’Mathuna, Kieran Delaney 1 

Tyndall National Institute, Lee Maltings, Prospect Row, Cork, Ireland 

Cork Institute of Technology, Cork, Ireland 

E-mail: bmajeed@tyndall.ie 

ABSTRACT 

The paper describes the work done in materials 

characterisation and process development of a proof-ofconcept 

test vehicle for miniaturised wireless sensor 

network nodes. The test vehicle consists of thin silicon on 

a flexible substrate packaged in a novel 3-D structure. 

Two flexible substrates (commercial and in-house 

polyimide substrates, in the thickness range 25 microns 

down to 3 microns (each with 4 microns of sputtered 

copper) were analysed. It was observed that as the 

thickness of the polyimide substrate decreased below 9 

microns, wrinkling became a major issue. The wrinkling 

was attributed to the copper sputtering. There was no 

adverse effect on test chip properties due to reduction in 

chip thickness while mechanically the chip was able to 

flex more with decreasing thickness and thus 

accommodate higher stresses. A finite element analysis 

model was constructed to observe the stress in silicon die 

under different loading conditions. The model matched 

well with the experimental values and showed that gold 

stud bumps cause stress in the chip. Test chips were 

packaged to develop a highly miniaturised 3D module by 

folding flexibly in an S shape structure. The 3D module 

consists of four test chips each having thickness of 50 

microns, resulting in a packaged test device 450 microns 

in thickness and with a footprint of 18x7mm 2 . This 

module is being currently investigated for its 

implementation in a wireless sensor network system. 


As the demand for low cost, highly miniaturised 

electronics increases, 3D packaging has emerged as a high 

potential solution. Many innovative and exciting 3D 

technologies have been recently reported in literature. 

These include techniques for wafer level stacking [1], 

stacked chip scale package (S-CSP) [2], the neo-stack [3], 

and multi-chip stacked package [4]. Each method provides 

clear benefits in increasing the on-board systems density 

in numerous applications. However, from the perspective 

of wireless sensor networks, perhaps the most interesting 

is one that can use either bare die or package, and employs 

the use of flexible substrates. The technique will involve 

bonding the die and making interconnection using flipchip 

and then folding the substrate to obtain a viable 3-D 

package. This technique will be used for the development 

211 

of novel 5mm cube micro-sensor modules for use as nodes 

in future wireless network applications. This node presents 

a fundamental research target in the development of 

exploitable distributed scalable wireless networks. This 

node is developed as a phased proof-of-concept test 

vehicle to ensure effective investigation of assembly 

issues and characterisation of the behaviour of different 

materials. 

2. DEVELOPMENT AND 

CHARACTERISATION 

2.1 Development of thin flexible substrate 

The need for the development of thin flexible substrates 

arises because, in folded stack assembly, as the thickness 

of chip decreases below 100 microns, substrate thickness 

has an adverse effect on silicon volume efficiency [5]. 

Thus, the demand for volume effective wireless, 

autonomous nodes dictates that in order to fully capitalise 

on the benefit of thin silicon, the substrate itself needs to 

be made as thin as possible. 

The method developed to form a thin flexible substrate 

started with spinning of precursor polyimide on a standard 

four-inch carrier wafer. Once applied to the wafer, the 

precursor is thermally converted into an intractable 

polyimide film. In this way, a number of different 

thickness polyimides, ranging from 16 microns down to 3 

microns, were prepared in order to characterise the effect 

of thickness on different properties of the film. This was 

followed by development of a test circuit, containing a 

pattern required to interconnect a four-layer test vehicle 

assembly. The test pattern was generated by depositing a 

conductive seed layer on polyimide, sputtering a copper 

layer 3 microns thick and then metal etching. 

The next step in the process is the technique to release the 

substrate from the carrier wafer. A number of different 

methods were investigated including mechanical, chemical 

and laser ablation. In mechanical release the polyimide 

was physically stripped from the wafer. This method was 

effective without the adhesion promoter on samples with 

no metal patterning; samples with the adhesion promoter 

could not be removed at all. Samples with metal patterns 

on them could not be successfully released either, as the 

polyimide was torn during the peeling process; this is 

believed to have happened because the copper metal acted

to create stress concentration points. In chemical release, 

some of the chemical affected the polyimide and thus 

these methods were discarded. In laser ablation technique 

a short wavelength high-energy UV laser beam is focused 

onto the backside of the wafer. The schematic of the 

process is shown in Figure 1. 

Figure 1: Schematic of flex release technique using 

UV laser 

The effectiveness of the process depends on three factors 

namely: laser wavelength, carrier wafer and the polymer. 

A 193nm ArF excimer laser was used in the experiments 

with quartz wafer as carrier wafer. Quartz is used, as it is 

transparent to the laser, while polyimide is highly 

absorbing at this wavelength. The mechanism of ablation 

depends on the laser ablation power density (P d)[6] In 

general with low P d as (in our case) photochemical 

ablation mechanism dominates and for high P d 

photothermal mechanism dominates. In photoablation 

process a sub-micron layer at the polyimide-quartz 

interface is etched away to release the flexible substrate 

from the carrier substrate [7]. The important characteristic 

of this process is no thermal damage to the material 

adjacent to the ablation. For the current experiment the 

laser release process gave the best possible results with the 

minimum damage to the polyimide flexible substrate. 

2.2 Characterisation of thin flexible 

substrate 

Five types of characterisation including electrical, 

chemical, mechanical, moisture absorption and stress were 

performed on released substrates of varying thickness. The 

results were analysed and compared with commercial 

polyimide. The results showed that electrical, chemical, 

mechanical and moisture absorption properties are 

acceptable for all of the spun off polyimide including the 

thinnest ones. One of the problems that was observed 

during the processing of thin flex was wrinkling of 

thinnest flex once it was released from the carrier wafer. 

Figure 2 shows an example of wrinkled and wrinkle free 

substrates. There are two main reasons for wrinkling; 

firstly it can be caused by internal stress generated in 

polyimide during the curing process and secondly residual 

stress in copper. The stresses in the cured polyimide 

before release were calculated and it was concluded that 

the difference in stress level between the thickest and the 

thinnest polyimide was not that huge to justify such a 

large observed difference in wrinkling patterns. Thus the 

residual stress in copper must drive the formation of 

wrinkling in areas surrounding the Cu due to non-uniform 

patterning of the circuit. The thicker substrates are too stiff 

to wrinkle but the driving force can overcome the small 


212 

resistance offered by stiffness in the thinner substrate. The 

critical thickness below which such an effect will be 

present was estimated to be 10 microns. To overcome this 

issue a polymer ring formation around the circuit was 

investigated and it resulted in wrinkle free substrates. 

Figure 2: Laser delaminated flexible test circuit 

substrate a) 3 microns b) 3 microns with polymer ring. 

2.3 Thin silicon 

As discussed in the introduction section of the paper, one 

of the major requirements, to meet the increasing demand 

for higher functionality in lower profile, is to thin the 

silicon die itself. This is achieved by thinning the nonfunctional 

part of silicon die. Thinning silicon not only 

reduces the package profile but also offers added 

advantages of better thermal resistance and reduced device 

stress thus increasing device reliability [8, 9]. Also, when 

silicon is thinned to below 50 microns it becomes flexible, 

combined with a flexible substrate it can be a major 

advantage in the areas of wearable computing, embedded 

artefacts and wireless sensor nodes. 

There are many approaches including mechanical grinding 

[10], chemical mechanical polishing [11] and dry and 

plasma etching [12], that can be used to achieve a silicon 

thickness to less than 100µm. Each of these methods carry 

with them their own advantages and disadvantages, the 

final choice of which method to use is very much 

dependant on the final device application and the silicon 

thickness required. As the thickness of the silicon is 

reduced below about 100µm a portion of the silicon can be 

damaged by some of the thinning methods. This damage 

can be separated into two parts; surface damage including 

micro-cracks and crystal damage consisting of 

dislocations. Both of these damage layers contribute to 

wafer warpage and a reduction of the fracture strength of 

the wafer [13]. The damage produced can propagate 

through the sample causing it to crack and it can also 

affect the electrical operation of the devices on the sample 

surface. For this reason it is imperative that this damage 

layer be reduced and full electrical, mechanical and visual 

characterisation should be done to eliminate any error in 

a 

b

performance of the chip due to thinning process before 

packaging. 

In the current work, test chips were thinned to final 

thicknesses of 250, 100 and 50 microns. The thinning 

process involved chemical mechanical polishing to 

remove the bulk of the material followed by dry plasma 

etching to remove the damage layer. Dicing was done with 

a specialised saw in order to minimise the damage to the 

chip. Effect of thinning electrical and mechanical 

properties were investigated and results are presented in 

the next section. 

2.3.1 Electrical characterisation 

The test chip contains a diffused heater resistor covering 

85% of the chip area and 3 temperature sensitive diodes. 

The diodes are positioned for optimal temperature sensing 

across the surface of each die. For the current work the 

central diode is used for measuring different parameters. 

The following parameters were investigated to observe the 

effect of chip thickness: 

1. Temperature Sensitive Parameter for the Diode 

2. IV Characteristics 

3. Heater Resistance 

Measurements were done with a Kiethly current source 

237 connected to a computer via a GPIB. A Labview 

program was used to record the results for the experiment. 

The results showed that there is no relationship between 

TSP and thickness of the chip and silicon thinning has no 

adverse effect on the electrical performance of the diode. 

IV characteristics of the diode were measured for different 

chip thickness at different temperature. The result showed 

the dependence of IV on temperature and there was no 

adverse effect of silicon thinning on this property. Heater 

resistance of the test chip was measured in order to 

determine the power dissipated by the chip for a given 

current. The results given indicated that the thinnest chip 

dissipated the maximum power for 100 mA current but 

there was not much of difference between different chips. 

In general thinning has no adverse effect on the electrical 

properties of the material. 

2.3.2 Mechanical characterisation 

Silicon thinning can impart damage to the silicon die and 

it is very important that the damage layer be removed. 

Scanning electron microscopy was performed on the 

backside of the chip and it was observed that there was no 

surface damage on the backside but there was some 

surface damage done due to dicing. For mechanical 

characterisation three point bend test was carried out on 

the different thickness chip. This test allowed for the 

determination of chip flextural stress. A finite element 

analysis model was then constructed. The basis of the 

model is the maximum principle stress theory [14]. 

Maximum principle stress theory can predict fracture of 

brittle materials subjected to stress states with at least one 

tensile principle stress under static loading conditions. 

Fracture will occur when the principle stress of greatest 

magnitude for that state of stress reaches a critical value. 

In the first model, different distributed load along the yaxis 

of the 525 microns die were applied for 525. The 


213 

model predicted that for 60N force the maximum principle 

stress was higher than the flexural strength and failure will 

occur. These results were within 5 percent of the 

experimental data. Similar results were obtained for 50 

microns die thus validating the model. Figure 3 shows the 

stress generated for a 3N point force applied at the centre 

of 250 microns thin die. The stress is below the flexural 

stress and die should not break at this applied load. Also 

the stress is concentrated near the applied load and most of 

the chip is stress free. 

Figure 3: FEA model predicting the stress generated 

in the 250 microns thin chip 

In the next step the model was used to predict the stress 

generated for four gold stud bumps placed at each corner 

of the chip. The results shown in figure 4 predict that the 

maximum stress generated is still below the flexural stress 

and similar in magnitude to the previous example. But 

overall the chip is under higher stress state compared to 

the previous example and there is compound effect of 

adding the stress from individual stress concentration 

point. 

Figure 4: Stress generated in 250 microns chip with 

four gold stud bumps. 

In the next phase of the work the effect of this stress on 

the properties of the flip chip test chip will be carried out. 

This will involve stressing the chip via a tensile tester and 

measuring the properties of the test chip. 

2.4 Development of 3-D module 

The 3-D module consisted of flexible substrates of varying 

thickness; standard and thinned test dies to 50 microns and 

was fabricated with flip chip technology using either 

anisotropic conductive paste or film. The first modules 

were developed as technological demonstrators using 

commercial flex of 25 microns thickness. Figure 5 shows

Chips 

thickness 

Microns 

the mechanical demonstrator built by using four-test chip 

of two different thicknesses and table I gives the 

dimension of two modules. It shows that for a 4-chip 

demonstrator with a total thickness of 480 microns, the 

percentage of flex increases from 4 to 20 percent. 

Figure 5 Technological Demonstrators 

Total 

thickness 

Microns 

Table I: Dimensions of the first demonstrator 

An environmental test regime including humidity and high 

temperature/ high humidity was carried initially on an 

unfolded test samples. The sample failed in humidity 

testing after 500 cycles while in thermal cycling samples 

didn’t fail after 200 cycles. The failure analysis proved 

that humidity was a major cause of failure and this 

corroborates with the results recently reported in literature 

[15]. In the next step these tests will be carried out on 

folded stack to thermo-mechanically characterise the 3-D 

modules. 


4 Test chip 3D Demonstrator 

% 

chip 

% 

chip 

Length 

(mm) 

3. CONCLUSION 

Width 

(mm) 

525 2357 90 4 18.74 7.19 

50 450 41 20 18.74 8.25 

This work focused upon the early development phase of 

the packaging of a wireless sensor node, and, in particular, 

specific material issues and assembly techniques. Folded 

flex provided a very good potential solution to the system 

packaging challenges inherent in implementing functional 

miniaturised sensor modules. The problem arising due to 

the miniaturising of different component especially 

flexible substrates and silicon die were investigated. 

Solutions and mechanism to overcome problem like 

wrinkling were presented. The effect of silicon thinning 

was investigated and it was concluded that electrical 

properties are not affected by thinning process. While thin 

silicon die are very flexible and thus are able to 

compensate stresses generated due to thermal mismatch. 

The FEA model showed the stresses generated in different 

loading situations. It showed that stress concentration 

points like gold stud bumps; result in higher stressed die 

as their stresses add up. The first 3-D technological 

module showed the advantages of reducing the thickness 

of the chip and the feasibility of the current work. In the 

214 

next phase the stresses in thin silicon under dynamic 

loading will be analysed and corroborated by FEA. 

Different reliability testing will be performed on the 3D 

module the feasibility study for the development of sensor 

node. 

4. REFERENCES 

[1] Y.P Wu, et al “Innovative Stacked Die Package – 

S2BGA,” Proc 52 nd ECTC May 28 - 31, San Diego, 

USA, s06p4, 2002 

[2] K Y Chen; et al, “Ultra Thin Electronic Package”, 

IEEE Transactions on Advance Packaging, Vol 23, N1, 

pp22-26, 2000 

[3] K D Gann, Neo Stacking Technology; Irvine Sensors 

Corporation, http://www.irvine-sensors.com/pdf/Neo- 

Stacking%20Technology%20HDI-3.pdf 

[4] M Sunohara, et al “Development of Wafer Thinning 

and Double Sided Bumping Technologies for Three 

Dimensional Stacked LSI, Proc 52 nd ECTC, May 28 - 

31, San Diego, California USA, s06p2, 2002 

[5] B. Majeed, et al The Development of a Test Vehicle 

for Applications in Ambient Electronic Systems Using 

Very Thin Flexible Substrate, 3rd EMPS, Prague Czech 

Republic, 16th to 18th June 2004 

[6] S. Kuper et al, “Threshold Behaviour in Polyimide 

Photoablation: Single-Shot Rate Measurements and 

Surface-Temperature modelling”, Journal of Applied 

Physics, A56, 43-50, 1993 

[7] J U. Meyer; “High Density Interconnects for Flexible 

Hybrid Assemblies for Active Biomedical Implants”; 

IEEE Transaction on Advance Packaging, Vol 24, Iss 

3, pp 366-374 2001 

[8] E Jung, et al, “Ultra Thin Chip for Miniaturised 

Products” Proc 52 nd ECTC May 28 - 31, San Diego, 

California USA, s26p5, 2002, 

[9]S. Sinniaguine; “3 D Stacked Wafer Level Packaging 

Advance Packaging, Vol 9, n 3, March 2000 

10 Pat Halahan, Backgrinding Technologies for Thin- 

Wafer Production, Chip Scale Review, Jan 2002. 

11 P. Perdu, A review of sample backside preparation 

techniques for VLSI, Microelectronics Reliability 40, 

2000 

[12] Sergey Savastiouk, Atmospheric Downstream 

Plasma – An approach to 300mm Wafer Thinning, Semi 

Global 300mm Report, July 1998 

[13] Kenji Takahashi, Current Status of Research and 

Development for Three-Dimensional Chip Stack 

Technology, Japanese Journal of Applied Physics, Vol. 

40 April 2001 

[14] N.Willems, “Strength of Materials” New York 

McGraw-Hill, 1981 

[15] J.de Vries, et al “100microns Pitch Flip Chip on Foil 

Assemblies with adhesive interconnects”, 

Microelectronics Reliability, 45 pp 527-534 2005


A NOVEL PLANAR MAGNETIC SENSOR BASED 

ON ORTHOGONAL FLUXGATE PRINCIPLE 

O. Zorlu, P. Kejik, F. Vincent, R. S. Popovic 

Ecole Polytechnique Fédérale de Lausanne (EPFL), Laboratoire de Microsystèmes 3 

Batiment BM, Station 17, CH-1015 Lausanne, Switzerland 

E-mail: ozge.zorlu@epfl.ch 

ABSTRACT 

In this paper, we present a new planar fluxgate 

magnetometer structure. The sensor has the 

orthogonal fluxgate configuration which makes the 

detection part independent of the excitation 

mechanism. The sensor consists of a ferromagnetic 

cylindrical core covering an excitation rod, and 

planar coils for signal detection. The fabricated 

sensor has a linear range of ±250 µT, a sensitivity 

of 4.3 mV/mT, and a perming below 400 nT for 

200 mA peak sinusoidal excitation current at 

100 kHz. The effect of demagnetization on the 

sensitivity, linear range, and perming for this 

structure is demonstrated by varying the length of 

the ferromagnetic core. 


Fluxgate type magnetic sensors are used in the 

magnitudal and directional measurement of DC or 

low-frequency AC magnetic fields. Their typical 

application areas are electronic compasses, current 

sensors, magnetic ink reading, detection of ferrous 

materials, and non-destructive testing [1, 2]. The 

main advantage of fluxgate sensors are their high 

sensitivity and linearity. On the other hand, low 

magnetic field operation range and high perming are 

still the problems of current fluxgate sensors [3]. 

2. SENSOR STRUCTURE 

In this paper, a new orthogonal fluxgate sensor 

structure is presented. Figure 1 shows the new 

sensor structure. An excitation rod is coated with 

the ferromagnetic material in a way that a circular 

excitation field loop is formed inside the 

ferromagnetic material. The permeability of the 

ferromagnetic layer is periodically modulated in the 

orthogonal direction with respect to the measured 

magnetic field by passing an AC current through the 

excitation rod. This makes the detection part 

independent of the excitation mechanism and the 

measuring range and the sensitivity can be adjusted 

by modifying only the core length. The 

215 

modification of the core length changes the 

demagnetization factor of the core. The apparent 

relative permeability µapp of the core deviates from 

its intrinsic value according to the demagnetization 

factor. This can be expressed as: 

µ 

app 

µ i = 

1+ N µ − 

( 1) 

i 

(1) 

where µi is the intrinsic relative permeability and N 

is the demagnetization factor. A change in the 

apparent permeability produces a change in the 

linear region of the B-H curve of the ferromagnetic 

layer. Since the saturation magnetic filed intensity 

Bsat remains constant, the slope of the linear region 

decreases and the magnetic field H required to 

saturate the material increases. This corresponds to 

a decrease in the sensitivity, but also to an increase 

in the linear operating range of the sensor. This 

phenomenon is effective in the longitudinal direction 

in the sensor, i.e. in the sensing direction of the 

magnetic field. 

Figure 1: The sensor structure. 

On the other hand, in the radial direction, i.e. in the 

excitation direction the geometry can be considered 

as an infinitely long core due to the closed magnetic 

loop, for which the demagnetization factor is zero. 

So, the slope of the B-H curve is a maximum, which 

allows easy and homogenous saturation along the 

whole core length. Two planar coils positioned 

under the tips of the ferromagnetic core pick up the 

measured signal. The use of planar pick-up coils 

provides easy integration into standard CMOS 

processes.


3. FABRICATION 

Figure 2 shows the fabricated sensor prototype. The 

fabrication starts with forming the pick-up coils on a 

Pyrex substrate by sputtering, photolithography, and 

patterning. Then, a gold wire which is passing over 

two pick-up coils is bonded. The gold wire serves 

as the excitation rod. After this step, the two edges 

of the gold wire are covered with an epoxy. The 

epoxy is used as a mask to determine the length and 

placement of the ferromagnetic layer which is 

electroplated over the gold wire. A standard FeNi 

electroplating bath is used for the electroplating of 

the magnetic layer [4]. A 10 µm thick and 4 mm 

long cylindrical FeNi layer is electroplated over the 

gold wire having 20 µm diameter. 

Figure 2: (a) The fabricated sensor. (b) Closer 

view to one edge. The planar coil, the 

electroplated and protected parts of the gold wire, 

and the epoxy is seen. 

4. SENSOR PERFORMANCE 

The tests of the sensor are done by passing a 

sinusoidal current through the excitation rod. The 

frequency of the current is kept constant at 100 kHz, 

whereas its amplitude is varied. The excitation 

current leads to an induced voltage across the pickup 

coils whose 2 nd harmonic is proportional to external 

magnetic field. The 2 nd harmonic of the induced 

voltage is measured with a lock-in amplifier and the 

linear operation range, sensitivity, and the perming 

of the sensor are analyzed. Figure 3 shows the test 

results of the sensor with different excitation 

currents within ±2 mT external magnetic filed range. 

The linear range is defined as the region in which 

the waveform fits to a linear function with 1% 

nonlinearity. It can be seen from Figure 3 that the 

linear measuring range is independent of the 

excitation current. 

216 

Figure 3: The sensor response within ±2 mT 

range for different levels of the sinusoidal 

excitation current at 100 kHz. The linear 

measuring range (shaded region) is independent of 

the excitation current. 

The slopes of the linear lines give the sensitivity of 

the sensor over this linear range. Figure 4 shows the 

variation of the sensitivity with the excitation 

current. The sensitivity of the sensor increases with 

the excitation current and tends to saturate after 

100 mA peak excitation current. 

Figure 4 shows also the variation of the perming 

value of the sensor with the excitation current. The 

perming of the sensor is the memory effect due to 

hard magnetic shocks. In order to measure the effect 

of perming, an external field of about 50 mT is 

applied to the sensor, and then the field is reduced to 

ambient. Then the stabilized value seen on the lockin 

amplifier is recorded. The same procedure is 

repeated with a field in the opposite direction. The 

difference between the two measured values gives 

the perming voltage. This voltage is then converted 

into the equivalent input magnetic field by dividing 

the value by the sensitivity at the very small region 

around the zero field value. It is important to note 

that the sensitivity of the sensor at this region is 

different from the sensitivity over the whole linear 

range. It is seen from Figure 4 that the perming 

decreases with the excitation current due to the 

better saturation of the core. 

The measurements show that, with 200 mA peak 

excitation current at the frequency of 100 kHz, the 

sensor shows a linear response in the range of 

±250 µT with a perming below 400 nT and a 

sensitivity of 4.3 mV/mT.

Figure 4: The variation of the sensitivity and the 

perming of the sensor with the magnitude of the 

excitation current. 

5. EFFECT OF DEMAGNETIZATION 

The effect of demagnetization on the sensitivity, 

linear range, and perming were also investigated. It 

is decided to perform the measurements on the same 

sample with only one pick-up coil by reducing the 

core length by ½ after performing all tests. In order 

to achieve different core lengths, half of the 

ferromagnetic core is protected by photoresist and 

the other half is etched by an H2SO4 based solution. 

The tests are then performed on the new structure 

having smaller core length. With this method, 

structures with 2 mm, 1 mm, and 0.5 mm lengths are 

obtained and tested. The advantage of this method 

over fabricating sensors with different lengths is that 

the sensor response is only dependent on the change 

in the length of the ferromagnetic core, but not on 

the variations on the electroplating thickness and the 

core distance from substrate. These two would not 

be well controlled if the tests would be performed 

with different samples. 

Figure 5 gives the responses of the sensors having 

different core lengths with a 200 mA peak excitation 

current. It should be noted that for better 

comparison, the voltage values for the 4mm-long 

sensor are divided by 2. It is seen that the linear 

range is increasing and the sensitivity of the sensor 

is decreasing with smaller core length. These are 

both due to the effect of demagnetization of the 

sensor. 

Figure 6 provides a more clear view of the change of 

the linear range with the sensor length. As well as 

the data for four different lengths, the variation of 

the inverse of the apparent permeability, µapp, which 

is calculated for a µi of 1000 with (Eq. 1), by 


217 

Figure 5: The response of the sensors with 

different core lengths at 200 mA peak current. 

The change in the linear range and the sensitivity 

with length is seen. 

assuming that the core has an ellipsoidal shape [5], 

is presented. The linear range follows the 1/µapp 

curve as expected. Furthermore, Figure 6 shows that 

the linear range is almost the same for the same 

sensor length for different excitation values, which 

is previously depicted in Figure 3. 

Figure 6: The change of the linear range with the 

sensor length for different excitation current 

values and the comparison with the 1/µ app values. 

Figure 7 shows the variation of the sensitivity with 

the core length, and its comparison with the 

variation of the apparent permeabilityp. The 

sensitivity tends to saturate for longer core lengths 

due to the fact that the demagnetization factor for 

longer cores is close to zero and does not have such 

a big effect when compared to the smaller lengths. 

This is also in good agreement with the very small 

change in the linear range between 2 mm and 4 mm 

cores which is seen in Figure 6.

Figure 7: The variation of the sensitivity with the 

core length, and its comparison with the variation 

of the apparent permeability, µ app. 

Figure 8 shows the variation of perming with the 

excitation current for a given core length. For 

higher excitation currents, the sensor is saturated 

more strongly in the orthogonal direction. This 

results in the better alignment of the magnetic 

domains inside the core which gives rise to a smaller 

perming value. On the other hand, the magnetic 

properties in the radial direction are independent of 

the core length, which gives the same remanent 

magnetization for different core lengths with the 

same excitation current. However, the sensitivity of 

the sensor is smaller, and this gives rise to a higher 

perming value. 

Figure 8: The variation of perming with the 

excitation current for a given core length. 


218 

6. CONCLUSION 

A new planar orthogonal fluxgate sensor structure is 

presented, and the feasibility of the idea is verified 

by the fabricated prototype. The sensor has a linear 

range of ±250 µT, a sensitivity of 4.3 mV/mT, a and 

perming below 400 nT for 200 mA peak sinusoidal 

excitation current at 100 kHz. The effect of 

demagnetization on the linear range, sensitivity, and 

perming of sensor is also demonstrated by varying 

the length of the ferromagnetic core. The sensitivity 

can be increased and the perming can be decreased 

by increasing the core length, but this decreases the 

linear range of the sensor. Higher excitation 

currents lead to a better core saturation, which 

decreases the perming. 

Further work is the scaling down of the sensor. The 

current required for an adequate core saturation can 

be drastically decreased by scaling down the sensor. 

Smaller sensor structures also enable the integration 

of the sensor into CMOS processes. 

7. REFERENCES 

[1] F. Kaluza, A. Gruger, H. Gruger, “New and 

future applications of fluxgate sensors,” Sensors 

& Actuators A 106, pp: 48-51, 2003. 

[2] P. Ripka, “Advances in fluxgate sensors,” 

Sensors & Actuators A 106, pp: 8-14, 2003. 

[3] Pavel Ripka, “Magnetic Sensors and 

Magnetometers”, Artech House Publishers, 

January, 2001. 

[4] J.M. Quemper, et. al, “Permalloy electroplating 

through photoresist molds,” Sensors & 

Actuators A74, pp. 1-4, 1999. 

[5] J. A. Osborn, “Demagnetizing Factors for the 

General Ellipsoid,” Physical Review, Vol. 67, 

No. 11-12, June 1-15, pp. 351-357, 1945.


A Monolithic CMOS 3-axis Accelerometer 

Combining Piezoresistive and Heat Transfer Effects 

A. CHAEHOI, L. LATORRE, F. MAILLY and P. NOUET 

Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, France. 

latorre@lirmm.fr 

Abstract 

This paper presents the analytical modelling and 

experimental data of a novel monolithic 3-axis 

CMOS accelerometer. The proposed sensor exhibit 

a sensitivity of 24mV/g and a resolution of 1g in out 

of plane detection and a sensitivity of 370mV/g and 

a resolution of 30mg in lateral measurement. 


Most accelerometers sense the acceleration along 

one single axis (vertical) or two axis (in-plane). This 

information is insufficient in applications where full 

data about the movement is required. Thus 3-axis 

accelerometers are essential for the movement 

sensing in numerous applications such as robotics or 

automotive applications. In this article we present a 

novel monolithic 3-axis accelerometer. Front Side 

Bulk Micromachining (FSBM) is the cheapest way 

to release mechanical structures on CMOS dies. 

This mature technique leads to low-cost and reliable 

devices. The proposed sensor is based on CMOS- 

FSBM beam and bridges. Out of plane (z axis) 

accelerations are measured by a "T-shaped” 

cantilever beam (seismic mass). The acceleration is 

measured by means of two embedded strain gauges 

that convert the vertical displacement of the 

mechanical structure into resistance variations. In 

plane (x and y axis) accelerations are sensed using 

convection heat transfer devices. A heating resistor 

flanked by two temperature detectors is suspended 

over a cavity. The symmetric temperature profile 

created by the heater become asymmetric with the 

acceleration, this temperature variation is converted 

into a resistance variation [1]. 

In this paper we present analytical modelling, finite 

element simulations (FEM) and experimental results 

of our unique monolithic CMOS-FSBM 3-axis 

accelerometer. 

219 

2. OUT-OF-PLANE SENSING: 

Piezoresistive accelerometer 

Using FSBM, the obtained suspended structures do 

not feature important seismic mass. Nevertheless, 

we have recently demonstrated that the very low 

noise level in polysilicon gauges allows a theoretical 

resolution of about 0.5g [2]. We have then designed 

a test chip to verify the performances of such CMOS 

cantilevers used as inertial sensors. The proposed 

sensor is based on a “T-shaped” cantilever beam. An 

image of the proposed sensor and its associated 

CMOS electronic circuitry is illustrated in Figure 1. 

The dimensions are of the two fabricated devices are 

presented in figure 2 and table 1. 

Figure 1. Picture of the T-Shaped based 


Figure 2. Design parameters of the proposed 

accelerometer.

Table 1. Dimensions of the “T-Shaped” structures 


Device A Device B 

Lb × Wb (µm) 480 × 80 480 × 40 

Lp × Wp (µm) 280 × 280 280 × 280 

In order to simulate the behavior of the sensor 

concurrently with the electronic circuitry, we have 

implemented an analog-HDL model description of 

the sensor. The output voltage is directly 

proportional to the beam bending z. The expression 

of the bending z, is determined as a function of the 

beam’s load (Figure 3), where the loads qb and qp 

represents the gravitational force resulting from the 

sensor mass itself, E the Young modulus and I the 

moment of inertia of the cross section. 

q b 

L b 

q p 

L p 

Fig. 3: Loading model for the proposed sensor. 

The bending z (at a distance x from the attached point 

of the beam) is obtained by integrating the bending 

torque T(x) along the cantilever length. In expression 

(1) E is the equivalent young modulus and I is the 

moment of inertia of the beam cross section I=Ib. The 

moment of inertia of the plate section is given by 

expression (2). 

2 

d z 

E . I = T ( x) 

2 

dx 

(1) 

WpWp Ip = Ib = I 

Wb Wb 

(2) 

The bending torque along the cantilever is given by: 

x ∈ [ 0, 

Lb] 

: T ( x) 

= qb 

2 ( Lb − x) 

⎛ Lp ⎞ 

+ q pLp⎜ 

Lb + − x⎟ 

2 ⎝ 2 ⎠ 

[ Lb , Lb + Lp] 

: T( 

x) 

x p 

( Lb + Lp − x) 

∈ = q 

(3) 

2 

The expression of the bending is obtained by 

solving equation (1). We choose the centre of the 

plate as the reference point where the equivalent 

force is applied ( x = Lb + Lp 2 ). It comes: (4) 

2 

220 

z 

plate 

= q 

p 

+ q 

2Lp 

45EI 

p 

( W W ) 

p 

4 

2 

Lp Lb 

2EI 

2 

b 

+ q 

+ q 

b 

b 

4 

Lb 

+ q 

8EI 

p 

3 

Lb Lp 

+ q 

12EI 

p 

Lp Lb 

3EI 

3 

3 

Lp Lb 

4EI 

From this equation we can deduce the expression of 

the equivalent stiffness and the equivalent mass of 

the model. The stiffness is defined by (5), where M 

is the equivalent lumped mass located at the centre 

of the plate. 

M. 

g 

K = 

z plate 

(5) 

By nature the mass is a distributed load while our 

second order mechanical system assumes a located 

single force. In order to determine the expression of 

the punctual equivalent mass, we assume that the 

output voltage of the sensor is the same whether we 

consider the distributed mass or the equivalent 

punctual mass. The output voltage is directly 

proportional to the bending torque, it comes: 

( 0) ( 0) 

T x = = T x = (6) 

Distributed Mass Lumped Mass 

Where the bending torque for a distributed mass is: 

2 2 

Lb Lp 

TDistributed Mass ( x = 0) 

= qb + qp qb + qp LbLp 

2 2 

And the bending torque for a lumped mass is: 

⎛ Lp ⎞ 

TLumped Masse ( x= 0) 

= ( MLumped ⋅g) ⋅ ⎜Lb+ ⎟ 

⎝ 2 ⎠ 

It comes: 

2 2 

⎛Wb. Lb + Wp. Lp + 2 Wp. Lb. Lp ⎞ 

M Lumped = ρS ⋅⎜ ⎟ 

⎝ 2Lb 

+ Lp ⎠ 

(7) 

(8) 

(9) 

The behavioral model of the cantilever has been 

validated by ANSYS® simulations (FEM). 

Simulations results are compared to experimental 

data from our prototypes in Table 2. A sensitivity of 

about 23.9mV/g and a resolution of 1g have been 

measured with the fabricated devices.

Table 2. Summary of results 


Model ANSYS® Prototype 

Stiffness (N.m) 0.44 n/a n/a 

Seismic Mass (kg) 1.08 10 -9 n/a n/a 

Sensibility (nm/g) 23.9 25.5 25.5 

Resonant Freq (kHz) 3.22 3.06 3.06 

3. IN PLANE SENSING: 

The thermally based accelerometer 

For the in plane acceleration, we use a device based 

on convection heat transfer from a suspended 

heating resistor. The proposed sensor is depicted in 

Figure 4. The cavity is an 800µm square, the 

dimension of the polysilicon heating resistor is 

40*1040µm and 30*420µm for the detectors. A 

heating resistor flanked by two temperature 

detectors is suspended over a cavity. With an 

acceleration in the chip plane and perpendicular to 

the resistors, the temperature profile created by the 

heater become asymmetric and this temperature 

variation is converted into a resistance variation by 

the detectors. Figure 5 shows the asymmetrical 

temperature distribution due to the acceleration. The 

detectors are arranged in a Wheatstone bridge and 

connected to an on-chip instrument amplifier 

(programmable gain: 20\100\1000). 

Figure 4. Picture of the thermally based 


We have simulated the behavior of the sensor with 

the FEM simulator ANSYS®. We consider a 2D 

model of the sensor using the FLOTRAN CFD 

element FLUID 141 where the velocities are 

221 

obtained from the conservation of momentum 

principle, the pressure from the conservation of 

mass principle and the temperature from the law of 

conservation of energy. The silicon cavity width and 

depth are 1000 and 300 µm respectively. The heater 

and detectors widths are 40 and 30 µm respectively 

and their thickness is 5 µm. The distance between 

the heater and the sensors is 200µm. With this 

model we find a difference of temperature on the 

detectors of 1.37°C for 1g acceleration and a heater 

temperature of 440°C. Figures 5 and 6 are examples 

of ANSYS simulations, Figure 5 illustrates the 

asymmetrical temperature distribution due to the 

acceleration and Figure 6 displays the fluid velocity 

vectors. 

Figure 5. Temperature distribution for an 

acceleration toward the left. 

Figure 6. Fluid velocity vectors. 

As it was described by [3], the silicon cavity limits 

the thermal boundary layer and the convection

phenomena in the bottom region of the fluid. 

Therefore the volume of the packaging influences 

the convection in the top region and has a large 

consequence on the sensor sensitivity. 

This kind of device exhibits a high sensitivity to the 

acceleration; its resolution is below 1g. To 

determine its sensitivity and resolution, we have 

used it as an inclinometer. Figure 7 displays 

experimental results for the test chip under 

inclination. This result is for a 35mW heating 

power. In this condition, the heater temperature 

reaches 438°C (deduced from the polysilicon 

temperature coefficient). The temperature difference 

across the detectors is calculated from the output 

voltage (taking into account the Wheatstone bridge 

and the amplifier gain). We obtain about 1.53°C/g. 

Finally an angular resolution of about 1.7° (around 

90°) is observed (SNR=1). 

Output voltage (V) 

2,2 

1,8 

1,6 

1,4 


2 

0 30 60 90 120 150 180 

Inclination (degree) 

Figure 7. Sensitivity of the device to inclination. 

Figure 8 presents the sensor output under a sinusoidal 

acceleration of 40 Hz: the sensitivity is 375mV/g and the 

resolution is 30 mg. The sensor has a very good linearity 

between 0 and 10g, the linearity error as a percentage of 

full scale is smaller than 

2%. 

Output voltage (mVpp) 

800 

600 

400 

200 

0 

0 2 4 6 8 10 

Acceleration (g) 

Figure 8. Sensitivity of the device to acceleration. 

222 

4. CONCLUSION 

The self-aligned wet-etching of CMOS bulk from 

the front side (FSBM) is the cheapest way to 

manufacture suspended structures and so monolithic 

microsystems. In this paper, we demonstrate that 

such low cost mechanical devices can be used as 

inertial sensors. We have proposed a complete 

model of the piezoresistive out-of-plane 

accelerometer. The model has been validated by 

FEM simulations. It is implemented into an analog- 

HDL description to simulate the behaviour of the 

sensor concurrently with the electronic circuitry in 

order to predict the whole system performances. We 

have proposed a 2D-model of the in-plane thermal 

accelerometer based on FEM simulations. Proposed 

FEM are used as a basis for further behavioural 

modelling and system integration 

The paper presents both simulation and 

characterization results. We have achieved a lowcost 

3-axis accelerometers with a sensitivity of 

23.9mV/g and a resolution of 1g in the out of plane 

direction and a sensitivity of 370mV/g with a 

resolution below 30mg in lateral direction. The 

performances of this prototype can be easily 

improved by on-chip amplification and filtering. 

5. REFERENCES 

[1] A.M. Leung, J. Jones, E. Czyzewska, J. Chen 

and B. Woods, “Micromachined accelerometer 

based on convection heat transfer”, IEEE 

MEMS’1998, Heidelberg, Germany, 25-29 Jan. 

1998, pp. 627–630. 

[2] A. Chaehoi, L Latorre, S. Baglio, P. Nouet; 

Piezoresistive CMOS Beams for inertial Sensin, 

IEEE Sensors’03, Toronto, Canada, October 

22-24,2003, pp. 142-143. 

[3] F. Mailly, A. Martinez, A. Giani, F. Pascal- 

Delannoy and A. Boyer, Effect of gas pressure 

on the sensitivity of a micromachined thermal 

accelerometer, Sens. Actuators A 109 (1-2), 

2003, pp. 88-94.

2005 PhD Research in Microelectronics and Electronics - Lirmm

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