SiGe CVD, fundamentals and device applications SiGe CVD ...

SiGe CVD,
fundamentals and device
applications
Dr Derek Houghton
Aixtron Inc
ICPS, Flagstaff July 2004

� OVERVIEW
1. Introduction
2. SiGe Market Survey
3. Fundamentals of SiGe CVD
4. CVD Equipment for SiGe
5. Device aplications and
commercialization
6. SiGe materials engineering, metrology
7. Summary and Discussion

SiGe’s Market Opportunity...
Si CMOS/BJTs SiGe HBTs/CMOS? III-V FETs/HBTs
GSM
DCS
DECT
Automotive
Road
Pricing
Navigation/Areospace
GPS x-band
Radar
Communications
ISM
FRA WLAN
OC-48
G-Ethernet
DTH
DBS
OC-192
Collision
Avoidance
WLAN
FRA
LMDS
0.1 0.2 0.5 1 2 5 10 20 50 100
Frequency (GHz)

SiGe HBT device structure and process description
Only difference: Base
SiGe replaces Silicon
Key figures of SiGe HBT process
• SiGe BiCMOS uses SiGe HBT + Si
CMOS
• SiGe HBT shows same process as
Si BT with exception of 30-80 nm
thin SiGe base layer (Ge

SiGe‘s main market is telecommunication (wireless and datacom)
SiGe IC Market [Mio. US$]
1800
1600
1400
1200
1000
800
600
400
200
0
SiGe IC forecast by market, 2000 to 2005, in mil. US$
Industrial
Computer
Consumer
Communications
CAGR=+125%
2000 2001 2002 2003 2004
CAGR: Compound Average Growth Rate
YEAR
2005
Comments
• SiGe viable alternative to GaAs
• Main markets being targeted:
• Cellular / Cordless / WLAN
• FO-Datacom
(MUX/DEMUX)
• PC interface cards / LAN
• Future trends:
• integrated low power RFfront
end of most handsets
• First choice for up/down
conversion in tuners/
transceivers
• will dominate 40 Gbps
Source: Strategies Unlimited, 1999

Strained Si: prototypes from Intel, IBM & UMC demonstrated
Almost all large Si-CMOS manufacturers are presenting cross sectional pictures of
CMOS transistors (with gate lengths between 65 and 90 nm) which use Strained-Si
technology. Intel and IBM use their own technology, whereas UMC is Amberwave’s
licensee

Strained-Si HeteroWafer ® technology: process and actual status
Actual status Strained-Si process
• Strained Si technology enables improvement
in CMOS performance and functionality via
replacement of the bulk, cubic-crystal Si
substrate with a Si substrate that contains a
tetragonally distorted, biaxially strained Si
thin film at the surface
• Different types of processes developed and
patented by the main players: Amberwave
(IQE) - AIXTRON, IBM,Toshiba & Intel
• First demos of perfect working 52 Mbit
SRAMs with 90 nm CMOS devices on 300
mm wafers available from Intel. Ramp-up of
Pentium 4 production with Str.-Si planned for
2H/2003 !
• Process and substrate costs still not 100%
fixed. Price expectations for substrate from
IC manufacturers still unknown

Strained Si process of Amberwave: One of the Strained Si pioneers
•Typically, 2 to 4 µm thick graded SiGe buffer layer, followed
by thin (

Strained Silicon CMOS technology
*SiGe deposited selectively,
Intel Pentium IV in production

Digital CMOS Electronic Market [Mio. US$]
Strained Si based CMOS Market [Mio. US$]
100000
80000
60000
40000
20000
0
100000
80000
60000
40000
20000
Strained silicon mainly addresses high-end digital CMOS markets
Digital electronic market forecast and expected strained Si penetration, 2003 to 2007, in mil. US$
CAGR*= 12.5%
CAGR*= 12.5%
2003 2004 2005 2006 2007
Source: VLSI Research, 2002
YEAR
CAGR*= >200%
CAGR*= >200%
0
2003 2004 2005 2006 2007
YEAR
Source: AIXTRON estimates
Si FPGAs
Si Digital Signal Processors (DSPs)
Si Micro-controllers (MCUs)
Si Microprocessors (MPUs)
Assumptions
• Main application will be high-end
Microprocessors like IBM‘s
Power-PC, SUN‘s Sparc, AMD‘s
Athlon, Intel Pentium / Itanium.
• Main markets being targeted:
PCs, workstations, game
consoles, other internet
appliances
• Future trends: Strained Si
penetrates 3G/WLAN wireless
applications (DSPs/MCUs)
CAGR: Compound Average Growth Rate

Effect of air exposure prior to HF passivation
Carbon and Oxygen concentrations (cm -3 )
10 21
10 20
10 19
10 18
10 17
RCA + 4 hours in air + HF dip
RCA + HF dip
Oxygen
Carbon
0 500 1000 1500 2000 2500 3000 3500
Depth (Å)

Partial pressure for oxygen incorporation from H 2 O and O 2

AIXTRON‘s flexible epi systems for Strained Si / SiGe
Tricent ® vs. Multiwafer Reactor ®
Tricent SiGe Cluster Tool: 150, 200 or 300
mm
AIX 2600G3: up to 7x150 or 3x200 mm

Quartz tube
P~ 10 -3 mbar
T g

Hot wall UHVCVD Batch tool

Growth Rate
Uniform Gas Distribution by
AIXTRON´s Closed Coupled Showerhead
Horizontal Quarz Tube Reactor
Distance to gas inlet
Closed Coupled Showerhead Reactor
Growth Rate
Distance to gas inlet

Wafer
SiGe Tricent ®
Dual-Chamber Showerhead (pat. pend.)
Water-Cooled Reactor Lid
Coated Graphite
Susceptor
Showerhead Detail
N 2 /H 2
Gas Mix
Showerhead
Process
Chamber
T Lid
T SH
T Substr
Temperature Control Concept

SiGe Tricent ®
�� Showerhead
�� Temperature control
Unique CVD chamber features
developed beyond industry standards

Tricent ®
Clean
Room Wall
Cassette
Station
Customer Process Support
Process platform for
HBTs, HFETs and BiCMOS
- pure Silicon Growth
- differential SiGe:C growth
- selective SiGe:C growth
- SiGe on SOI
Temp Process Gas Sources
550-680°C SiGe:C SiH4 + GeH4 + SiCH6
650-750°C SiGe SiH4 + GeH4
730-800°C sel. SiGe SiH2Cl2 + HCl + GeH4
800-900°C SEG SiH2Cl2 + HCl

SiGe HBT in a BiCMOS flow
Metallisation
Spacers
EpitaxialLayer N
MOS
Polysilicon Emitter
LOCOS
n +
HBT
N
+
Base SiGe

XTEM of Si deposition on Si/oxide

HBT base structure SIMS profiling
Boron conc. (cm -3 )
10 19
10 18
10 17
10 16
10 15
SIMS analysis (cameca)
Ge
CVD-197
0 500 1000
0
1500
Depth (Å)
15
10
5
Germanium conc. (%)

IC, IB (A)
10 -3
10 -5
10 -7
10 -9
10 -11
10 -13
Gummel Plot, npn HBT
Ic
Ib
A = 0.6 x 1.2 micron
E 2
V = 0
CB
V BE (V)
NPN11A, CVD-140
Triangular SiGe base profile
0 0.2 0.4 0.6 0.8 1 1.2 1.4

CMOS transistor

Selective SiGe
Epitaxy

DC Houghton J.Appl.Phys.1991

Strained Silicon on
graded SiGe buffer
Amberwave
Ge%
Strained Silicon on
SOI wafer by layer
transfer
SOITEC
Strained Si Strained Si
SiGe stack
SiGe grade
Si substrate
Si substrate

DCD x ray diffraction

Concentration
SIMS profileStrained Si – Graded SiGe Buffer
1E+23
1E+22
1E+21
1E+20
1E+19
1E+18
1E+17
Cs Cascade Scientific
12/04/2003
SIMS
70Ge
Sample A3
Low O and C background
No Interface peak
12C
interface
16O
29Si+30Si->
1E+16
0 2 4 6
Depth (microns)
8 10
1E+05
1E+04
1E+03
1E+02
1E+01
1E+00
Counts Per Second

Strained Si layers
SiGe 40%
SiGe graded 5...40%

Pure Ge on Silicon substrates
Low defect density Ge without SiGe graded buffer
Ge
Si wafer
Cross sectional TEM
Plan view TEM (looking down
through Ge cap)

Growth Rate vs Germanium concentration
Growth Rate (nm/minute)
12
10
8
6
4
2
0
570°C
525°C
495°C
Rate @ 495°
Rate @ 525°
Rate @ 570°
0 5 10 15 20 25 30 35 40
Ge concentration (%)

Growth rate (nm/minute)
Growth Rates vs Temperature
10
1
600°C
Ea = 1.6 ± 0.1 eV
Si 0.7 Ge 0.3
Reactant Limited
495°C
0.1
1.1 1.15 1.2 1.25 1.3 1.35
Si
1000/T (k -1 )

SiGe
silicon
SiGe/Si Multilayer structure
Abrupt Si/SiGe interfaces
and precise control
of Ge % for “PIN
Photodetector”

Concentration (Ge %)
20
18
16
14
12
10
8
6
4
2
0
SIMS
SiGe Multi Quantum Wells (MQW)
Cs Cascade Scientific
12/04/2003
SIMS
Sample A
0 1000 2000 3000 4000 5000
70Ge
Depth (angstroms)
a5321d_lin.SWF
30Si->
1E+07
1E+06
1E+05
1E+04
1E+03
1E+02
1E+01
1E+00
Counts Per Second

Intensity (cps)
4
A532-1
10
103
102
101
100
10-1
XRD
SiGe Multi Quantum Wells (MQW)
Reference (Active) Comparison
• Double crystal X-ray data
• Period of super-lattice = 39.5nm
• Mean Ge fraction of structure
(Si spacers + SiGe Wells) = 0.6%
-3000 -2000 -1000 0
th\2th (sec)
1000 2000 3000
Measured by

Raman Scattering

Raman Scattering

Fourier transform low temperature photoluminescence apparatus.
Fourier
Spectrometer
Moving
Mirror
Beamsplitter
Excitation Source
Laser
Cryostat SAMPLE
Germanium
Detector

PL spectra from SiGe HBT transistors
Photoluminescence Intensity
Patterned
Wafer
Si Surround
SiGe
Etched Off
SiGe
Layer
Vertical
Profile SiGe
50 nm
900 1000 1100
Energy - meV

SiGe PL Peak Height
0.1
0.01
1E-3
PL Intensity
1
PL of SiGe HBT
10 15
100
10
SiGe PL Threshold &
Saturation Effects
Sample A
As Grown
TO
10 16
PL Spectra
Sample B Annealed
3.5x10 16 s -1 cm -2
1
980 1000 1020 1040 1060
Energy / meV
Si
TA
1.4x10 16 s -1 cm -2
Sample B
Annealed
10 17
Incident Photon Flux / s -1 cm -2
NP
Carrier
Wavefunction
Si
15%
Sample B
As Grown
Ge Profile
10 18
20 nm
SiGe - Graded Composition
Si

Sample point "NP" energy
(meV)
Photoluminescence Mapping of
Composition and Bandgap on a 6" wafer
Energy
bandgap (meV)
Composition
(% of Ge)
a 1080 1092.2 8.97
b 1082.5 1094.7 8.69
c 1085.2 1097.4 8.39
d 1083.3 1095.5 8.60
e 1082.5 1094.7 8.69
f 1084.8 1097.0 8.44
g 1083.7 1095.9 8.56
h 1079 1091.2 9.08
d c
h
g
f
e
b
a

Auger Electron Spectroscopy
Of Graded germanium concentration profiles
Germanium atomic concentration (%)
20
15
10
5
0
Actual profile
Ideal profile
HBT profile FET profile
0 2000 4000 6000 8000 1 10 4
Sputtering time (s)

Trends in “novel” epitaxy in Si based materials
For graded SiGe buffers
Low CoO, defect density reduction, flatness
Thin SiGe epitaxy with defect nucleation layer
SOI substrates
Lower thermal budget in CMOS
low leak rate tools
new precursors with high GR at