DesignCon 2002

of high-speed design characteristics yielded four primary areas that had to be taken into
consideration: printed circuit board losses, impedance discontinuities, crosstalk, and skew
due to board routing and connectors. In addition, to validate some of the simulation
results, a number of tests were performed using a standard VHDM backplane evaluation
board to guide decisions for designing and building a backplane capable of supporting a
bit rate of 10 Gb/s. Simulations that used a behavioral channel model were employed to
process all design permutations. The goal was to determine the worst-case scenario and
then optimize the solution space. The mechanical and electrical constraints for the highspeed
serial link, shown in the topology of Figure 1, represent the typical blade design, in
which the signal traverses three boards and two connectors with data rates that vary from
1 to 10 Gb/s.
Accurate modeling of high speed serial channels from the driver to the receiver requires
numerous building blocks that accurately interoperate. Tackling these design issues
would be an impossible task without the use of proper tools such as electromagnetic
models within a circuit simulation environment that can demonstrate silicon performance
including equalization. No longer are purely analytic methods an acceptable solution to
today’s high speed serial design challenges. In addition to pre-layout system simulation
analysis, another key to ensuring proper system operation is post-layout extraction that
quickly analyzes the actual architecture that will be sent off to the fabrication house.
This work will concentrate on a single IEEE 802.3ap KR BladeServer channel that will
include analyses from the driver to the receiver. This BladeServer channel spans over 26
inches of FR-4 and includes three multi-layered circuit boards consisting of a switch card,
backplane, blade card, two high speed connectors, and standard through hole vias (Figure
1). The pre-layout consisted of full wave three-dimensional electromagnetic models
created from Ansoft’s HFSS for the differential vias used within the BladeServer
channel, SMP connectors used for channel measurements, and the VHDM high speed
connectors. The differential traces for the switch, mid-plane, and blade were modeled
using the two-dimensional electrostatic solver within Ansoft’s Q3D. The striplines
were modeled as differential cross-sections that included frequency dependent dielectric
responses of the FR-4 within the PWBs. Ansoft’s Q2D produces a Spice syntax netlist
containing a tabular RLGC w-element file that is used within Ansoft’s Designer with
Nexxim.
This methodology was used to perform pre-layout simulations by defining the channel
within the Designer simulation environment and then performing time-domain and
statistical domain simulations using the Nexxim simulation engine. Initially, a
behaviorally based circuit model with de-emphasis was used to represent the driver side
of the channel. This buffer model consisted of five taps of continuous time linear
equalization.