DesignCon 2002
DesignCon 2002
DesignCon 2002
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of high-speed design characteristics yielded four primary areas that had to be taken into<br />
consideration: printed circuit board losses, impedance discontinuities, crosstalk, and skew<br />
due to board routing and connectors. In addition, to validate some of the simulation<br />
results, a number of tests were performed using a standard VHDM backplane evaluation<br />
board to guide decisions for designing and building a backplane capable of supporting a<br />
bit rate of 10 Gb/s. Simulations that used a behavioral channel model were employed to<br />
process all design permutations. The goal was to determine the worst-case scenario and<br />
then optimize the solution space. The mechanical and electrical constraints for the highspeed<br />
serial link, shown in the topology of Figure 1, represent the typical blade design, in<br />
which the signal traverses three boards and two connectors with data rates that vary from<br />
1 to 10 Gb/s.<br />
Accurate modeling of high speed serial channels from the driver to the receiver requires<br />
numerous building blocks that accurately interoperate. Tackling these design issues<br />
would be an impossible task without the use of proper tools such as electromagnetic<br />
models within a circuit simulation environment that can demonstrate silicon performance<br />
including equalization. No longer are purely analytic methods an acceptable solution to<br />
today’s high speed serial design challenges. In addition to pre-layout system simulation<br />
analysis, another key to ensuring proper system operation is post-layout extraction that<br />
quickly analyzes the actual architecture that will be sent off to the fabrication house.<br />
This work will concentrate on a single IEEE 802.3ap KR BladeServer channel that will<br />
include analyses from the driver to the receiver. This BladeServer channel spans over 26<br />
inches of FR-4 and includes three multi-layered circuit boards consisting of a switch card,<br />
backplane, blade card, two high speed connectors, and standard through hole vias (Figure<br />
1). The pre-layout consisted of full wave three-dimensional electromagnetic models<br />
created from Ansoft’s HFSS for the differential vias used within the BladeServer<br />
channel, SMP connectors used for channel measurements, and the VHDM high speed<br />
connectors. The differential traces for the switch, mid-plane, and blade were modeled<br />
using the two-dimensional electrostatic solver within Ansoft’s Q3D. The striplines<br />
were modeled as differential cross-sections that included frequency dependent dielectric<br />
responses of the FR-4 within the PWBs. Ansoft’s Q2D produces a Spice syntax netlist<br />
containing a tabular RLGC w-element file that is used within Ansoft’s Designer with<br />
Nexxim.<br />
This methodology was used to perform pre-layout simulations by defining the channel<br />
within the Designer simulation environment and then performing time-domain and<br />
statistical domain simulations using the Nexxim simulation engine. Initially, a<br />
behaviorally based circuit model with de-emphasis was used to represent the driver side<br />
of the channel. This buffer model consisted of five taps of continuous time linear<br />
equalization.