DesignCon 2002

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Introduction High-speed channel designs, such as 10 Gb/s Ethernet, PCIe 3.0, 8.5 Gb/s Fiber channel, demand accurate channel simulation and modeling to ensure first-pass system success in a BladeServer environment. The backplane product in a BladeServer is defined here as the flexible interface to attach shared devices such as processor blades, 10 Gb/s Ethernet switches, management modules, etc… Modeling was used, primarily, to guide decisions on the design trade-offs which promote system-level compatibility between shared devices. The simulation strategy was developed to balance implied business goals (cost, time-to-market) against the requirements of product performance. This paper discusses the implementation of simulation to cope with AC loss (the predominant concern), with inter-symbol interference (ISI) effects due to impedance geometry changes such as via stubs, and signal jitter. At high data rates, layout discontinuities coupled with long delays bring on severe ISI that may be mitigated by equalization or topology manipulation. Statistical methods have been used to rapidly generate two well known channel performance metrics: eye diagrams and bit error rate (BER) curves. Simulation time becomes a critical factor because the real-time simulation of standard pseudo-random bit sequence (PRBS) patterns such as PRBS23 or PRBS31 is impractical for a designer who is trying to detect BER rates lower than 10 -12 using transient simulators. These statistical methods provide a useful approximation of channel performance with the benefit of very fast simulation times. The BladeServer 10 Gb/s channel design case study incorporates statistical and transient analyses within a schematic entry simulator. To achieve the greatest channel accuracy, three-dimensional models of vias and connectors were incorporated along with onedimensional distributed frequency dependent dielectric transmission line models. The statistical channel analyses include a combination of Touchstone S-parameter files, buffers with de-emphasis, w-elements, passive components, feed forward and decision feedback equalization. Typical high speed channels include differential traces meandering along some given length, usually many wavelengths relative to the data rate. The aforementioned statistical methods offer a quick means of analyzing these high speed channels for impairments caused by discontinuities. This paper introduces two such methods, one that specifically analyzes the channel, independent of bit pattern, while the other utilizes a known bit pattern such as a standard PRBS pattern in order to produce an eye diagram and bit error rate (BER) plots. The latter analysis produces a BER curve that is as accurate as the number of bits simulated; however, the statistical nature of the modeling allows for a quick result unattainable by traditional transient simulation engines. Both analyses will be explained in detail including the inherent assumptions and modeling details that provide a fast and accurate simulation result. Finally, equalization will play a major role in the design of next generation high speed channels beyond 5 Gb/s. In this paper different equalization schemes will be discussed including feed-forward equalizers (FFE), continuous time linear equalizers (CTLE), and decision feedback equalizers (DFE). A multi-tapped FFE combined with a multi-tap DFE
eceiver has been implemented to show corresponding statistical eye information at the pad of the receiver. Putting it all together; equalization, accurate physical models, statistical models and methods provide an integrated suite of tools that were utilized in BladeServer 10Gb/s high-speed channel designs. The BladeServer Channel The IBM eServer BladeCenter backplane provides the electrical interconnections among all of the chassis components, including the processor blades, switch modules, management modules, media devices, power modules, and blower modules. It also serves as the redundant power distribution medium from the power supplies to all of these components. The backplane provides up to 14 blade slots, four switch slots, one media bay, two management modules, and four power modules, all of which support hot-swap capability. Interconnections are redundant in order to provide high availability and maximize uptime for the customer. To provide a multiblade system that supports multiple protocols, such as Gigabit Ethernet, Fibre Channel, and InfiniBand, over a common copper-trace medium, a serialized/de-serialized (SerDes) interface was used for this highspeed internal input/output (I/O) fabric. High-speed designs often require complex, highspeed printed circuit boards that can easily drive costs higher, usually through the use of overly stringent design methodologies or expensive printed circuit board materials that are not required for the system operating parameters. To achieve a cost-competitive backplane for the BladeCenter system, an extensive pre-design modeling and simulation analysis was performed to determine the appropriate material and practices to be used in the design of the backplane. This paper discusses the implementation of solutions to overcome some of the challenges of 10 Gb/s data transmission over multiple printed circuit boards and connectors in order to reduce board costs. A benefit of a multi-server chassis is that it provides the capability to share devices and hence lower the per-server cost. In the BladeCenter system, all 14 blades share a keyboard and mouse via the management module, and a Universal Serial Bus (USB) CD-ROM/DVD (compact disc, read-only memory/digital video disc) drive and USB floppy disk drive (FDD) located in the front of the chassis. This paper describes the initial pre-design analysis that was performed to establish the backplane design requirements for both material and design practices for the high-speed SerDes wiring. This section describes the electrical design challenges that were associated with the highspeed SerDes interfaces and were encountered during the definition, design, and verification of the BladeCenter system. SerDes is a full-duplex, high-speed serial bus comprising of a single transmit and a single receive differential pair of signals. The BladeCenter design uses SerDes channels for interconnecting processor blades and highspeed switches that support Gigabit Ethernet, Fibre Channel, InfiniBand, and Myrinet I/O fabrics. A comprehensive electrical design methodology, including accurate and detailed modeling and simulation of the complete design space, was required in order to achieve the speeds required by these standard interfaces while at the same time using low-cost printed circuit board material. Some of the obstacles and solutions to supporting 10 Gb/s data transmission over a copper backplane, multiple boards, and multiple connector technologies are highlighted. The pre-design analysis was performed to predict interconnect performance for relatively long trace lengths (across three boards and two
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