DesignCon 2002

Introduction
High-speed channel designs, such as 10 Gb/s Ethernet, PCIe 3.0, 8.5 Gb/s Fiber channel,
demand accurate channel simulation and modeling to ensure first-pass system success in
a BladeServer environment. The backplane product in a BladeServer is defined here as
the flexible interface to attach shared devices such as processor blades, 10 Gb/s Ethernet
switches, management modules, etc… Modeling was used, primarily, to guide decisions
on the design trade-offs which promote system-level compatibility between shared
devices. The simulation strategy was developed to balance implied business goals (cost,
time-to-market) against the requirements of product performance. This paper discusses
the implementation of simulation to cope with AC loss (the predominant concern), with
inter-symbol interference (ISI) effects due to impedance geometry changes such as via
stubs, and signal jitter. At high data rates, layout discontinuities coupled with long delays
bring on severe ISI that may be mitigated by equalization or topology manipulation.
Statistical methods have been used to rapidly generate two well known channel
performance metrics: eye diagrams and bit error rate (BER) curves. Simulation time
becomes a critical factor because the real-time simulation of standard pseudo-random bit
sequence (PRBS) patterns such as PRBS23 or PRBS31 is impractical for a designer who
is trying to detect BER rates lower than 10 -12 using transient simulators. These statistical
methods provide a useful approximation of channel performance with the benefit of very
fast simulation times.
The BladeServer 10 Gb/s channel design case study incorporates statistical and transient
analyses within a schematic entry simulator. To achieve the greatest channel accuracy,
three-dimensional models of vias and connectors were incorporated along with onedimensional
distributed frequency dependent dielectric transmission line models. The
statistical channel analyses include a combination of Touchstone S-parameter files,
buffers with de-emphasis, w-elements, passive components, feed forward and decision
feedback equalization.
Typical high speed channels include differential traces meandering along some given
length, usually many wavelengths relative to the data rate. The aforementioned statistical
methods offer a quick means of analyzing these high speed channels for impairments
caused by discontinuities. This paper introduces two such methods, one that specifically
analyzes the channel, independent of bit pattern, while the other utilizes a known bit
pattern such as a standard PRBS pattern in order to produce an eye diagram and bit error
rate (BER) plots. The latter analysis produces a BER curve that is as accurate as the
number of bits simulated; however, the statistical nature of the modeling allows for a
quick result unattainable by traditional transient simulation engines. Both analyses will be
explained in detail including the inherent assumptions and modeling details that provide a
fast and accurate simulation result.
Finally, equalization will play a major role in the design of next generation high speed
channels beyond 5 Gb/s. In this paper different equalization schemes will be discussed
including feed-forward equalizers (FFE), continuous time linear equalizers (CTLE), and
decision feedback equalizers (DFE). A multi-tapped FFE combined with a multi-tap DFE