DesignCon 2002

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Figure 15: VerifEye contour BER diagram with 3 ps of RJ introduced into the system with 5 taps of FFE at the receiver. VerifEye BER results for the final pre-layout channel (Figure 13) that included the SMP connector and an additional four 50 mil via stubs are shown in Figure 16. This shows that additional equalization was required to achieve an acceptable system BER; this required the inclusion of DFE into the receiver along with FFE. The final design showed 8 taps of FFE and 3 taps of DFE at the receiver were required to equalize the system channel. A B Figure 16: A- VerifEye contour BER plot for Figure 13 yielding BERs up to 1x10 bathtub -12 . B- VerifEye BER curve shown up to a BER of 1x10 -12 . Both A and B plots are using 8 taps of FFE and 3 taps of DFE at the receiver. Post-Layout Analysis The Allegro CAD design was translated into an Ansoft Neutral File format (.anf) using Ansoft links. The translated PWB layout was then imported into Ansoft’s SIwave fullwave package and PWB extractor tool. The package and PWB extractor tool was used to create a Touchstone S-parameter file that included the exact layout of each lane analyzed. A differential pair for the 10 Gb/s (5 GHz) lane is shown in Figure 17 for the Blade and switch cards.
A B Figure 17: A: SIwave isometric view of the extracted differential pair on the Blade card. B: SIwave top-down view of the Switch card. The post-layout model is shown in Figure 18 and consists of the three SIwave models, SMP connector models, and a high speed connector model. A Touchstone file was created for each PWB in the system (Blade, Switch, and Backplane); these were used to model the channel in lieu of w-elements and discreet vias. The full-wave package and PWB extraction tool performs a 2D FEM solution on all planar objects within the PWB and combines this with a Method of Moments solution for the signal traces. The final solution incorporates the fabricated board including the stack-up, plane geometries, trace geometries, components, vias, via padstacks, and frequency dependent dielectrics for each layer. Upon completion of the simulation, a Touchstone file was exported to the statistical tools for rapid,statistical analysis. 0 1 2 3 4 5 0 ref 0 Port1 Port2 SWITCH HFSS Mid-Plane HFSS Blade switch switch Port3 Port4 ref ref ref 0 smp+ smp- conn- ref conn+ C sw+ blade+ sw- blade- ref 0 0 0 0 0 1 = Switch PCB Model (SIwave) 2 = Connector Model (HFSS) 3 = Mid-plane PCB Model (SIwave) 4 = Connector Model (HFSS) 5 = Blade PCB Model (SIwave) Figure 18: Post-layout circuit model. The post-layout simulation results show a very similar solution space to that of the final pre-layout simulation (2 ps difference at a BER of 1x10 -12 ). VerifEye BER results are shown in Figure 19 for the post-layout simulation. C conn+ smp+ conn- smp- ref blade blade ref ref 0 0
Page 1 and 2: DesignCon 2008 BladeServer 10 Gb/s
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